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Conventional two-level as well as multilevel voltage-source-inverter topologies with a hexagonal voltage-space vector structure generate low-order harmonics in the machine terminal voltages when operated beyond the linear modulation range in variable speed drive application. Progressing from hexagonal to a higher sided polygonal voltage-space-vector structure (VSVS) suppresses significant low-order harmonics throughout the modulation range. In addition, the linear modulation range will also be enhanced very near to the base speed. In this paper, for the first time, the generation of a multilevel 24-sided VSVS using a single dc source for induction-motor drives is proposed. A cascaded topology with a dc-source-fed flying-capacitor inverter and two low-voltage capacitor-fed H-bridge cells forms the power circuit. The features and advantages of the proposed scheme are validated through experimental results and discussions. [ABSTRACT FROM AUTHOR]

This paper proposes an analytical procedure for computation of all pairs of valid switching angles used in pattern generation in five-level H-bridge cascaded inverters. The proposed procedure eliminates harmonic components from inverter output voltage and, for each harmonic, returns the exact boundaries of all valid modulation index intervals. Due to its simple mathematical formulation, it can be easily implemented in real time using a digital signal processor or a field-programmable gate array. In this paper, after a detailed description of the method, simulation and experimental results demonstrate the high quality of achievable results. [ABSTRACT FROM PUBLISHER]

Traditional model predictive control cost functions, when utilizing long prediction horizons ( $N\geq 10$) in power inverter applications, have demonstrated harmonic performances approaching that of schemes based on offline-generated optimal pulse patterns. However, long prediction horizons often prohibitively increase computational load. A different approach to maximizing harmonic performance is taken in this paper. It is shown that shaping the output voltage spectra using a simple feedback mechanism can significantly reduce the length of the required prediction horizon, facilitating a feasible computational load. When a short-horizon cost function is augmented by the feedback mechanism an excellent tradeoff between harmonic performance and switching loss is achieved, even with a prediction horizon of one. It is also shown that the feedback mechanism can be used to improve input reference tracking. Experimental verification of the proposed modulator is performed on a two-level three-phase inverter. [ABSTRACT FROM AUTHOR]

In this paper, a novel cascaded seven-level inverter topology with a single input source integrating switched-capacitor techniques is presented. Compared with the traditional cascade multilevel inverter, the proposed topology replaces all the separate dc sources with capacitors, leaving only one H-bridge cell with a real dc voltage source and only adds two charging switches. The capacitor charging circuit contains only power switches, so that the capacitor charging time is independent of the load. The capacitor voltage can be controlled at a desired level without complex voltage control algorithm and only use the most common carrier phase-shifted sinusoidal pulse width modulation strategy. The operation principle and the charging–discharging characteristic analysis are discussed in detail. A 1-kW experimental prototype is built and tested to verify the feasibility and effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

This paper presents a harmonic elimination technique based on a three-level dodecagonal space vector structure for open-end winding induction motor (IM) drives with a single-dc supply. Advantages of dodecagonal space vector switching and multilevel inverters are achieved with a single-dc supply. A dc supply-fed three-level flying capacitor (FC) inverter feeds active power to one end of the IM winding terminals and H-bridge connected capacitors eliminate fifth- and seventh-order harmonics from the other end. A pulsewidth modulation (PWM) technique is developed to switch the three-level dodecagonal space vectors and simultaneously control the H-bridge capacitors at 0.1445V\text{dc}. The fifth- and seventh-order harmonics are eliminated for the full modulation range of the three-level FC inverter, including the extreme 6-step operation. An increase in the linear modulation range has been achieved, resulting in improved dc bus utilization. Harmonic elimination is achieved by increasing switching frequency of the low-voltage capacitor connected H-bridge inverter; thus, switching frequency for the high-voltage dc supply-fed FC inverter is not increased. Using the proposed scheme, the instantaneous phase voltage never exceeds \frac23V\text{dc} (maximum phase voltage applied for hexagonal space vector structure) for which the machine windings are rated. Additionally, the proposed inverter has also been shown to operate for field oriented control of the open-end winding IM drive. [ABSTRACT FROM AUTHOR]

Multilevel converters have received more attention recently. Multilevel converters can be used not only in high-voltage high-power applications, but also in energy storage systems, thanks to reduced harmonics and electromagnetic interferences. State-of-charge (SoC) balancing of the storage system cells within cascaded multilevel inverters, e.g., batteries, can be one of the challenges in practical applications. Different methods have been studied and reported in technical literature. However, the SoC balancing is still a challenging issue. In this paper, a new method is proposed to solve this problem by applying several clever but simple changes to the staircase modulation switching scheme without changing the output waveform properties. Validations for this simple method were performed through simulation and experimental prototype. Despite the simplicity of the method, the simulation and experimental results show that SoC balancing of the cells has significantly improved. [ABSTRACT FROM PUBLISHER]

The cost reduction of power-electronic devices, the increase in their reliability, efficiency, and power capability, and lower development times, together with more demanding application requirements, has driven the development of several new inverter topologies recently introduced in the industry, particularly medium-voltage converters. New more complex inverter topologies and new application fields come along with additional control challenges, such as voltage imbalances, power-quality issues, higher efficiency needs, and fault-tolerant operation, which necessarily requires the parallel development of modulation schemes. Therefore, recently, there have been significant advances in the field of modulation of dc/ac converters, which conceptually has been dominated during the last several decades almost exclusively by classic pulse-width modulation (PWM) methods. This paper aims to concentrate and discuss the latest developments on this exciting technology, to provide insight on where the state-of-the-art stands today, and analyze the trends and challenges driving its future. [ABSTRACT FROM PUBLISHER]

Multilevel inverters are gaining more attention in ac drive application due to their many attractive features. In the case of conventional neutral-point-clamped (NPC) or flying capacitor multilevel inverter configurations, active switches are connected in series to produce multilevel output voltage waveform. Therefore, if any one switch fails, the entire configuration has to be shut down; this will reduce the reliability of the system. A dual three-level inverter configuration for induction motor drive is proposed in this paper to improve reliability of the system. This topology is developed by feeding four-pole induction motor stator winding with four conventional two-level inverter modules. A level-shifted carrier-based third harmonic injection pulsewidth-modulation technique is used to produce the gating signals for the proposed configuration. By providing proper phase shift between carrier waves, multilevel voltage waveform is produced across the total motor phase winding, and first center band harmonics are also canceled. Thereby, the torque ripple will be considerably reduced compared with conventional NPC five-level inverter-driven induction motor drive. Finite-element analysis (FEA) is used to estimate the torque ripple when induction motor is supplied by the proposed configuration and conventional five-level NPC inverter configuration to show the effectiveness of the proposed converter. The proposed configuration is simulated using MATLAB/Simulink and experimentally verified using a laboratory prototype with a 5-hp four-pole induction motor drive. [ABSTRACT FROM PUBLISHER]

In this paper, three overmodulation techniques for the three-to-five-phase indirect matrix converter (IMC) are proposed. The first technique utilizes only the adjacent large vectors in the sector in which the reference output voltage vector lies. The second technique improves on that by continuously adapting vector elimination in the d_2-q_2 vector space based on the output voltage requirements. The third technique utilizes the ripple in the dc link to further reduce the modulation index of the inverter stage during overmodulation. All three techniques increase the voltage transfer ratio of the three-to-five-phase IMC from 0.788 to 0.923, but with the addition of harmonics generated by a vector in the d_2-q_2 vector space of the inverter stage. Simulation and experimental results from a prototype three-to-five-phase IMC validate the three proposed overmodulation techniques. [ABSTRACT FROM AUTHOR]

Power converters using deterministic switching frequency schemes have switching noise concentrated at harmonic frequencies, resulting in enhanced electromagnetic emission. To suppress the harmonic spikes in three-phase multilevel voltage source converters, a digital control scheme based on dithered sigma–delta modulation (SDM) is proposed in this paper. Introducing a dithered sequence in an SDM varies the switching frequency randomly, resulting in the suppression of the spurious harmonic spikes in the output spectrum even with a regular control input. Although the switching frequency varies randomly, the minimum pulsewidth of the proposed scheme is the sampling time period, avoiding the minimum pulsewidth problem. Instead of a conventional scalar quantizer, the quantizer in the proposed dithered sigma–delta converter uses the principle of space vector quantization. The proposed scheme is experimentally verified on a constant $v/f$ open-loop induction motor drive for a three-level inverter realized by cascading two two-level inverters. The performance of the proposed scheme is compared with different pulsewidth modulation schemes in the entire modulation index, including the overmodulation region. [ABSTRACT FROM PUBLISHER]