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This paper presents a comparison of two modulation methods for the seven-level switched-capacitor (SC) inverter using series/parallel conversion (SCISPC). The SCISPC is a multilevel inverter which has the less number of switching devices than the conventional multilevel inverters. The level-shifted pulsewidth modulation (PWM) (LS-PWM) was applied to the seven-level SCISPC in the previous research. In this paper, the level- and phase-shifted PWM (LPS-PWM) and the LS-PWM are applied to the seven-level SCISPC, and LPS-PWM is compared with LS-PWM for the seven-level SCISPC. The LPS-PWM has both the characteristics of the phase-shifted PWM (PS-PWM) and the LS-PWM. The voltage reduction during the discharging term of the SCs is reduced by means of the shorter discharging period compared to LS-PWM. The voltage ripple of the capacitors is also reduced, which leads to higher power conversion efficiency. The difference of the two modulation methods is confirmed by the theoretical approach, simulation with PSIM, and circuit experiment. [ABSTRACT FROM PUBLISHER]

In this paper, a new zero-voltage switching and resonant core reset pulse width modulation forward converter with a simple auxiliary circuit is introduced. The proposed auxiliary circuit can be applied to both single-switch and two-switch forward converters. The main and the auxiliary mosfets of the proposed converters operate under soft switching condition independent of line and load variation. Also, due to the capability of operating at duty cycles higher than 0.5, the proposed converters can be used for wide input voltage applications. In comparison to the existing zero-voltage transition (ZVT) forward converters, this auxiliary circuit has low number of components and also does not require any additional magnetic element which has improved the power density. The proposed converter is compared with exiting ZVT forward converters in details. The converter steady-state operation is analyzed and various operating modes are explained. Also, in addition to a design example, a comprehensive design procedure is presented. The experimental results of a laboratory prototype of the converter with 85–180 V input voltage and 24 V output voltage at 150 W are provided which verify the theoretical analysis and confirm the converter operation. The overall efficiency of 93.5% is achieved for the proposed converter at full load. [ABSTRACT FROM PUBLISHER]

The main objective of this paper is to examine the operation of a fundamental buck-based three-phase single-stage ac–dc full-bridge converter. In this paper, the operation of this fundamental converter is explained and analyzed, and a procedure for the design of its key components is derived and demonstrated with an example. The performance and characteristics of the converter are shown with experimental results that have been obtained from a prototype, and general concluding remarks comparing buck-based and boost-based three-phase single-stage ac–dc full-bridge converters are made. [ABSTRACT FROM PUBLISHER]

During the design phase of a modular multilevel converter (MMC), an accurate loss evaluation of the submodule (SM) plays an important role. In this paper, a method based on the analytical description of the MMC key waveforms that allows to directly obtain the average semiconductor and capacitor losses that each SM will experience is introduced, under different operating conditions or control schemes. To verify the proposed concept, the results are compared with the losses obtained from a switched model with closed-loop control, where the analytical MMC key waveforms are approached in steady state. The proposed method provides a great flexibility and a significant reduction of the simulation/computational time otherwise needed to evaluate SM losses under various operating conditions. [ABSTRACT FROM PUBLISHER]

Cascaded converters are adopted in many power systems to manage sources and loads at different voltage levels simultaneously. DC bus capacitor is one of the key components in these converters due to its energy storage and fast response capabilities. However, the ripple current through the capacitor will influence its lifetime and the overall efficiency of the converter. Previous studies showed that the capacitor current of ac systems is optimized when the duty cycles are synchronized under in phase or antiphase condition. In this paper, the bus capacitor ripple current of cascaded two-stage converters for dc systems with different combinations of duty cycles is analyzed. It is found that the optimum capacitor current ripple varies depending on the values of individual duty cycles and the phase-shift angle between them. By properly adjusting the phase shift, the capacitor RMS current value can be reduced without affecting the converter normal operation or the need for extra sensing circuits, hence improving the energy conversion efficiency and prolonging the capacitor lifetime with relatively simple implementation. To illustrate, a case study of a two-stage dc/dc converter is carried out. A laboratory prototype converter confirmed a maximum efficiency improvement of 2.8% if the phase shift is adjusted properly when compared to the same converter with the worst case phase-shift angle. [ABSTRACT FROM AUTHOR]

In this paper, an improved model predictive control (MPC) of the modular multilevel converter (MMC) with reduced computational burden is proposed. A mathematical model of the MMC system based on the sum and difference of arm voltages are derived. Instead of determining the switching state of individual submodule (SM), the voltage levels of MMC are considered as control options based on the assumption that the SM capacitor voltages are well balanced. The further reduction of calculation effort is realized by using the tolerance band of capacitor voltages. The proposed MPC has a hierarchical structure. The cost function taking into account the ac-side current control, circulating current elimination and arm energy balancing is presented. The optimal voltage level, selected by the cost function, provides the voltage reference for the pulse width modulation modulator. The SM capacitor voltage balancing is done using a separate control loop. The proposed control strategy is investigated using an MMC high-voltage direct current system with 200 SMs in each arm in real-time simulation and hardware-in-the-loop tests. The performance of proposed method is verified by both steady-state and transient-state operations. [ABSTRACT FROM PUBLISHER]

A hybrid switched-capacitor/interleaved boost converter able to provide a high voltage gain and to cancel the input current ripple at a preselected duty cycle was recently presented in the literature. This paper extends that work by proposing an optimized switching strategy for operating conditions at other values of duty cycle. The switching strategy effect on the converter's voltage gain and input current ripple is quantified and compared against the performance under the conventional switching strategy. The approach is validated in the laboratory through hardware prototyping. [ABSTRACT FROM PUBLISHER]

This paper presents a single-phase transformerless grid-connected photovoltaic converter based on two cascaded full bridges with different dc-link voltages. The converter can synthesize up to nine voltage levels with a single dc bus, since one of the full bridges is supplied by a flying capacitor. The multilevel output reduces harmonic distortion and electromagnetic interference. A suitable switching strategy is employed to regulate the flying-capacitor voltage, improve the efficiency (most devices switch at the grid frequency), and minimize the common-mode leakage current with the help of a novel dedicated circuit (transient circuit). Simulations and experiments confirm the feasibility and good performance of the proposed converter. [ABSTRACT FROM PUBLISHER]

This paper presents the hybrid seven-level cascaded active neutral-point-clamped (ANPC)-based multilevel converter. The converter topology is the cascaded connection of a three-level ANPC converter and an H-bridge per phase. The voltage of the H-bridge is actively maintained to the required level through selection of the switching states of the converter. The topology is operated under selective harmonic elimination pulsewidth modulation (SHE-PWM), maintaining the switching frequency of the converter to a minimum. The operating principles, voltage balancing methods, and limitations of the converter are analyzed together with extensive simulation results of the topology. Experimental results from a low-power laboratory prototype are presented that verify the operation of the hybrid converter under SHE-PWM. [ABSTRACT FROM PUBLISHER]

This paper proposes a zero-voltage switching (ZVS) pulsewidth modulation (PWM) dc/dc converter with current double rectifiers to achieve ZVS for all switches under a wide range of load conditions and input voltages. Two three-level PWM circuits sharing the same power switches are adopted in the proposed converter to reduce the voltage stress of each MOSFET at Vin/2 and achieve load current sharing. Thus, the current stress and power rating at the secondary-side components are reduced. The current double rectifiers are used at the secondary side to partially cancel the output ripple current. Thus, the sizes of the magnetic components and output filter capacitance are reduced. Due to the resonant behavior by the resonant inductance and resonant capacitance at the transition interval, all switches are turned on at ZVS. The experimental results based on a 1-kW prototype are provided to verify the operation principle of the proposed converter. [ABSTRACT FROM PUBLISHER]