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This paper presents a 5-level inverter topology for open-end induction motor drives by using a single dc source. The open stator windings of the drive are supplied with a 3-level flying capacitor inverter from one end and capacitor-fed 2-level inverter from another end. The voltage ratio of the dc link to the capacitor in 2-level inverter is maintained at 4:1 ratio to generate five-level voltage output. The capacitor in 2-level inverter is balanced by the switching redundant vector combinations from both the inverters while the floating capacitors in the 3-level inverter are balanced by using redundant switching states. The proposed topology gives 5-level operation with less number of floating capacitors and power semiconductor switches compared to other existing topologies. Also, the balancing of the capacitors is independent of load power factor and modulation index. Further, the generalization of the proposed dual inverter scheme for any n-level inverter is also included in this paper. The experimental results and required analysis are also presented to validate the inverter scheme. [ABSTRACT FROM AUTHOR]

In this paper, many impedance-source inverters with coupled inductors have been investigated to obtain a high step-up boost ratio. However, the leakage inductors in these topologies induce great voltage spikes at the dc link, which will increase the voltage stress of switches. Thus, the power level of inverters is limited. Furthermore, the efficiency of the inverters can be degraded by the losses associated with leakage inductors. To address abovementioned issues, this paper proposes a family of low-spike high-efficiency Y-source inverters. The proposed inverters have the ability of eliminating voltage spikes at the dc link and recycling the leakage energy via the additional diode and capacitor. In order to show the excellent characteristics of the proposed topologies, this paper compares the performances of the proposed inverters and the improved-Y-source inverter in many aspects. Simulation and experimental results have verified the abilities of the proposed inverters. [ABSTRACT FROM AUTHOR]

Reduced switch active phase converters (APC) are cost-effective solutions for running three-phase loads from single-phase grids. This paper proposes a novel auxiliary-capacitor-based APC (AC-APC) for this application. The combination of the topological location of the auxiliary capacitor and the control of the AC-APC reduces current stress on the semiconductor devices. In this paper, a selection criterion for the optimal auxiliary capacitor value is formulated to reduce the device currents in such a way that the overall efficiency is enhanced. This paper presents a comparative analysis of converter volt-ampere (VA) rating and device power loss for conventional H-bridge active front-end and inverter-based topology, APC, and AC-APC. To evaluate the efficacy of the proposed AC-APC, an experimental study is conducted on the APC and the AC-APC feeding a 3-hp three-phase induction motor. At a full load of $\text{2.5}\,\text{kW}$ and $\text{0.8 } \text{power factor}$ , the measured maximum efficiency of the AC-APC is $2\%$ higher than that of the APC. Analytical evaluation of converter currents and device power loss are in close agreement with experimental observations. [ABSTRACT FROM AUTHOR]

This paper proposes a new dc–ac converter with a reduced number of semiconductor switches and gate drive and control circuit components. A salient feature of this inverter is its pure sinusoidal line-to-line voltages with no need for output filter. Also, the proposed inverter improves the voltage utilization factor of the input dc supply compared to the four-switch three-phase inverter (first best topology in the literature from the number of switches point of view) and standard six-switch inverter with sine pulsewidth modulation. The proposed inverter is capable of operating with a wide range of output voltages from zero to the full value of the dc input voltage by appropriately altering the instantaneous duty cycle. A three-phase universal inverter with only three power switch has been proposed in this paper for the first time ever, to our knowledge. For the purpose of providing a good compromise between fast transient response and stability, a model predictive controller is proposed. All the design expressions have been derived. A comparison with other dc–ac converters is given to show the merits of the proposed converter. Finally, satisfactory circuit operation is confirmed by experimental results from a laboratory prototype. [ABSTRACT FROM AUTHOR]

In this paper, two structures are proposed for the switched-inductor quasi-Z-source inverter. In the proposed structures to extend the voltage gain of inverter, two new switched-inductor structures are used. In the proposed structures, voltage across the capacitors in the Z-source network and in the switched-inductor is symmetric and small. The other advantage of proposed inverters is known as achieving higher voltage gain per smaller duty cycle ratio (of shoot-through). Compared with a conventional continuous input current switched-inductor quasi-Z-source inverter at the same gain voltage, there is less of a ripple of input current in the proposed inverters. In this paper, at first the both the conventional and the proposed switched-inductor Z-source inventers are thoroughly investigated to find out their governing relations. Then, the proposed Z-source inverters are compared with the conventional ones by simulating them to assess their performance efficiency. Next, applying the simple boost pulse width modulation the simulation is carried out with PSCAD/EMTDC software. After that, to evaluate the obtained results, the prototypes of the proposed inverters with 48 Vdc input voltage are used. [ABSTRACT FROM PUBLISHER]

This paper analyzes the combination in a cascaded H-bridge multilevel inverter (CHBI) based on transformers with the different turn ratios for increasing the voltage level and proposes the switching method for achieving the output voltage distribution among H-bridge cells (HBCs). The transformers used in this paper are connected to the output of the respective HBCs, and the secondary sides of all the transformers are connected in series for generating the final output voltage. Only one of the transformers, in particular, has a different turn ratio for increasing the output voltage level. In this paper, the possible turn ratio of the special transformer with a different turn ratio is discussed in detail, and a switching method based on the level-shifted switching method for the topology used in this paper is proposed. To verify the effectiveness of the proposed method, a three-phase 21-level CHBI is experimentally tested. [ABSTRACT FROM PUBLISHER]

This paper presents a new multilevel converter topology based on a variable or multilevel dc-link stage. This stage is shared by all inverter output phases, thus increasing the number of output voltage levels while reducing the overall number of active devices compared to traditional topologies; therefore, it is called a reduced multilevel converter (RMC). The converter is not capable of reducing the blocking voltage of the devices; hence, unlike other multilevel converters aimed at medium-voltage applications, this converter is interesting for low-voltage- and high-power-quality-demanding applications such as photovoltaic inverters, wind energy conversion systems, and uninterruptible power supplies. The main novelty behind the proposed concept is the basic dc cell used to generate the variable dc-link voltage, which includes a controlled path through the floating capacitors to provide the necessary degree of control to enable a shared multilevel dc link for all the output phases of the converter. The dc cells are connected in a multicell structure to increase the number of levels of the converter. A five-level version of the RMC topology is briefly compared to other five-level converters such as the five-level active neutral-point-clamped converter and the five-level flying capacitor converter. This paper presents the structure of the new topology with its operating principle, switching states, main characteristics, and experimental validation using finite-control-set model-predictive control. [ABSTRACT FROM PUBLISHER]

In this paper, new half-bridge and full-bridge topologies for a switched-boost inverter are proposed. These topologies have a high boost factor in comparison with conventional types. In addition, the proposed topologies have continuous input current and can generate zero-voltage level in output. In this paper, the operation of the proposed inverters in different operating modes is analyzed. Then, the values of inductors and capacitors are designed. Moreover, the used switching pattern and its logical diagram are introduced. A comprehensive comparison between the proposed and conventional topologies in terms of the boost factor, the number of elements, and the efficiency shows the good features of the proposed inverters. Finally, to verify correct operation of the proposed topologies and derived equations, simulation and experimental results are presented. [ABSTRACT FROM AUTHOR]

In this paper, two topologies are presented for the enhanced-boost quasi-Z-source inverters (qZSI), namely continuous input current configuration and discontinuous input current configuration of enhanced-boost qZSI with two-switched impedance networks. Similar to enhanced-boost impedance-source inverters (ZSIs), these proposed inverter topologies possess very high boost voltage inversion at low shoot-through duty ratio and high modulation index to provide an improved quality output voltage. Compared to enhanced-boost ZSIs with two-switched Z-source impedance networks, these proposed inverter topologies share common ground with source and bridge inverter, overcome the starting inrush problem, and draw continuous input current and the lower voltage across the capacitors. Moreover, the input ripple current is negligible. This paper presents the operating principles and analysis of continuous input current configuration enhanced-boost qZSI with two-switched impedance networks and compares with ZSI, switched inductor ZSI, DA/CA-qZSI, and enhanced-boost ZSIs. The theoretical analysis is done and is validated through simulation and experimental results. [ABSTRACT FROM PUBLISHER]

This paper proposes an effective sliding mode controller (SMC) for a grid-connected 7-level packed U-cell (PUC7) inverter. The aim is to design a simple controller that deals effectively with the complex control problem of the PUC7 inverter (multiobjective control problem). The selection of the control actions is achieved according to the system state error at every sampling time, regardless of the previous values, which makes the control technique model-independent. The control algorithm evaluates online two cost functions (one for each state error), which are derived on the basis of sliding mode theory, and it selects the optimal control input in order to satisfy the reaching conditions of the two cost functions. Compared with the existing solutions, the proposed SMC technique ensures lower average switching frequency by tuning the hysteresis bandwidth of the capacitor-voltage error. The fast implementation, needless of gains tuning, and simple design procedure are the main features of the proposed algorithm. Simulation and experimental results are presented to prove the effectiveness of the proposed technique in controlling the PUC7 inverter with high dynamic performance and robustness against disturbances and parameters mismatch. [ABSTRACT FROM AUTHOR]

This paper proposes a new multilevel inverter (MLI) topology that utilizes trinary sequence for the dc sources. It gives maximum output voltage level with minimum dc source and switch count when compared to other sequences, such as symmetric, natural, binary, and quasi-linear. This is due to the fact that the trinary sequence generates of all additive and subtractive combinations of input dc levels in the output voltage waveform. The concept is implemented on a 9-level asymmetric MLI using only four active devices. Multicarrier unipolar pulsewidth modulation technique is adopted to create the switching pulses. Theoretical calculation of total harmonic distortion in both voltage and current waveforms has been performed using asymptotic time domain formula. These values are compared with simulation and experimental values for different modulation indices. Power loss calculation for proposed topology is discussed with appropriate mathematical equations. [ABSTRACT FROM AUTHOR]

This paper deals with the analysis of the input dc-link voltage ripple in multilevel inverter based on H-bridge and level doubling network (LDN). The LDN is basically a half-bridge fed by a floating capacitor, with voltage self-balancing capability, recalling the concept of a flying capacitor configuration. The amplitude of the LDN voltage ripple is analytically determined considering both the low-order and the switching harmonic components. In particular, peak-to-peak distributions of voltage ripples over the fundamental period are analytically determined, making possible the design of dc-link capacitor relying only on the dc-voltage ripple requirements. The case study makes reference to negligible switching ripple in the output current. It well represents either grid connection or passive load having almost sinusoidal currents. Numerical simulations carried out by MATLAB/Simulink and a complete set of experimental verifications are given to confirm the theoretical developments. [ABSTRACT FROM AUTHOR]

In this paper, a novel structure of switched capacitor converter (SCC) is proposed. First, the basic unit of the proposed SCC is presented. After that, a generalized structure of the proposed SCC is discussed. The presented SCC uses one dc source, several switches, diodes, and capacitors to produce multistep dc boosted output voltage. The capacitors in the SCC can be charged in trinary asymmetrical pattern. A detailed comparative study between the proposed and other recently developed SCC structures is presented. It is shown that the proposed SCC can produce an output voltage level with lower total standing voltage and lower maximum switch stress voltage as compared to most of the suggested SCC structures. Further, a switched capacitor multilevel inverter (SCMLI) based on cross-switched multilevel inverter has been developed and analyzed for symmetric and asymmetric dc source configurations. For fair comparison with the existing SCMLI structures, the overall cost of the structures is compared based on a cost function (CF). The proposed SCMLI provides lower cost function/output voltage level (CF/NL) in comparison with most of the other SCMLI structures for both symmetric and asymmetric dc source configurations. Extensive experimental studies validate the operation and performance of the proposed SCMLI structure. [ABSTRACT FROM AUTHOR]

In this paper, a new topology for half-bridge Z-source inverter is proposed. The proposed topology has only one impedance network. Unlike to the conventional half-bridge inverter, the proposed topology can provide zero voltage level at the output. It also increases output voltage level and stabilizes it in the desired value. Capacitor voltage stress in the proposed topology is low, and, therefore, nominal voltage of capacitor and cost decreases. In this paper, the steady-state analysis of the proposed inverter in two new operations which are named synchronous operation of diodes and asynchronous operation of diodes is conducted based on mathematics calculations. A method to obtain high-voltage gains by cascading the Z-network and combining middle inductors is presented that leads to cost, size, and weight reduction. Comparison among the proposed converter with conventional ones shows its excellent performance. The experimental results have good agreement with analytical analysis for the proposed topology. [ABSTRACT FROM PUBLISHER]

Zero-common-mode-voltage (CMV) operation of multilevel inverters results in reduced dc-bus utilization and reduced linear modulation range. In this paper, a method to increase the linear modulation range for zero-CMV operation without increasing the dc-bus voltage using a cascaded multilevel inverter with a single dc supply is presented. Using this method, the peak fundamental output voltage can be increased from 0.499 to 0.637  \textV\text{dc} with zero CMV inside the linear modulation range. Also, various pulse width modulation (PWM) switching sequences are analyzed in this paper, and the PWM sequence that gives minimum current ripple is used for the zero-CMV operation of the inverter. The inverter topology with single dc supply is realized by cascading a two-level inverter with two floating-capacitor-fed full-bridge modules. Simulation and experimental results for steady-state and dynamic operating conditions are presented to validate the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a model predictive control technique applied to a dual-active bridge inverter where one of the bridges is floating. The proposed floating bridge topology eliminates the need for isolation transformer in a dual inverter system and therefore reduces the size, weight, and losses in the system. To achieve multilevel output voltage waveforms, the floating inverter dc-link capacitor is charged to the half of the main dc-link voltage. A finite-set model predictive control technique is used to control the load current of the converter as well as the floating capacitor voltage. Model predictive control does not require any switching sequence design or complex switching time calculations as used for space vector modulation; thus, the technique has some advantages in this application. A detailed analysis of the converter as well as the predictive control strategy is given in this paper. Simulation and experimental results to validate the approach are also presented. [ABSTRACT FROM PUBLISHER]

This paper presents a three-phase open-end winding induction motor drive. The drive consists of a three-phase induction machine with open stator phase windings and dual-bridge inverter supplied from a single dc voltage source. To achieve multilevel output voltage waveforms, a floating capacitor bank is used for the second of the dual bridges. The capacitor voltage is regulated using redundant switching states at half of the main dc-link voltage. This particular voltage ratio (2:1) is used to create a multilevel output voltage waveform with three levels. A modified modulation scheme is used to improve the waveform quality of this dual inverter. This paper also compares the losses in the dual-inverter system in contrast with a single-sided three-level neutral point clamped converter. Finally, detailed simulation and experimental results are presented for the motor drive operating as an open-loop v /f controlled motor drive and as a closed-loop field-oriented motor controller. [ABSTRACT FROM PUBLISHER]

This paper presents a new reconfiguration module for asymmetrical multilevel inverters in which the capacitors are used as the dc links to create the levels for staircase waveforms. This configuration of the multilevel converter makes a reduction in dc sources. On the other hand, it is possible to generate 13 levels with lower dc sources. The proposed module of the multilevel inverter generates 13 levels with two unequal dc sources (2VDC and 1VDC). It also involves two chargeable capacitors and 14 semiconductor switches. The capacitors are self-charging without any extra circuit. The lower number of components makes it desirable to be used in wide range of applications. The module is schematized as two back-to-back T-type inverters and some other switches around it. Also, it can be connected as a cascade modular which leads to a modular topology with more voltage levels at higher voltages. The proposed module makes the inherent creation of the negative voltage levels without any additional circuit (such as H-bridge circuit). Nearest level control switching modulation scheme is applied to achieve high-quality sinusoidal output voltage. Simulations are executed in MATLAB/Simulink and a prototype is implemented in the power electronics laboratory in which the simulation and experimental results show a good performance. [ABSTRACT FROM AUTHOR]

In this paper, a fixed switching frequency model predictive current controller is designed and implemented on a sensorless five-level packed U-cell (PUC5) inverter interfacing the utility. The predictive control methodology is based on a voltage vector generation technique for the cost function optimization by nullifying its derivative. The aim of the controller is to allow a fixed-frequency operation with no iterations while operating as a utility line current regulator. A pulsewidth modulator based on employing PUC5 redundant switching states fixes the PUC5 auxiliary dc bus capacitor voltage to its desired level with no necessity of a regulator; the overall technique reduces system complexity with less sensors and no loops in the predictive algorithm making it suitable for industrial applications. System discrete model is developed and experimental results verify the performance of the designed controller in making a fast response in regulating the grid current and balancing the capacitor voltage. [ABSTRACT FROM AUTHOR]

Conventional two-level as well as multilevel voltage-source-inverter topologies with a hexagonal voltage-space vector structure generate low-order harmonics in the machine terminal voltages when operated beyond the linear modulation range in variable speed drive application. Progressing from hexagonal to a higher sided polygonal voltage-space-vector structure (VSVS) suppresses significant low-order harmonics throughout the modulation range. In addition, the linear modulation range will also be enhanced very near to the base speed. In this paper, for the first time, the generation of a multilevel 24-sided VSVS using a single dc source for induction-motor drives is proposed. A cascaded topology with a dc-source-fed flying-capacitor inverter and two low-voltage capacitor-fed H-bridge cells forms the power circuit. The features and advantages of the proposed scheme are validated through experimental results and discussions. [ABSTRACT FROM AUTHOR]

Usually, the parallel-compensated inductive power transfer (IPT) topology fed by a current-source inverter is controlled through variable switching frequency and fixed 50% duty cycle method. This enables the system to operate at resonance frequency, which drifts due to load and other parameter variations. Owing to this control constraint, the load requirements are fulfilled by adding extra dc–dc chopper at the output. This paper presents a new control technique for a parallel–series/series IPT network, fed from a full-bridge current-source inverter to meet the load demand directly by an inverter. Therefore, the extra chopper stage at the output side of the converter is eliminated. The control goals are achieved through a two-loop control method, where the inner input current loop controls the source current and the outer output current loop meets the load requirements. The detailed steady-state operation, converter design, small-signal modeling, and control are reported, and experimental results obtained from a 1.6-kW lab prototype are included to verify the mathematical analysis. [ABSTRACT FROM AUTHOR]

Microinverters operating into the single-phase grid from new energy source with low-voltage output face the challenges of efficiency bottleneck and twice-line-frequency variation. This paper proposed a multilevel inverter based on bridge modular switched-capacitor (BMSC) circuits with its superiority in conversion efficiency and power density. The topology is composed of dc–dc and dc–ac stages with independent control for each stage, aiming to improve system stability and simplify the control method. The BMSC dc–dc stage, which can be expanded to synthesize more levels, not only features multilevel voltage gain but also partially replaces the original bulk input capacitor and functions as an active energy buffer to enhance power-decoupling ability between dc and ac sides. In dc–ac stage, the control strategy of optimized unipolar frequency doubling sine-wave pulse width modulation is proposed to improve the quality of output waveform. Meanwhile, the multilevel voltage phase has been optimized to further reduce the power loss. Finally, a prototype has been built and tested. Associated with the simulation, the experimental results validate the practicability of these analyses. [ABSTRACT FROM PUBLISHER]

A new pulsewidth modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is proposed in this paper. A three-level NPC inverter is completely mature and very well-established topology in high-power applications. However, the three-level NPC inverter has an inheritance problem of the neutral-point voltage unbalancing due to the split dc-link capacitors. This structure can cause large neutral-point voltage ripple. Furthermore, output currents of the three-level NPC inverter are distorted by the neutral-point voltage ripple. Therefore, the neutral-point voltage must be controlled. In this paper, a new DPWM method using two different offsets for the neutral-point ripple reduction is proposed and the effectiveness of the proposed DPWM method is verified by using the simulation and the experimental results. [ABSTRACT FROM PUBLISHER]

Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector structure have advantages, such as complete elimination of fifth and seventh harmonics, reduction in electromagnetic interference, reduction in device voltage ratings, reduction of switching frequency, extension of linear modulation range, etc., making it a viable option for high-power medium-voltage drives. This paper proposes two power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles (for the first time) with minimum number of dc-link power supplies and floating capacitor H-bridges. The first power topology is composed of two hybrid cascaded five-level inverters connected to either side of an open-end winding induction machine. Each inverter consists of a three-level neutral-point-clamped inverter, which is cascaded with an isolated H-bridge making it a five-level inverter. The second topology is for a normal induction motor. Both of these circuit topologies have inherent capacitor balancing for floating H-bridges for all modulation indexes, including transient operations. The proposed topologies do not require any precharging circuitry for startup. A simple pulsewidth modulation timing calculation method for space vector modulation is also presented in this paper. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any offline computation, lookup tables, or angle computation. Experimental results for steady-state operation and transient operation are also presented to validate the proposed concept. [ABSTRACT FROM PUBLISHER]

This paper proposes the combination of a novel modified quasi-Z-source (MqZS) inverter with a single-phase symmetrical hybrid three-level inverter in order to boost the inverter three-level output voltage. The proposed single-phase MqZS hybrid three-level inverter provides a higher boost ability and reduces the number of inductors in the source impedance, compared with both the single-phase three-level neural-point clamped quasi-Z-source inverter and the single-phase quasi-Z-source cascaded multilevel inverter. Additionally, it can be extended to obtain the nine-level output voltage by cascading two three-level pulse width modulation switching cells with a separate MqZS and a dc source, which herein is called a single-phase MqZS cascaded hybrid five-level inverter (MqZS-CHI). A modified modulation technique based on an alternative phase opposition disposition scheme is suggested to effectively control the shoot-through state for boosting the dc-link voltage and balancing the two series capacitor voltages of the MqZS. The performances of both the proposed MqZS-CHI and the modulation techniques are verified through simulation and experimental results. [ABSTRACT FROM PUBLISHER]

This paper presents a nine-level active-neutral-point-clamped (ANPC) based multilevel inverter (MLI) topology for grid-connected applications requiring only ten switches. The envisaged structure comprises two parts, namely five-level ANPC unit, and a two-level converter leg whose midpoint is used as another ac terminal. An ad hoc switching state redundancy based modulation strategy is used to ensure that the voltage across the flying capacitor is tightly balanced and is implemented using a look-up table further simplifies the control complexity. The performance and effectiveness of the proposed topology with its control scheme are validated through simulations and experimental tests. Comparison with other MLIs is included to highlight the merits of the proposed topology. From the results, it will be shown that the proposed inverter requires the least part count as compared to other topologies with the same performance and output quality. [ABSTRACT FROM PUBLISHER]

Cascaded H-bridge (CHB) multilevel inverters (MLIs) have been widely used for power electronics systems. While high-voltage blocking across power switches is not a constraint for low voltage applications, the research trend has been oriented to the design of more compact module topologies as an alternative for CHB. Despite the generation of more voltage levels with reduced switch count, the existing module topologies in recent literature take no account of the freewheeling current path during dead-time, thus, inducing multistep jumps in voltage levels and giving rise to undesirable voltage spikes. Addressing this concern, this paper proposes two symmetrical compact-module topologies for cascaded MLI, where freewheeling current path during dead-time is provided for smooth transition between voltage levels to prevent voltage spikes. The proposed 7-level and 13-level compact-modules demonstrated low number of conducting switches for all voltage levels. Comprehensive analysis and comparison with the latest module topologies are conducted. To validate the operation of the proposed compact-module topologies, simulation and experimental results are presented. [ABSTRACT FROM PUBLISHER]

This paper presents an optimized topology of 3-$\phi$ , multilevel inverter (MLI) configuration for five or higher level operation with reduced switch count. The proposed solution consists of two basic units (BUs) of multilevel converter and a T-structured 3-level inverter (3-LI). Both BUs are equally shared by the three phases maintaining symmetry among the phases. Moreover, for a higher level operation of the proposed MLI, the modifications required are at two BUs only and not at three legs of the inverter. It further helps in reducing the requirement of extra components for higher level operation compared to the conventional solutions. Furthermore, the topology also has the benefits of reduced switching and conduction loss. An algorithm is also devised to generate the switching pulses for the BUs and the 3-LI, using a carrier-based space vector modulation technique. Presented topology is compared with other existing topologies to prove its advantage. All the details regarding the operating modes and pulse width modulation techniques employed for the proposed system are given and supported by the simulation and experimental results. [ABSTRACT FROM AUTHOR]

Adding the auxiliary switches to the conventional H-bridge inverter is an effective way to eliminate the leakage current for transformerless PV systems, such as H5, H6, etc. Inspired by the newly developed embedded-switch H6 topology, a novel embedded-switch inverter (ESI) is proposed in this paper for three-phase transformerless PV systems. First, the operation principle and characteristics of the proposed ESI are analyzed. Second, the common-mode model of the three-phase ESI is established, based on which the main factors that affect the leakage current are discussed. The finding reveals that the switching states with conventional modulation strategy result in high-frequency common-mode voltage, which is the source of leakage current. In order to solve the problem, a new modulation strategy is presented for ESI to eliminate the high-frequency leakage current. Finally, the time-domain simulation and the experimental tests are carried out. The results verify the effectiveness of the proposed solution. [ABSTRACT FROM AUTHOR]

This paper proposes a family of novel flying capacitor transformerless inverters for single-phase photovoltaic (PV) systems. Each of the new topologies proposed is based on a flying capacitor principle and requires only four power switches and/or diodes, one capacitor, and a small filter at the output stage. A simple unipolar sinusoidal pulse width modulation technique is used to modulate the inverter to minimize the switching loss, output current ripple, and the filter requirements. In general, the main advantages of the new inverter topologies are: 1) the negative polarity of the PV is directly connected to the grid, and therefore, no leakage current; 2) reactive power compensation capability; and 3) the output ac voltage peak is equal to the input dc voltage (unlike neutral-point-clamped and derivative topologies, which requires twice the magnitude of the peak ac voltage). A complete description of the operating principle with modulation techniques, design guidelines, and comprehensive comparisons is presented to reveal the properties and limitations of each topology in detail. Finally, experimental results of 1-kVA prototypes are presented to prove the concept and theoretical analysis of the proposed inverter family for practical applications. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel 49-level stacked inverter topology for drives. The 49 levels are achieved by stacking three 17-level inverters. Each of the 17-level inverter is developed by cascading a flying capacitor (FC) inverter with three capacitor-fed H-bridges. The device count can be reduced by making the FC and the three cascaded H-bridges common to the dc link in each phase using selector switches in between them. The selector switches need to operate at fundamental frequency only. Also, the devices need to block very low voltages. Hence, MOSFETs can be used. This topology requires three dc sources, each of V\text{dc} /6 only, which can be replaced with stacked batteries for electric vehicle applications. The reduction in the dc voltage requirement is achieved by using a normal symmetric six-phase induction motor with parallel connection of the opposite phase windings. All the floating capacitors in the topology can be balanced irrespective of any modulation index or load power factor. Due to the high number of voltage levels, nearest level control can be used instead of pulse width modulation, which reduces the switching losses. The $dv/dt$ during the inverter operation is also less. Detailed experimental results at different speeds of operation and during transients ensure that the novel topology can be a viable option for high-power adjustable speed drives. [ABSTRACT FROM PUBLISHER]

In this paper, an improved transformerless single-phase single-stage grid-tied flying inductor inverter is presented. The negative terminal of the photovoltaic (PV) array is grounded in the improved topology, which increases reliability and suppresses the leakage current. The proposed topology has buck–boost capability without increasing the number of required components and has a high efficiency. An improved control algorithm for proper operation of the proposed topology which decreases switching losses has been investigated. Moreover, a perturbation and observation maximum power point tracking (MPPT) algorithm has been adapted to the proposed inverter, which does not utilize proportional–integral (PI) controllers, for the purpose of the MPPT. Furthermore, a design procedure of the passive elements of the converter based on the corresponding operating has been demonstrated. Simulation in MATLAB Simulink plus an experimental prototype is developed to reconfirm the designed results. Finally, a comparison study has been investigated for better clarification of the advantages and disadvantages of the proposed inverter. [ABSTRACT FROM PUBLISHER]

Photovoltaic (PV) microinverters dispense with the line frequency transformer, however at the cost of system grounding and ground leakage current problems. These have been erstwhile resolved by the topologies derived from buck, boost, buck–boost, Zeta, Watkins–Johnson, and Ćuk converters, or combinations of these. The Ćuk derived inverters, employing second-order input and output filters, offer the most efficient, lightweight, and economical solution in the class. This paper presents design and detailed operation of a Ćuk derived, common-ground PV microinverter in continuous conduction mode operation. The inverter is shown to be compatible with both linear and nonlinear loads, in stand-alone and grid-connected modes of operation. Optimal design rules of passive components are rigorously derived to ensure attenuation of input voltage ripples arising from the twin effects of switching and double-frequency output power oscillation. Additionally, the design rules also incorporate considerations of efficiency maximization and some aspects of easing control complexity. Inverter performance is experimentally validated with a 300 VA, 110 V, and 50/60 Hz laboratory prototype. [ABSTRACT FROM PUBLISHER]

This paper discusses the implementation of level-shifted and phase-shifted carrier-based modulation methods, in conjunction with a multiphase open-end winding drive topology. The considered drive is supplied using two five-phase two-level voltage source inverters (VSIs), with input provided from two isolated supplies of equal dc voltages. The topology is known to yield the same space-vector pattern as a corresponding three-level inverter in single-sided supply mode. It is shown in this paper that, with the application of a simple logic, the same phase voltage waveforms result as those obtainable with the appropriate carrier-based modulation scheme applied to the three-level VSI in single-sided supply mode. While the outcomes of the modulation techniques are the same, the open-end winding topology offers certain advantages, such as modularity and absence of capacitor voltage balancing requirements. The analysis is conducted for selected modulation methods using voltage and current waveforms, spectra Fast Fourier Transform (FFT), and total harmonic distortion as figures of merit. Theoretical considerations are verified by means of simulation and experimental results. [ABSTRACT FROM PUBLISHER]

In this paper, a new topology for Z-source inverter based on switched Z-source network is proposed. The proposed switched Z-source inverter can provide high voltage gain in low duty cycles. The continuous input current is one of the other advantages of the proposed inverter. The performance of the proposed inverter is investigated in different operating modes and the voltage and current equations of all elements and equations of critical inductance are calculated. Furthermore, the power losses and efficiency analyses are presented. The comprehensive comparison between the proposed inverter and the other conventional Z-source inverters shows its excellent performance. Finally, to prove the correct operation of the proposed topology, the experimental and simulation results using PSCAD/EMTDC software are presented. [ABSTRACT FROM PUBLISHER]

This paper presents a novel soft-switching galvanically isolated buck-boost dc–dc converter as a module-integrated converter for photovoltaic (PV) applications. It features three major operating modes: boost, normal, and buck mode. Their proper distribution over the input voltage range enables wide voltage regulation capabilities, i.e., close to those of nonisolated power optimizers. The proposed control algorithm requires only one buck-boost switching stage that performs voltage regulation by means of the switching stage reconfiguration with smooth transition between the modes. The design guidelines and the digital control system for PV applications are provided. The module-integrated converter was verified experimentally with a solar array simulator. The converter showed good maximum power point tracking performance and a peak efficiency of nearly 97%. [ABSTRACT FROM PUBLISHER]

In this paper, a new cascade switch-ladder multilevel inverter topology is presented which can generate a large number of output voltage levels. First, a fundamental switch-ladder multilevel inverter structure is described. Then, the structure of recommended cascade topology based on series connection of fundamental switch-ladder topologies is presented. To generate maximum number of levels with minimum number of switching elements, dc sources, and voltage on switches, the proposed cascade topology is optimized. Comparison results prove that the presented cascade topology requires fewer numbers of components. Also, the value of voltage rating on switches is less than other structures. Experimental results for two topologies are analyzed to verify the performance of the proposed topology. [ABSTRACT FROM PUBLISHER]

This paper presents a nine-level inverter topology for an open-end induction motor drive requiring only eight switches per phase, using two three-level inverters with two isolated dc links in a 3:1 ratio. A space-vector-based formulation is used to determine pole voltages such that both inverters supply power to the load over the full modulation range, eliminating the possibility of dc bus overcharging. Proper selection of switching states ensures that all floating capacitor voltages are kept tightly balanced. A digital state machine is used to select sequences of switching states in order to eliminate deadtime-induced pole voltage transients, further improving the output-voltage quality. A level-shifted carrier-based pulse width modulation scheme is used. The steady-state and transient performance of this topology were verified and the experimental results are included. [ABSTRACT FROM AUTHOR]

A novel flying-capacitor-clamped five-level inverter based on bridge modular switched-capacitor topology is proposed in this paper. The inverter features the switched-capacitor circuit with dc–dc boosting conversion ability and the multilevel inverter circuit with flying-capacitor-clamped performance. With the special composite structure, the number of components is cut down compared to the topology of the conventional cascaded multilevel inverter. Meanwhile, part of switches can be operated under line voltage frequency, resulting in switching loss reduction. Hence, the potential of system efficiency and power density is released due to embed switched-capacitor circuit. More importantly, the optimized carrier-based phase disposition pulse width modulation method is employed as a control strategy. Under this control strategy, the capacitor voltage self-balance can be realized and quality of output waveforms can be improved significantly. After simulation, the prototype is built to validate the correctness and practicability of the analysis. [ABSTRACT FROM AUTHOR]

Cascaded converters are adopted in many power systems to manage sources and loads at different voltage levels simultaneously. DC bus capacitor is one of the key components in these converters due to its energy storage and fast response capabilities. However, the ripple current through the capacitor will influence its lifetime and the overall efficiency of the converter. Previous studies showed that the capacitor current of ac systems is optimized when the duty cycles are synchronized under in phase or antiphase condition. In this paper, the bus capacitor ripple current of cascaded two-stage converters for dc systems with different combinations of duty cycles is analyzed. It is found that the optimum capacitor current ripple varies depending on the values of individual duty cycles and the phase-shift angle between them. By properly adjusting the phase shift, the capacitor RMS current value can be reduced without affecting the converter normal operation or the need for extra sensing circuits, hence improving the energy conversion efficiency and prolonging the capacitor lifetime with relatively simple implementation. To illustrate, a case study of a two-stage dc/dc converter is carried out. A laboratory prototype converter confirmed a maximum efficiency improvement of 2.8% if the phase shift is adjusted properly when compared to the same converter with the worst case phase-shift angle. [ABSTRACT FROM AUTHOR]

The five-phase coupled-inductor inverter is a newly proposed option for three-level five-phase inverter drives. This paper comprehensively analyzes the inverter including the coupled-inductor current, current stress on the dc-link capacitors, and a comparison of these performance aspects using three pulse width modulation (PWM) strategies. Mathematical derivations of the inverter currents and the associated current stress reveal that the current stress is not only influenced by the choice of modulation strategy, as in the neutral-point-clamped topology, but also by the value of coupled inductance; furthermore, the choice of the modulation strategy impacts the core loss of the coupled inductors. Three carrier-based PWM methods are considered: sinusoidal PWM (SPWM), and two methods with the common-mode voltage reduction (referred to as CMVR1 and CMVR2) for the five-phase coupled-inductor inverter. CMVR2 is shown to be the best solution if common-mode voltage reduction is required. The analysis demonstrates that SPWM performs better with respect to current stress and inverter losses, therefore is the preferable modulating strategy for the five-phase coupled-inductor inverter if common-mode voltage reduction is not required. The analysis is verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

This paper proposes a new three-phase modular multilevel inverter (MMLI). The proposed inverter consists of repeated modular primary cells that are connected in series configuration. Therefore, the proposed topology can be extended to get more output voltage levels by adding additional cells without increasing voltage stresses across power switches. Both sinusoidal pulsewidth modulation (SPWM) and staircase modulation are successfully applied to the proposed inverter. The proposed inverter features many advantages such as reduced number of semiconductor power switches, driver circuits, dc-voltage sources, simplified control algorithm, and reduced voltage stresses across the switches independent of output voltage level. Furthermore, the performance of the proposed inverter is studied under both open-loop and closed-loop operations for highly inductive load. Beside the obtained simulation results, a laboratory prototype has been carried out and tested to verify the control techniques and performances of the topology. Simulation and experimental results are compared together to highlight the similarity and consistence of them. [ABSTRACT FROM AUTHOR]

The reduced capability of multilevel converters with more than one intermediate node to balance the dc-link capacitors voltage, as well as the lack of standard modulation methods to improve their balancing performance, makes these converter topologies unattractive for real power applications. This is especially true when the load demands active power. One of these topologies is the five-level multipoint clamped (5L-MPC) converter. The back-to-back (B2B) configuration of two 5L-MPC converters and the use of a space vector modulation (SVM) that exploits the voltage balancing capability of the redundant switching vectors extend the operation conditions range in which a proper voltage balance can be achieved. However, if practical modulation restrictions are considered (limitation of voltage steps, dead times, switching losses, etc.), the voltage balance cannot be achieved for all operation conditions. In this paper, an SVM which takes into account practical restrictions is proposed. In order to guarantee the voltage balance at any operation condition, the grid-side rectifier exchanges reactive power with the grid-side LCL filter. Thus, the voltage balance of the dc-link is guaranteed while a unity grid-side power factor is achieved. The proposed modulation scheme and the voltage balancing strategy are experimentally validated in a 6.6 kV 1.5 MW 5L-MPC B2B converter. [ABSTRACT FROM AUTHOR]

This paper presents a closed-loop space vector modulation (SVM)-based sliding mode controller (SMC) for a three-level grid-connected neutral point clamped (3L-NPC) inverter. The nonlinear SMC based on Gao's reaching law has been designed to control the grid current and inject desired amount of active and reactive power into the network. Due to using single dc source at the NPC inverter dc bus, neutral point voltage is controlled through redundant switching states and instantaneous dc voltage feedback integrated into SVM technique. Meanwhile, there is no external voltage controller involved, thus no associated fine tuning issues are existed. The performance of the proposed hybrid controller to inject a desired active/reactive power to the grid is investigated through external perturbations such as change in the line current amplitude/phase shift, ac voltage fluctuation, as well as dc voltage variation. Full converter state-space model was developed and simulated. Experimental results are provided to verify the fast dynamic performance, low content of line current THD%, and good voltage balancing of dc bus capacitors of the NPC inverter. [ABSTRACT FROM AUTHOR]

Multiterminal converters eliminate using several single-input-single-output converters and simplify their topologies and reduce their cost. In this paper, a new family of multi-input converters based on three switches leg is introduced. Inputs of the proposed converters are similar and they are topologically interchangeable and have boost or buck operation modes. The proposed converter has one output that operates as an inverter. Here, all operating modes of the proposed converters and their effects on each other are investigated, in details. Also, an appropriate switching technique for the converters is given. A detailed comparison between conventional and proposed two-input converters is also presented. A two-input, one-output prototype converter has been implemented to validate the given analyses and to verify the proposed converter's performance. The experimental results are in good agreement with the theoretical and simulated analyses. [ABSTRACT FROM AUTHOR]

In this paper, a novel topology of six-level inverters for a medium-voltage high-power applications is proposed, which consists of inner flying-capacitor inverter (FCI) units and outer two-level inverter units. The proposed topology can reduce the number of devices, components, and isolated sources compared with the existing ones in the case of the same number of output voltage steps, which result in a reduction of the size and weight of the inverters. Also, the total power loss of the proposed topology is lower than that of the diode-clamped inverter (DCI) and FCI. Besides, the estimated cost of the proposed topology is about 60.5% and 81.3% compared with the DCI and FCI, respectively. In addition, the modulation technique and the control strategy for the dc-link capacitor and flying-capacitor voltages are developed for the proposed topology. The effectiveness of the proposed six-level inverter for the medium-voltage applications has been verified by simulation results. Also, the feasibility of the proposed inverter has been proved by experimental results for the prototype at the laboratory. [ABSTRACT FROM AUTHOR]

This paper presents a finite-control-set model predictive control (FCS-MPC) for grid-tied packed U cells (PUC) multilevel inverter (MLI). The system under study consists of a single-phase 3-cells PUC inverter connected to the grid through filtering inductor. The proposed competitive topology allows the generation of 7-level output voltage with reduction of passive and active components compared to the conventional MLIs. The aim of the proposed FCS-MPC technique is to achieve, under various operating conditions, grid-tied current injection with unity power factor and low total harmonic distortion while balancing the capacitor voltage. Parameters’ sensitivity analysis was also conducted. The study is conducted on a low-power case study single-phase 3-cells PUC inverter and with possible extension to higher number of cells. Theoretical analysis, simulation, and experimental results are presented and compared. [ABSTRACT FROM AUTHOR]

In this paper, a novel cascaded seven-level inverter topology with a single input source integrating switched-capacitor techniques is presented. Compared with the traditional cascade multilevel inverter, the proposed topology replaces all the separate dc sources with capacitors, leaving only one H-bridge cell with a real dc voltage source and only adds two charging switches. The capacitor charging circuit contains only power switches, so that the capacitor charging time is independent of the load. The capacitor voltage can be controlled at a desired level without complex voltage control algorithm and only use the most common carrier phase-shifted sinusoidal pulse width modulation strategy. The operation principle and the charging–discharging characteristic analysis are discussed in detail. A 1-kW experimental prototype is built and tested to verify the feasibility and effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

For cascaded multilevel inverter topologies with a single dc supply, closed-loop capacitor voltage control is necessary for proper operation. This paper presents zero and reduced common-mode voltage (CMV) operation of a hybrid cascaded multilevel inverter with predictive capacitor voltage control. Each phase of the inverter is realized by cascading two- three-level flying capacitor inverters with a half-bridge module in between. For the presented inverter topology, there are redundant switching states for each inverter voltage levels. By using these switching state redundancies, for every sampling instant, a cost function is evaluated based on the predicted capacitor voltages for each phase. The switching state that minimizes cost function is treated as the best and is switched for that sampling instant. The inverter operates with zero CMV for a modulation index upto 86%. For modulation indices from 86% to 96%, the inverter can operate with reduced CMV magnitude (Vdc/18) and reduced CMV switching frequency using the new space-vector pulsewidth modulation (SVPWM) presented herein. As a result, the linear modulation range is increased to 96% as compared to 86% for zero CMV operation. Simulation and experimental results are presented for the inverter topology for various steady state and transient operating conditions by running an induction motor drive with open loop $V/f$ control scheme. [ABSTRACT FROM PUBLISHER]

In this paper, a model-predictive control (MPC) has been designed and implemented on the packed U-cell (PUC) inverter, which has one isolated dc source and one capacitor as an auxiliary dc link. The MPC is designed to regulate the capacitor voltage at the desired magnitude to have seven voltage levels at the output of the inverter. Since grid-connected application is targeted by this application, the inverter should be capable of supplying requested amount of active and reactive power at the point of common coupling (PCC) as well. Therefore, MPC should also consider the line-current control to monitor the exchange of reactive power with the grid while injecting appropriate active power at low total harmonic distortion (THD). Various experimental tests including change in dc-source voltage, active power variation, and operation at different power factor (PF) have been performed on a laboratory prototype to validate the good performance obtained by the proposed MPC. The dynamic performance of the controller during sudden changes in dc capacitor voltage, supply current, and PF demonstrates the fast and accurate response and the superior operation of the proposed controller. [ABSTRACT FROM PUBLISHER]