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A space vector modulation (SVM) technique of a dual-inverter system for an open-end winding motor drive is described in this paper, where one inverter has a battery power source and the other has an only capacitor across the dc bus. The SVM must be achieved to operate the motor with field-oriented control and simultaneously to control the capacitor voltage at a constant value by using redundant switching states of the dual-inverter system. The control of the capacitor voltage is carried out by selecting a charging or a discharging mode in each redundant switching state, taking the instantaneous motor power factor into account. In addition, it is also required to reduce the error voltage pulses, which are generated in output multilevel voltage waveforms during the dead time. The compensation method of the existing dead-time scheme and the improved SVM sequence to reduce the error voltage vectors are proposed in this paper. The proposed methods are examined through several experimental tests and are confirmed to generate superior output voltage waveforms from the viewpoint of the measured total harmonic distortion and dv/dt. [ABSTRACT FROM AUTHOR]

This paper analyzes the combination in a cascaded H-bridge multilevel inverter (CHBI) based on transformers with the different turn ratios for increasing the voltage level and proposes the switching method for achieving the output voltage distribution among H-bridge cells (HBCs). The transformers used in this paper are connected to the output of the respective HBCs, and the secondary sides of all the transformers are connected in series for generating the final output voltage. Only one of the transformers, in particular, has a different turn ratio for increasing the output voltage level. In this paper, the possible turn ratio of the special transformer with a different turn ratio is discussed in detail, and a switching method based on the level-shifted switching method for the topology used in this paper is proposed. To verify the effectiveness of the proposed method, a three-phase 21-level CHBI is experimentally tested. [ABSTRACT FROM PUBLISHER]

This paper proposes an effective sliding mode controller (SMC) for a grid-connected 7-level packed U-cell (PUC7) inverter. The aim is to design a simple controller that deals effectively with the complex control problem of the PUC7 inverter (multiobjective control problem). The selection of the control actions is achieved according to the system state error at every sampling time, regardless of the previous values, which makes the control technique model-independent. The control algorithm evaluates online two cost functions (one for each state error), which are derived on the basis of sliding mode theory, and it selects the optimal control input in order to satisfy the reaching conditions of the two cost functions. Compared with the existing solutions, the proposed SMC technique ensures lower average switching frequency by tuning the hysteresis bandwidth of the capacitor-voltage error. The fast implementation, needless of gains tuning, and simple design procedure are the main features of the proposed algorithm. Simulation and experimental results are presented to prove the effectiveness of the proposed technique in controlling the PUC7 inverter with high dynamic performance and robustness against disturbances and parameters mismatch. [ABSTRACT FROM AUTHOR]

This paper presents the current control design procedure of a single-phase grid-tied five-level packed U-cell inverter (PUC5) with an LCL output filter. The PUC5 inverter is used as an interface of renewable energy sources, such as solar applications. The LCL filter is calculated according to the grid-tied operation and converter ratings. An optimal controller, based on a linear quadratic regulator with integral action, is designed to inject a sinusoidal current with low harmonic distortion at unity power factor. For that design, the PUC5 inverter is modelled in the D–Q frame. The sensorless voltage control is incorporated into the switching technique to balance the PUC5 capacitor voltage and generate a five-level waveform at the output. Experimental tests are performed on a laboratory benchmark to confirm the theoretical design. The results prove the efficiency and accuracy of the adopted control strategy in a steady state and under transients of grid current, grid inductance, ac and dc voltage amplitudes. [ABSTRACT FROM AUTHOR]

Zero-common-mode-voltage (CMV) operation of multilevel inverters results in reduced dc-bus utilization and reduced linear modulation range. In this paper, a method to increase the linear modulation range for zero-CMV operation without increasing the dc-bus voltage using a cascaded multilevel inverter with a single dc supply is presented. Using this method, the peak fundamental output voltage can be increased from 0.499 to 0.637  \textV\text{dc} with zero CMV inside the linear modulation range. Also, various pulse width modulation (PWM) switching sequences are analyzed in this paper, and the PWM sequence that gives minimum current ripple is used for the zero-CMV operation of the inverter. The inverter topology with single dc supply is realized by cascading a two-level inverter with two floating-capacitor-fed full-bridge modules. Simulation and experimental results for steady-state and dynamic operating conditions are presented to validate the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a model predictive control technique applied to a dual-active bridge inverter where one of the bridges is floating. The proposed floating bridge topology eliminates the need for isolation transformer in a dual inverter system and therefore reduces the size, weight, and losses in the system. To achieve multilevel output voltage waveforms, the floating inverter dc-link capacitor is charged to the half of the main dc-link voltage. A finite-set model predictive control technique is used to control the load current of the converter as well as the floating capacitor voltage. Model predictive control does not require any switching sequence design or complex switching time calculations as used for space vector modulation; thus, the technique has some advantages in this application. A detailed analysis of the converter as well as the predictive control strategy is given in this paper. Simulation and experimental results to validate the approach are also presented. [ABSTRACT FROM PUBLISHER]

This paper presents a three-phase open-end winding induction motor drive. The drive consists of a three-phase induction machine with open stator phase windings and dual-bridge inverter supplied from a single dc voltage source. To achieve multilevel output voltage waveforms, a floating capacitor bank is used for the second of the dual bridges. The capacitor voltage is regulated using redundant switching states at half of the main dc-link voltage. This particular voltage ratio (2:1) is used to create a multilevel output voltage waveform with three levels. A modified modulation scheme is used to improve the waveform quality of this dual inverter. This paper also compares the losses in the dual-inverter system in contrast with a single-sided three-level neutral point clamped converter. Finally, detailed simulation and experimental results are presented for the motor drive operating as an open-loop v /f controlled motor drive and as a closed-loop field-oriented motor controller. [ABSTRACT FROM PUBLISHER]

In this paper, a fixed switching frequency model predictive current controller is designed and implemented on a sensorless five-level packed U-cell (PUC5) inverter interfacing the utility. The predictive control methodology is based on a voltage vector generation technique for the cost function optimization by nullifying its derivative. The aim of the controller is to allow a fixed-frequency operation with no iterations while operating as a utility line current regulator. A pulsewidth modulator based on employing PUC5 redundant switching states fixes the PUC5 auxiliary dc bus capacitor voltage to its desired level with no necessity of a regulator; the overall technique reduces system complexity with less sensors and no loops in the predictive algorithm making it suitable for industrial applications. System discrete model is developed and experimental results verify the performance of the designed controller in making a fast response in regulating the grid current and balancing the capacitor voltage. [ABSTRACT FROM AUTHOR]

In this paper, a three-level quasi-switched boost T-type inverter (3L qSBT2I) is proposed. A new pulse-width modulated (PWM) control method is presented to reduce the inductor current ripple of the qSBT2 I. In the introduced PWM technique, the shoot-through duty cycle is maintained constant to keep the modulation index as high as possible. Then, the only control parameters of the qSBT2I are the duty cycles of the two additional switches. By controlling the duty cycles of the two additional switches, the voltage gain of the proposed qSBT2 I can be improved to a value larger than that of the conventional 3L impedance source inverters. The steady-state analysis, operating principles, and comparisons with the impedance source-based 3L inverters are presented. A 1-kW prototype is constructed to verify the operating principle of the 3L qSBT2I. An indirect dc-link voltage regulator and a capacitor voltage-balance controller are applied to the proposed qSBT2I. Simulation and experimental results are presented. [ABSTRACT FROM AUTHOR]

Microinverters operating into the single-phase grid from new energy source with low-voltage output face the challenges of efficiency bottleneck and twice-line-frequency variation. This paper proposed a multilevel inverter based on bridge modular switched-capacitor (BMSC) circuits with its superiority in conversion efficiency and power density. The topology is composed of dc–dc and dc–ac stages with independent control for each stage, aiming to improve system stability and simplify the control method. The BMSC dc–dc stage, which can be expanded to synthesize more levels, not only features multilevel voltage gain but also partially replaces the original bulk input capacitor and functions as an active energy buffer to enhance power-decoupling ability between dc and ac sides. In dc–ac stage, the control strategy of optimized unipolar frequency doubling sine-wave pulse width modulation is proposed to improve the quality of output waveform. Meanwhile, the multilevel voltage phase has been optimized to further reduce the power loss. Finally, a prototype has been built and tested. Associated with the simulation, the experimental results validate the practicability of these analyses. [ABSTRACT FROM PUBLISHER]

A new pulsewidth modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is proposed in this paper. A three-level NPC inverter is completely mature and very well-established topology in high-power applications. However, the three-level NPC inverter has an inheritance problem of the neutral-point voltage unbalancing due to the split dc-link capacitors. This structure can cause large neutral-point voltage ripple. Furthermore, output currents of the three-level NPC inverter are distorted by the neutral-point voltage ripple. Therefore, the neutral-point voltage must be controlled. In this paper, a new DPWM method using two different offsets for the neutral-point ripple reduction is proposed and the effectiveness of the proposed DPWM method is verified by using the simulation and the experimental results. [ABSTRACT FROM PUBLISHER]

This paper proposes the combination of a novel modified quasi-Z-source (MqZS) inverter with a single-phase symmetrical hybrid three-level inverter in order to boost the inverter three-level output voltage. The proposed single-phase MqZS hybrid three-level inverter provides a higher boost ability and reduces the number of inductors in the source impedance, compared with both the single-phase three-level neural-point clamped quasi-Z-source inverter and the single-phase quasi-Z-source cascaded multilevel inverter. Additionally, it can be extended to obtain the nine-level output voltage by cascading two three-level pulse width modulation switching cells with a separate MqZS and a dc source, which herein is called a single-phase MqZS cascaded hybrid five-level inverter (MqZS-CHI). A modified modulation technique based on an alternative phase opposition disposition scheme is suggested to effectively control the shoot-through state for boosting the dc-link voltage and balancing the two series capacitor voltages of the MqZS. The performances of both the proposed MqZS-CHI and the modulation techniques are verified through simulation and experimental results. [ABSTRACT FROM PUBLISHER]

This paper presents a nine-level active-neutral-point-clamped (ANPC) based multilevel inverter (MLI) topology for grid-connected applications requiring only ten switches. The envisaged structure comprises two parts, namely five-level ANPC unit, and a two-level converter leg whose midpoint is used as another ac terminal. An ad hoc switching state redundancy based modulation strategy is used to ensure that the voltage across the flying capacitor is tightly balanced and is implemented using a look-up table further simplifies the control complexity. The performance and effectiveness of the proposed topology with its control scheme are validated through simulations and experimental tests. Comparison with other MLIs is included to highlight the merits of the proposed topology. From the results, it will be shown that the proposed inverter requires the least part count as compared to other topologies with the same performance and output quality. [ABSTRACT FROM PUBLISHER]

Cascaded H-bridge (CHB) multilevel inverters (MLIs) have been widely used for power electronics systems. While high-voltage blocking across power switches is not a constraint for low voltage applications, the research trend has been oriented to the design of more compact module topologies as an alternative for CHB. Despite the generation of more voltage levels with reduced switch count, the existing module topologies in recent literature take no account of the freewheeling current path during dead-time, thus, inducing multistep jumps in voltage levels and giving rise to undesirable voltage spikes. Addressing this concern, this paper proposes two symmetrical compact-module topologies for cascaded MLI, where freewheeling current path during dead-time is provided for smooth transition between voltage levels to prevent voltage spikes. The proposed 7-level and 13-level compact-modules demonstrated low number of conducting switches for all voltage levels. Comprehensive analysis and comparison with the latest module topologies are conducted. To validate the operation of the proposed compact-module topologies, simulation and experimental results are presented. [ABSTRACT FROM PUBLISHER]

Compared with multilevel space vector modulation, level-shifted multicarrier sinusoidal pulsewidth modulation (SPWM) for nested neutral point-clamped (NNPC) inverters requires much less calculations and implementation efforts, but the existing conventional SPWM cannot suppress the severe flying-capacitor (FC) voltage ripples under low output-frequency conditions. In order to solve this problem, a multicarrier-based PWM strategy with complete voltage balance control (VBC) capacity is proposed in this paper. For NNPC inverters operating under low output-frequency conditions, two preprocessing steps, the zero-sequence injection and the modulation-signal rearrangement, are proposed before the comparisons between level-shifted carriers and modulating signals. These preprocessing steps make the average currents flowing through FCs zero, which is beneficial to greatly reduce the FC voltage ripples under low output-frequency conditions. Together with additional VBC, the proposed modulation can assure the FC voltages balanced under the entire output-frequency conditions. Principles and implementation processes of proposed modulation techniques and VBC methodsare elaborated in detail and compared with conventional modulation methods. Both simulation results from a 5-MVA system and experimental results based on a 5-kVA platform are presented to verify the effectiveness. [ABSTRACT FROM AUTHOR]

This paper proposes a high-efficiency two-stage three-level grid-connected photovoltaic (PV) inverter. The proposed two-stage inverter comprises a three-level step-up converter and a three-level inverter. The three-level step-up converter not only improves the power-conversion efficiency by lowering the voltage stress but also guarantees the balancing of the dc-link capacitor voltages using a simple control algorithm; it also enables the proposed inverter to satisfy the VDE 0126-1-1 standard of leakage current. The three-level inverter minimizes the overall power losses with zero reverse-recovery loss. Furthermore, it reduces harmonic distortion, the voltage ratings of the semiconductor device, and the electromagnetic interference by using a three-level circuit configuration; it also enables the use of small and low-cost filters. To control the grid current effectively, we have used a feed-forward nominal voltage compensator with a mode selector; this compensator improves the control environment by presetting the operating point. The proposed high-efficiency two-stage three-level grid-connected PV inverter overcomes the low efficiency problem of conventional two-stage inverters, and it provides high-power quality with maximum efficiency of 97.4%. Using a 3-kW prototype of the inverter, we have evaluated the performance of the model and proved its feasibility. [ABSTRACT FROM PUBLISHER]

This paper presents the design and implementation of a simple neutral point potential (NPP) regulator for a three-level diode-clamped inverter employing a sine-triangle regulator in conjunction with a closed-loop controller with reduced switching losses. The regulator principle is based on adding a continuous variable offset voltage which regulates the midpoint potential of the dc bus. The novelty of the proposed NPP regulator is in the determination of the magnitude of variable offset voltage based upon the average value, peak-to-peak amplitude, total harmonic distortions, and third harmonic content in NPP. Aside from maintaining dc-bus voltage balance, the proposed regulator leads to a significant reduction in the voltage distortion at the NP, resulting in the reduction of the required dc-bus capacitance. It also reduces the switching losses of the inverter by inserting the “no-switching” zone within each half cycle of the fundamental voltage wave. Analytical, computer simulation, and experimental results verifying the approach are presented in this paper for various load power factor angles. [ABSTRACT FROM AUTHOR]

In this paper, an immune algorithm (IA) is developed for optimization of the harmonic performance of a three-phase inverter under the space-vector pulsewidth-modulation (SVPWM) control strategy. The presented algorithm employs the immune approach as the search method for finding the best optimal control vectors and action time of the three-phase inverter. As a result, the optimal control vectors and action time are calculated to minimize the objective function of the weighted total harmonic distortion of the output voltage waveforms. In addition, an experimental platform based on DSP and field-programmable gate array is built. This paper provides a detailed performance analysis of the method with comparison to the conventional SVPWM. The simulation and experimental results verify the superiority of the best control sequences generated by IA compared with the existing conventional control strategies. [ABSTRACT FROM PUBLISHER]

A new pulse width modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is developed and presented in this paper. The proposed PWM scheme not only takes advantage of the special properties available in NPC inverters, but also reduces the switching loss of the inverter along with an inherent neutral point (NP) voltage control. Based on a circuit-level decoupling concept, the NPC inverter can be decoupled into two three-level Buck converters in every defined operating section, and thereby the controller design can be simplified. The salient features of the proposed scheme, as compared with the existing carrier-based DPWM strategies, are: 1) its reduced computational processing time, 2) its capability to balance the dc-link voltage without any additional control, and 3) its reduced complexity, e.g., only one carrier wave needed for pulse width modulating. Same as a space-vector modulation, the maximum modulation index, 1.1547, can be attainable by the proposed scheme. Moreover, compared to conventional continuous sinusoidal PWM, using this technique proposed here, the switching losses of the devices can be reduced by one third. In order to explain the operation of this topology properly, the decoupling principle including the driving signal synthesis and the NP potential variation are analyzed in detail in this paper. Finally, the viability and performance of the proposed modulation scheme are shown through simulation and experimental results in a laboratory prototype. [ABSTRACT FROM PUBLISHER]

This paper presents a novel soft-switching galvanically isolated buck-boost dc–dc converter as a module-integrated converter for photovoltaic (PV) applications. It features three major operating modes: boost, normal, and buck mode. Their proper distribution over the input voltage range enables wide voltage regulation capabilities, i.e., close to those of nonisolated power optimizers. The proposed control algorithm requires only one buck-boost switching stage that performs voltage regulation by means of the switching stage reconfiguration with smooth transition between the modes. The design guidelines and the digital control system for PV applications are provided. The module-integrated converter was verified experimentally with a solar array simulator. The converter showed good maximum power point tracking performance and a peak efficiency of nearly 97%. [ABSTRACT FROM PUBLISHER]

This paper proposes a unique carrier-based pulse width modulation strategy for a three-level neutral-point-clamped inverter that works satisfactorily and with uniform convergence time over the full power factor (PF) range of the load variation. It has excellent control over capacitor voltages and mitigates low-frequency oscillations in the neutral point for the full PF range. First, an investigation is made to see how the load currents get modulated to generate compensating neutral current causing charging and discharging of dc-link capacitors. It is observed that when an additional modulating voltage signal that is in phase with the corresponding phase current is added in each phase, a neutral current is produced in the right direction which can be used to compensate for any prior unbalance in capacitor voltages. It is demonstrated that the performance of this scheme is insensitive to the load PF variation (full range from zero to unity). It performs satisfactorily throughout the entire linear modulation range and eliminates any undesirable low-frequency harmonic component in the compensating neutral current. The effectiveness of the proposed scheme is verified through simulation and experimental results by varying load PF as well as modulation index with both passive and motor loads. [ABSTRACT FROM PUBLISHER]

The high number of power semiconductors in multilevel converters makes them susceptible to failure. Therefore, one of the main concerns in utilizing multilevel inverters is their reliability. This paper proposes a new simple fault-diagnosis and fault-handling method to increase the robustness and reliability of a flying capacitor multilevel inverter (FCMLI) which is one of the most prominent multilevel inverters. The proposed method is capable of diagnosing failed switch(es) and reconfiguring the switching sequence such that the output voltage is maintained similar to a normal operation condition. The proposed scheme identifies failed switch(es) by using the information about the charging state of the capacitors and the applied switching sequence. After identifying the failed switch(es), the algorithm bypasses the failed switch(es) and converts the control signals of the faulty leg from an M -cell L-level configuration to an (M-F)-cell L -level configuration (where F is the number of failed switches). The most attractive feature of the proposed control scheme is that any number of failed switches can be tolerated, as long as the number of functional switches is higher than the minimum number of cells required to build a full-binary L-level FCMLI. Simulation and experimental results are presented that verify the effectiveness of the proposed method. [ABSTRACT FROM PUBLISHER]

In this paper, the near-state pulse width modulation (NSPWM), adapted to be used in dual-voltage source inverter (VSI) fed open-end load, is introduced primarily aiming to appreciably minimize the voltage total harmonic distortion (THD). Within the framework of the proposed method, the active time of pulses at the second inverter is relatively adjusted within switching interval (compared to the first VSI). The phase voltage harmonics are formulated for dual-inverter modulated by NSPWM; then, optimal adjustment is identified via a three-dimensional curve of phase voltage THD versus modulation index (MI) and phase angle displacement (PAD). Due to the limitation of MI in NSPWM, the desired output voltage is synthesized with modifying not only MI but also PAD between references of two VSIs. Furthermore, NSPWM inherently takes advantage of better efficiency compared to conventional space vector modulation due to switching only two phases within an interval (by clamping one phase to positive/negative dc-rail). The dual-VSI supplied by two isolated dc sources is assembled in the laboratory to experimentally evaluate the THD reduction feature of the proposed method; also, the simulation results obtained by means of a MATLAB/Simulink environment show close agreement with experimental data. [ABSTRACT FROM PUBLISHER]

A novel flying-capacitor-clamped five-level inverter based on bridge modular switched-capacitor topology is proposed in this paper. The inverter features the switched-capacitor circuit with dc–dc boosting conversion ability and the multilevel inverter circuit with flying-capacitor-clamped performance. With the special composite structure, the number of components is cut down compared to the topology of the conventional cascaded multilevel inverter. Meanwhile, part of switches can be operated under line voltage frequency, resulting in switching loss reduction. Hence, the potential of system efficiency and power density is released due to embed switched-capacitor circuit. More importantly, the optimized carrier-based phase disposition pulse width modulation method is employed as a control strategy. Under this control strategy, the capacitor voltage self-balance can be realized and quality of output waveforms can be improved significantly. After simulation, the prototype is built to validate the correctness and practicability of the analysis. [ABSTRACT FROM AUTHOR]

This paper presents a closed-loop space vector modulation (SVM)-based sliding mode controller (SMC) for a three-level grid-connected neutral point clamped (3L-NPC) inverter. The nonlinear SMC based on Gao's reaching law has been designed to control the grid current and inject desired amount of active and reactive power into the network. Due to using single dc source at the NPC inverter dc bus, neutral point voltage is controlled through redundant switching states and instantaneous dc voltage feedback integrated into SVM technique. Meanwhile, there is no external voltage controller involved, thus no associated fine tuning issues are existed. The performance of the proposed hybrid controller to inject a desired active/reactive power to the grid is investigated through external perturbations such as change in the line current amplitude/phase shift, ac voltage fluctuation, as well as dc voltage variation. Full converter state-space model was developed and simulated. Experimental results are provided to verify the fast dynamic performance, low content of line current THD%, and good voltage balancing of dc bus capacitors of the NPC inverter. [ABSTRACT FROM AUTHOR]

This paper proposes a new configuration for static ground power unit (GPU) based on the novel 25-level hybrid active neutral-point-clamped (HANPC) converter. The superiority of the proposed converter, as compared with conventional and other suggested multilevel converters, is significant decreasing the number of switches and minimizing the number of flying capacitors (FC) in converter. This improvement is possible by using suggested low-voltage submodule converter to the ANPC converter and proposed modulation method. This results in reduction of the size and cost of converter and makes it more feasible and reliable. Applying the active voltage balancing method for FC in the proposed HANPC converter guaranties fast charging and voltage-level regulation of FC without using balance booster circuit. Improving output voltage spectrum leads to inductance reduction of output L–C filter which enhances static GPU performance. The simulation and experimental results verify the validity and feasibility of the proposed converter. [ABSTRACT FROM AUTHOR]

In this paper, a novel topology of six-level inverters for a medium-voltage high-power applications is proposed, which consists of inner flying-capacitor inverter (FCI) units and outer two-level inverter units. The proposed topology can reduce the number of devices, components, and isolated sources compared with the existing ones in the case of the same number of output voltage steps, which result in a reduction of the size and weight of the inverters. Also, the total power loss of the proposed topology is lower than that of the diode-clamped inverter (DCI) and FCI. Besides, the estimated cost of the proposed topology is about 60.5% and 81.3% compared with the DCI and FCI, respectively. In addition, the modulation technique and the control strategy for the dc-link capacitor and flying-capacitor voltages are developed for the proposed topology. The effectiveness of the proposed six-level inverter for the medium-voltage applications has been verified by simulation results. Also, the feasibility of the proposed inverter has been proved by experimental results for the prototype at the laboratory. [ABSTRACT FROM AUTHOR]

This paper presents a finite-control-set model predictive control (FCS-MPC) for grid-tied packed U cells (PUC) multilevel inverter (MLI). The system under study consists of a single-phase 3-cells PUC inverter connected to the grid through filtering inductor. The proposed competitive topology allows the generation of 7-level output voltage with reduction of passive and active components compared to the conventional MLIs. The aim of the proposed FCS-MPC technique is to achieve, under various operating conditions, grid-tied current injection with unity power factor and low total harmonic distortion while balancing the capacitor voltage. Parameters’ sensitivity analysis was also conducted. The study is conducted on a low-power case study single-phase 3-cells PUC inverter and with possible extension to higher number of cells. Theoretical analysis, simulation, and experimental results are presented and compared. [ABSTRACT FROM AUTHOR]

In this paper, a novel cascaded seven-level inverter topology with a single input source integrating switched-capacitor techniques is presented. Compared with the traditional cascade multilevel inverter, the proposed topology replaces all the separate dc sources with capacitors, leaving only one H-bridge cell with a real dc voltage source and only adds two charging switches. The capacitor charging circuit contains only power switches, so that the capacitor charging time is independent of the load. The capacitor voltage can be controlled at a desired level without complex voltage control algorithm and only use the most common carrier phase-shifted sinusoidal pulse width modulation strategy. The operation principle and the charging–discharging characteristic analysis are discussed in detail. A 1-kW experimental prototype is built and tested to verify the feasibility and effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

For cascaded multilevel inverter topologies with a single dc supply, closed-loop capacitor voltage control is necessary for proper operation. This paper presents zero and reduced common-mode voltage (CMV) operation of a hybrid cascaded multilevel inverter with predictive capacitor voltage control. Each phase of the inverter is realized by cascading two- three-level flying capacitor inverters with a half-bridge module in between. For the presented inverter topology, there are redundant switching states for each inverter voltage levels. By using these switching state redundancies, for every sampling instant, a cost function is evaluated based on the predicted capacitor voltages for each phase. The switching state that minimizes cost function is treated as the best and is switched for that sampling instant. The inverter operates with zero CMV for a modulation index upto 86%. For modulation indices from 86% to 96%, the inverter can operate with reduced CMV magnitude (Vdc/18) and reduced CMV switching frequency using the new space-vector pulsewidth modulation (SVPWM) presented herein. As a result, the linear modulation range is increased to 96% as compared to 86% for zero CMV operation. Simulation and experimental results are presented for the inverter topology for various steady state and transient operating conditions by running an induction motor drive with open loop $V/f$ control scheme. [ABSTRACT FROM PUBLISHER]

This paper proposes a new space-vector pulsewidth modulation (SV-PWM) strategy for a three-level neutral point clamped inverter. The presented SV-PWM strategy makes it possible to control the neutral point voltage by optimum choice of switch sequence for any position and length of output voltage vector. The proposed solution takes into consideration the unbalance of the dc-link voltages. It also analyzes the influence of vector sequences on the predicted unbalance of the dc-link voltage. The solution allows selecting optimum vectors and their on-time durations in order to reduce quickly the dc-link voltage unbalance. The calculation of the space vector area proposed in this paper takes into consideration voltage unbalance and its influence on the length and position of vectors. The proposed approach assures properly generating the voltage output vectors, even in the case of the existing large voltage unbalance in the dc-link. The results of the experimental investigation of the proposed modulation strategy are presented in this paper. [ABSTRACT FROM PUBLISHER]

In this paper, a model-predictive control (MPC) has been designed and implemented on the packed U-cell (PUC) inverter, which has one isolated dc source and one capacitor as an auxiliary dc link. The MPC is designed to regulate the capacitor voltage at the desired magnitude to have seven voltage levels at the output of the inverter. Since grid-connected application is targeted by this application, the inverter should be capable of supplying requested amount of active and reactive power at the point of common coupling (PCC) as well. Therefore, MPC should also consider the line-current control to monitor the exchange of reactive power with the grid while injecting appropriate active power at low total harmonic distortion (THD). Various experimental tests including change in dc-source voltage, active power variation, and operation at different power factor (PF) have been performed on a laboratory prototype to validate the good performance obtained by the proposed MPC. The dynamic performance of the controller during sudden changes in dc capacitor voltage, supply current, and PF demonstrates the fast and accurate response and the superior operation of the proposed controller. [ABSTRACT FROM PUBLISHER]

Modular multilevel converter (MMC) is a promising new topology for high-voltage applications. The MMC is made of several identical submodules. For proper operation, each submodule can be considered as a controlled voltage source where capacitor’s voltage should be maintained at a certain level. Besides, the minimization of the circulating current, which does not flow to the load, is crucial for achieving stable and efficient operation of the MMC. The interrelations among the load current, circulating current, and capacitor voltages complicate the MMC control. This paper aims to achieve stable and balanced voltage and current control with reduced circulating current in various operating conditions. The proposed control uses weighted model predictive control based on a normalized cost function to select the inverter switching patterns, which control the load current, while minimizing voltage fluctuation and circulating current. The weighting factors were selected based on minimizing the load-current total harmonic distortion (THD) and circulating current. The analysis is conducted on a low-power case study of single-phase four-cells MMC with possible extension to higher number of cells. The low-power three-level prototype is designed and built to validate this proposed method. Theoretical analysis, simulation, and experimental results are presented and compared. Parameter sensitivity analysis was also conducted. They all confirm the effectiveness of the proposed control method. [ABSTRACT FROM PUBLISHER]

The flying capacitor multilevel inverter (FCMLI) is one of the well-known structures of multilevel inverters having attracted considerable attention because of its merits. In spite of its many advantages, it has some limitations such as high volume and complicated control method because of its bulky capacitors and their voltage balancing requirement. Moreover, the high number of power semiconductors required makes this structure susceptible to failure. To increase the ratio of the number of levels to the number of components, an uneven distribution of capacitor voltages has been suggested in previous reports; however, this approach complicates the control method. Up to now, almost all presented methods suffer from high computational load and/or structure-dependent algorithm. In this paper, a simple state-based and structure-independent method is proposed for capacitor voltage regulation. The proposed method is straightforward and can perform online computation of switching sequences in a computationally efficient manner without any need for stored information or look-up tables. The method is conveniently extendible to any number of cells and levels in an FCMLI structure with arbitrary dc link voltage distribution schemes. Simulation and experimental results show the effectiveness and simplicity of this method. [ABSTRACT FROM PUBLISHER]

This paper presents proportional integral direct torque control (PIDTC) and fuzzy-2 DTC (F2DTC) of the induction motor (IM) drive using space vector pulse width modulation (SVPWM) for three-level diode-clamped inverter (TDCI). The above control schemes have been implemented in the laboratory using 2 HP IM through a DSPACE DS-1104 controller. The control schemes are capable to balance the dc-link capacitor voltages of TDCI by selecting an optimum voltage vector without using an extra controller. However, the three-level PIDTC of an IM gives poor transient performance during starting, loading, and speed reversal with considerable current and voltage total harmonic distortion (THD). In addition, it takes more time to reach the steady state with large spikes on capacitor voltages during the load or speed variation. This is due to poor performance of the PI controllers (speed and torque). In F2DTC, the conventional PI controllers are replaced by Mamdani-type fuzzy-2 controllers using a centroid method with simple logical rules. The simulated and experimental performance show that F2DTC for the three-level inverter-fed IM drive provides a fast dynamic response, less current and voltage THDs, considerable less distortion in flux and torque, and fewer spikes on capacitor voltages as compared to PIDTC. [ABSTRACT FROM PUBLISHER]

This paper describes a single-phase full-bridge inverter that possesses limited current ripple at the dc link while providing a sinusoidal square power at the ac output. This is achieved through the addition of an extra pair of switches and complementary control for the full-bridge inverter. The extra switches operate to prevent the double-line frequency ripple current from flowing into the input of the inverter. In doing so, the pulsation component of the sinusoidal square output power is confined to flow between the output capacitors and the load. Thus, the dc link input only supplies the dc component of the output power. Simulation and experimental results validating the proposed solution are presented. [ABSTRACT FROM PUBLISHER]

In this paper, a novel grid-connected high step-up inverter is proposed. The topology is composed of two stages. The first stage is a single-switch high step-up dc–dc converter with bipolar outputs, and the second stage is a conventional half-bridge dc–ac grid-connected inverter. Negative grounding of the photovoltaic (PV) module has resulted in elimination of unwanted ground leakage currents in the PV system. Simple structure, employing few semiconductor switches, simple control, and high efficiency are the features of the proposed topology. Theoretical analysis and principal operation of the circuit are discussed. An experimental prototype is implemented to verify the performance of the proposed inverter. The experimental results confirm the aforementioned features and the theoretical analysis of the converter operation. [ABSTRACT FROM PUBLISHER]

In this paper, the two-input buck converter is proposed as the dc/dc stage for photovoltaic (PV) cascaded converters. This converter is attractive for this application because it is cost effective and reliable and can achieve dual maximum power point tracking (MPPT) with only one power transistor. However, due to the simplified and integrated structure, the nonlinear characteristics of the converter and the two PV arrays complicate the control. By means of a small-signal modeling, the control theme of the two PV voltages is formulated, and the effect of the nonlinearities is presented. It is shown that, while fast voltage dynamics are achieved for the first input, the second-input voltage response depends on the second-stage converter control. Simulation and experimental results are reported to validate the theoretical analysis, showing the dual MPPT capability. [ABSTRACT FROM PUBLISHER]

Local dc distribution systems or dc nanogrids for residential and commercial buildings are growing popular due to the increased focus on energy savings. Using low-voltage dc for the nanogrid provides various advantages such as easier integration with renewable sources and battery banks, increased savings, etc. Future systems would use renewable sources and storage devices to become self-sufficient in generation with bare minimum consumption from the grid. The objective of this paper is to develop an energy management system (EMS) to provide uninterrupted power supply to the dc loads and achieve self-sufficiency by minimizing grid power consumption. This is achieved by developing a control scheme for a cascaded two-stage bidirectional converter interface between the nanogrid and the ac distribution network. In addition, an empirical relation for power flow through the converter is obtained, and an optimal capacitor link voltage range is derived to achieve power transfer between rated limits. The efficacy of the proposed control algorithm for the EMS is analyzed and proved to be well suited for the self-sustained dc nanogrid. A 5-kVA prototype of the converter is designed and developed in hardware, and the system operation is verified with experimental results. [ABSTRACT FROM PUBLISHER]

This paper proposes an improved performance interactive distribution static compensator (DSTATCOM) to address the limitations of conventional current control mode (CCM) and voltage control mode (VCM) operations. The proposed interactive scheme provides smooth transfer of modes of operation while remaining connected in the distribution system. In normal operation, the DSTATCOM operates in CCM to make source currents balanced, sinusoidal, and at a unity power factor. During voltage disturbances, the CCM operation cannot improve load voltage. In that case, DSTATCOM operation is changed to VCM, which maintains a constant voltage across the sensitive loads. Hence, this interactive DSTATCOM ensures continuous, flexible, and robust operation of the load. Moreover, the filter current requirements are reduced in the proposed scheme, which reduces the losses in the filter and feeder, improves inverter efficiency, and requires a reduced-rating inverter for sag mitigation. The principle of operation and control for both operating modes is analyzed. The detailed process of the flexible transfer between the two modes is derived. Deadbeat predictive control algorithms for CCM as well as VCM operation are developed for fast operation during mode transfers. The performance of the proposed scheme is validated by both simulation and experimental results. [ABSTRACT FROM PUBLISHER]

This paper presents an effective circuit configuration of a multilevel inverter that can increase the number of output voltage levels with a reduced number of circuit components. The proposed seven-level pulsewidth-modulation inverter consists of a single dc voltage source with a series of capacitors, diodes, active switches for synthesizing output voltage levels, and an H-bridge cell. After theoretical analysis, we carry out computer-aided simulations and experiments to verify the validity of the proposed approach. Here, we also introduce a modified switching strategy to solve the capacitor voltage unbalancing that occurs in series-connected capacitors. [ABSTRACT FROM PUBLISHER]

In this paper, a predictive control scheme is proposed for the low-voltage ride-through (LVRT) enhancement of direct-driven permanent-magnet-synchronous-generator-based megawatt-level wind turbines. The proposed method uses the turbine–generator rotor inertia to store the surplus energy during the grid voltage dips. The power conversion system is realized using a three-phase diode-bridge rectifier, a three-level-boost converter, and a neutral-point-clamped (NPC) inverter. The wind turbine requirements, such as maximum power point tracking, net dc-bus voltage control, balancing of the dc capacitor voltages, and reactive power generation, are modeled as the reference control variables. The generator- and grid-side cost functions are defined to deal with these control objectives. During each sampling interval, the control goals are achieved based on the minimization of cost functions. The coordination of boost and NPC converters and the exchange of reference control variables during normal and LVRT operation are formulated such that the power converters operate in a safe mode while meeting the grid code requirements. Simulation and experimental results are presented to validate the proposed strategy. [ABSTRACT FROM PUBLISHER]

In this paper, two new topologies are proposed for multilevel inverters. The proposed topologies consist of a combination of the conventional series and the switched capacitor inverter units. The proposed topologies reduce the number of switches and isolated dc voltage sources, the variety of the dc voltage source values, and the size and cost of the system in comparison with the conventional topologies. In addition, the proposed topologies can double the input voltage without a transformer. There is no need for complicated methods to balance the capacitor voltage. The simulation and experimental results of single-phase 25- and 17-level inverters are given to prove the correct operation of the proposed topologies. [ABSTRACT FROM PUBLISHER]

In this paper, a model predictive scheme is proposed to control the grid-connected high-power four-level diode-clamped inverter. To predict the future behavior of active and reactive grid power values and dc link capacitor voltages, a discrete-time model of the inverter is developed in synchronous reference frame. The controller uses all the possible switching states of the inverter for the prediction and evaluates them using a cost function. The switching state, which minimizes the cost function, is then chosen and applied at the next sampling interval. The switching frequency minimization is also achieved by including an extra constraint in the cost function. A simplified extrapolation method with reduced computational burden is proposed to safeguard the semiconductor devices during the dynamic changes in reference power values. The performance of the proposed method is investigated with the perturbations in the grid filter and dc link parameters. The feasibility of the proposed method is verified through simulation and experimental results, showing good dynamic and steady-state performance. [ABSTRACT FROM PUBLISHER]

Loads connected to a stiff source cannot be protected from voltage disturbances using a distribution static compensator (DSTATCOM). In this paper, a new control-algorithm-based multifunctional DSTATCOM is proposed to operate in voltage control mode under stiff source. This scheme provides fast voltage regulation at the load terminal during voltage disturbances and protects critical loads. In addition, during normal operation, the generated reference load voltages allow control of the source currents. Consequently, DSTATCOM injects reactive and harmonic components of load currents to make source power factor unity. Simulation and experimental results are presented to verify the efficacy of the proposed control algorithm and multifunctional DSTATCOM. [ABSTRACT FROM PUBLISHER]

This paper proposes the pulsewidth modulation (PWM) strategy of Z-source inverters (ZSIs) with minimum inductor current ripple. In existing PWM strategy with single-phase shoot-through, the shoot-through time interval is divided into six equal parts, therefore the three phase legs bear the equal shoot-through time interval. In this manner, the allotment and arrangement of the shoot-through state is easy to realize, but the inductor current ripple is not optimized. This causes to use relatively large inductors. In the proposed PWM strategy, the shoot-through time intervals of three phase legs are calculated and rearranged according to the active state and zero state time intervals to achieve the minimum current ripple across the Z-source inductor, while maintaining the same total shoot-through time interval. The principle of the proposed PWM strategy is analyzed in detail, and the comparison of current ripple under the traditional and proposed PWM strategy is given. Simulation and experimental results on the series ZSI are shown to verify the analysis. [ABSTRACT FROM PUBLISHER]

A new scheme for nine-level voltage space-vector generation for medium-voltage induction motor (IM) drives with open-end stator winding is presented in this paper. The proposed nine-level power converter topology consists of two conventional three-phase two-level voltage source inverters powered by isolated dc sources and six floating-capacitor-connected H-bridges. The H-bridge capacitor voltages are effectively maintained at the required asymmetrical levels by employing a space vector modulation (SVPWM) based control strategy. An interesting feature of this topology is its ability to function in five- or three-level mode, in the entire modulation range, at full-power rating, in the event of any failure in the H -bridges. This feature significantly improves the reliability of the proposed drive system. Each leg of the three-phase two-level inverters used in this topology switches only for a half cycle of the reference voltage waveform. Hence, the effective switching frequency is reduced by half, resulting in switching loss reduction in high-voltage devices. The transient as well as the steady-state performance of the proposed nine-level inverter-fed IM drive system is experimentally verified in the entire modulation range including the overmodulation region. [ABSTRACT FROM PUBLISHER]

Cascaded H-bridge multilevel power electronic converters generally require several dc sources. An alternative option is to replace all the separate dc sources feeding the H-bridge cells with capacitors, leaving only one H-bridge cell with a real dc voltage source. This will yield a cost-effective converter. However, the required capacitor voltage balancing is challenging. In this paper, using the phase-shift modulation approach, a new control method for cascaded H-bridge multilevel converters fed with only one independent dc source is presented. The proposed method has a wide voltage regulation range for the replacement capacitors in the H-bridge cells. Experimental and simulation results support the proposed control method. [ABSTRACT FROM PUBLISHER]

The five-level active neutral-point (NP)-clamped (ANPC) converter is a newly emerging topology which can overcome the drawbacks of traditional NP-clamped and flying-capacitor multilevel converters. This paper presents a comprehensive theoretical analysis of the NP potential balancing issue and demonstrates that the NP potential can be naturally balanced under ideal and steady conditions. An NP potential balancing method based on zero-sequence voltage injection is presented. By calculating the average NP currents of all key zero-sequence voltages, the most appropriate zero-sequence voltage is selected to generate the demanded NP current, which can also limit the switching frequency of the series-connected insulated-gate bipolar transistors to the fundamental frequency. A three-phase five-level ANPC inverter prototype is built up, and both steady and dynamic experimental results are presented to verify the validity of this method. [ABSTRACT FROM PUBLISHER]

A neutral-point-clamped three-level inverter with small dc-link capacitors is presented in this paper. The inverter requires zero average neutral-point current for stable neutral-point voltage. The small dc-link capacitors may not maintain capacitor voltage balance, even with zero neutral-point current. This may happen due to nonlinearities present in the circuit. This requires a fast control of the neutral-point voltage. A simple carrier-based modulation strategy which allows modeling of the neutral-point voltage dynamics as a continuous function of power drawn from the inverter is proposed. This continuous model shows that the neutral-point current is proportional to the power drawn from the inverter, and it enables the use of a well-established classical control theory for the neutral-point voltage controller design. A simple proportional integral controller is designed for the neutral-point voltage control on the basis of the continuous model. The design method for optimum performance is discussed. The implementation of the proposed modulation strategy and the controller is very simple. The controller is implemented in a 7.5-kW induction machine-based drive with only 14 \mu \F dc-link capacitors. Also, the experimental results show that fast and stable performance of the neutral-point voltage controller are achieved and thus verify the validity of the proposed control approach. [ABSTRACT FROM PUBLISHER]