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A space vector modulation (SVM) technique of a dual-inverter system for an open-end winding motor drive is described in this paper, where one inverter has a battery power source and the other has an only capacitor across the dc bus. The SVM must be achieved to operate the motor with field-oriented control and simultaneously to control the capacitor voltage at a constant value by using redundant switching states of the dual-inverter system. The control of the capacitor voltage is carried out by selecting a charging or a discharging mode in each redundant switching state, taking the instantaneous motor power factor into account. In addition, it is also required to reduce the error voltage pulses, which are generated in output multilevel voltage waveforms during the dead time. The compensation method of the existing dead-time scheme and the improved SVM sequence to reduce the error voltage vectors are proposed in this paper. The proposed methods are examined through several experimental tests and are confirmed to generate superior output voltage waveforms from the viewpoint of the measured total harmonic distortion and dv/dt. [ABSTRACT FROM AUTHOR]

In a sensorless vector control method, at low speeds and self-commissioning for AC motors, it is necessary to model dead time, rise/fall time, parasitic capacitors, and semiconductors’ voltage drop accurately. In this paper, voltage drop in each phase due to the nonlinear behavior of the inverter from the control system's viewpoint is precisely modeled by using two lookup tables. These lookup tables make the proposed model robust against the dc-link voltage and carrier frequency variations in the entire current range. In conventional methods at standstill, the measured voltage in the dc current test contains the nonlinearity of two phases. Therefore, to obtain the nonlinear voltage of each inverter phase, it is assumed that the values of inverter nonlinearity voltage at both high current and low current are equal. This simplification leads to distortion in measured voltage in the low currents. However, in this paper, the voltage drop equation of each phase is solved by numerical method that is realizable in conventional processors. The results obtained in actual voltage measurement show the superiority of the proposed method over traditional methods in the low currents. The proposed method is verified by using a voltage source inverter feeding a 2.2-kW three-phase induction motor. [ABSTRACT FROM AUTHOR]

The second harmonic current compensator (SHCC) can be added into the single-phase converters for compensating the second harmonic current (SHC) and thus removing the undesired electrolytic capacitor. In this paper, a virtual impedance, which is in the form of a capacitor and a resistor connected in parallel, is introduced to be in parallel at the bus-side port of the SHCC for effectively compensating the SHC while guaranteeing the system stability. This virtual parallel impedance is realized by feeding forward the bus-side port voltage of the SHCC, and thus the SHCC can be modular designed. The closed-loop parameter design of the SHCC is also presented. A 3.3-kW prototype of a two-stage single-phase power factor correction converter is built and tested in the laboratory, and the experimental results verify the effectiveness and feasibility of the proposed control method. [ABSTRACT FROM AUTHOR]

This paper analyzes the combination in a cascaded H-bridge multilevel inverter (CHBI) based on transformers with the different turn ratios for increasing the voltage level and proposes the switching method for achieving the output voltage distribution among H-bridge cells (HBCs). The transformers used in this paper are connected to the output of the respective HBCs, and the secondary sides of all the transformers are connected in series for generating the final output voltage. Only one of the transformers, in particular, has a different turn ratio for increasing the output voltage level. In this paper, the possible turn ratio of the special transformer with a different turn ratio is discussed in detail, and a switching method based on the level-shifted switching method for the topology used in this paper is proposed. To verify the effectiveness of the proposed method, a three-phase 21-level CHBI is experimentally tested. [ABSTRACT FROM PUBLISHER]

To improve light load efficiency, a three-phase photovoltaic (PV)-based microinverter may operate in single-phase, two-phase or three-phase mode depending on the available input power. Therefore, its dc-link capacitor may be subjected to large peak-to-peak voltage ripple when operating in phase skipping mode. This paper determines the minimum value of the dc-link capacitor by allowing the maximum acceptable voltage ripple on the dc link. This allows for the use of film capacitors instead of electrolytic capacitors in order to improve the microinverter reliability. Unfortunately, higher dc-link voltage ripple introduces harmonic distortion on the inverter output current waveform if it is not compensated for by the dc-link voltage controller. This paper proposes a simple synchronous control method to regulate the dc-link voltage with the presence of large voltage ripple. The dc-link voltage controller is synchronized with the phase-locked loop and samples the average value of dc-link voltage without introducing unwanted harmonics into the voltage sense path. Experimental results were obtained from a 300-W three-phase half-bridge microinverter prototype to verify the proposed dc-link voltage control performance. Inverter output current total harmonic distortion of 1.6% was achieved even though the dc-link peak-to-peak voltage ripple reached as high as 87 V with 219-V split dc-link voltage. Dynamic response is fast enough to easily track the most extreme ramp change in input PV power. [ABSTRACT FROM PUBLISHER]

This paper presents a method for small-signal dynamic studies of power systems including utility-scale PV energy systems considering the effects of dc-side components. Existing methods commonly model a PV energy system as a dc source connected to a grid-tied inverter. This paper shows that the dc components of a PV energy system can also contribute in the dynamics of the power system in the range of small-signal studies. The paper first develops the model of a PV energy system by merging the submodels of dc- and ac-side components. Then, a method to obtain the augmented model of the power system including a PV energy system will be explained using a study system. The study system consists of a PV energy system in parallel with a synchronous generator connected to a grid. Then, based on eigenvalue analysis, verified by time-domain simulations, it is shown that the dc-link capacitor, front-end converter, and its controller can introduce oscillatory modes in subsynchronous range of frequencies. Furthermore, it is shown that the damping of the sensitive modes can significantly vary with respect to the parameters of the dc-side components. [ABSTRACT FROM PUBLISHER]

This paper proposes an effective sliding mode controller (SMC) for a grid-connected 7-level packed U-cell (PUC7) inverter. The aim is to design a simple controller that deals effectively with the complex control problem of the PUC7 inverter (multiobjective control problem). The selection of the control actions is achieved according to the system state error at every sampling time, regardless of the previous values, which makes the control technique model-independent. The control algorithm evaluates online two cost functions (one for each state error), which are derived on the basis of sliding mode theory, and it selects the optimal control input in order to satisfy the reaching conditions of the two cost functions. Compared with the existing solutions, the proposed SMC technique ensures lower average switching frequency by tuning the hysteresis bandwidth of the capacitor-voltage error. The fast implementation, needless of gains tuning, and simple design procedure are the main features of the proposed algorithm. Simulation and experimental results are presented to prove the effectiveness of the proposed technique in controlling the PUC7 inverter with high dynamic performance and robustness against disturbances and parameters mismatch. [ABSTRACT FROM AUTHOR]

This paper presents the current control design procedure of a single-phase grid-tied five-level packed U-cell inverter (PUC5) with an LCL output filter. The PUC5 inverter is used as an interface of renewable energy sources, such as solar applications. The LCL filter is calculated according to the grid-tied operation and converter ratings. An optimal controller, based on a linear quadratic regulator with integral action, is designed to inject a sinusoidal current with low harmonic distortion at unity power factor. For that design, the PUC5 inverter is modelled in the D–Q frame. The sensorless voltage control is incorporated into the switching technique to balance the PUC5 capacitor voltage and generate a five-level waveform at the output. Experimental tests are performed on a laboratory benchmark to confirm the theoretical design. The results prove the efficiency and accuracy of the adopted control strategy in a steady state and under transients of grid current, grid inductance, ac and dc voltage amplitudes. [ABSTRACT FROM AUTHOR]

Two-stage isolated battery-driven grid interface (IBDGI) with front-end three-phase dual active bridge (DAB) dc–dc converter is promising to be applied in the residential battery energy storage system for supporting photovoltaic (PV) integration, load shifting, and backup power purposes. However, the second harmonic current (SHC) caused by the pulsating power of the downstream single-phase inverter will increase the battery's degradation and the component stress of the front-end converter. In this paper, a reduction method is proposed for the IBDGI with three-phase DAB converter using a load current feedforward control. The proposed idea is to incorporate virtual impedance to the output impedance of the front-end converter. The easy-to-be-implemented method does not need to modify the original voltage closed-loop controller but suppress SHC while keeping good dynamic performance. As the first step, the small-signal model of the three-phase DAB converter is provided. The parameter sensitivity analysis is proposed to demonstrate that the SHC can be well-suppressed within $\pm \text{20}\%$ parameter error of the feedforward control. Finally, a 1 kW experiment setup is built to verify the performance of the proposed SHC reduction method. [ABSTRACT FROM AUTHOR]

A quasi-Z-source modular cascaded converter (qZS-MCC) is proposed for dc integration of high-power photovoltaic (PV) systems. The qZS-MCC comprises series-connected front-end isolated qZS half-bridge (HB) dc–dc converter submodules (SMs). With the front-end isolation, the qZS-MCC achieves high-voltage dc capability, while maintaining modularity and PV panel grounded. The post-stage qZS-HB handles the PV voltage and power flows, dc-link voltage balance, and output-series power integration. Whereas, the front-end isolation converters of all SMs perform a constant duty cycle, lowing the control complexity. There is no double-line-frequency power flowing through the dc-side PV panels, qZS inductors, and qZS capacitors in the qZS-MCC, so small qZS impedance is possible compared to the existing qZS cascaded multilevel inverter. The configuration, operating principle, power loss evaluation, and passive components design of the proposed system are investigated in this part of the paper. The system control, modeling, and corresponding verifications are stated in Part II of this paper. [ABSTRACT FROM PUBLISHER]

Zero-common-mode-voltage (CMV) operation of multilevel inverters results in reduced dc-bus utilization and reduced linear modulation range. In this paper, a method to increase the linear modulation range for zero-CMV operation without increasing the dc-bus voltage using a cascaded multilevel inverter with a single dc supply is presented. Using this method, the peak fundamental output voltage can be increased from 0.499 to 0.637  \textV\text{dc} with zero CMV inside the linear modulation range. Also, various pulse width modulation (PWM) switching sequences are analyzed in this paper, and the PWM sequence that gives minimum current ripple is used for the zero-CMV operation of the inverter. The inverter topology with single dc supply is realized by cascading a two-level inverter with two floating-capacitor-fed full-bridge modules. Simulation and experimental results for steady-state and dynamic operating conditions are presented to validate the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a model predictive control technique applied to a dual-active bridge inverter where one of the bridges is floating. The proposed floating bridge topology eliminates the need for isolation transformer in a dual inverter system and therefore reduces the size, weight, and losses in the system. To achieve multilevel output voltage waveforms, the floating inverter dc-link capacitor is charged to the half of the main dc-link voltage. A finite-set model predictive control technique is used to control the load current of the converter as well as the floating capacitor voltage. Model predictive control does not require any switching sequence design or complex switching time calculations as used for space vector modulation; thus, the technique has some advantages in this application. A detailed analysis of the converter as well as the predictive control strategy is given in this paper. Simulation and experimental results to validate the approach are also presented. [ABSTRACT FROM PUBLISHER]

This paper presents a three-phase open-end winding induction motor drive. The drive consists of a three-phase induction machine with open stator phase windings and dual-bridge inverter supplied from a single dc voltage source. To achieve multilevel output voltage waveforms, a floating capacitor bank is used for the second of the dual bridges. The capacitor voltage is regulated using redundant switching states at half of the main dc-link voltage. This particular voltage ratio (2:1) is used to create a multilevel output voltage waveform with three levels. A modified modulation scheme is used to improve the waveform quality of this dual inverter. This paper also compares the losses in the dual-inverter system in contrast with a single-sided three-level neutral point clamped converter. Finally, detailed simulation and experimental results are presented for the motor drive operating as an open-loop v /f controlled motor drive and as a closed-loop field-oriented motor controller. [ABSTRACT FROM PUBLISHER]

In this paper, a fixed switching frequency model predictive current controller is designed and implemented on a sensorless five-level packed U-cell (PUC5) inverter interfacing the utility. The predictive control methodology is based on a voltage vector generation technique for the cost function optimization by nullifying its derivative. The aim of the controller is to allow a fixed-frequency operation with no iterations while operating as a utility line current regulator. A pulsewidth modulator based on employing PUC5 redundant switching states fixes the PUC5 auxiliary dc bus capacitor voltage to its desired level with no necessity of a regulator; the overall technique reduces system complexity with less sensors and no loops in the predictive algorithm making it suitable for industrial applications. System discrete model is developed and experimental results verify the performance of the designed controller in making a fast response in regulating the grid current and balancing the capacitor voltage. [ABSTRACT FROM AUTHOR]

In this paper, the wear-out performance of an impedance-source photovoltaic (PV) microinverter (MI) is evaluated and improved based on two different mission profiles. The operating principle and hardware implementation of the MI are first described. With the experimental measurements on a 300-W MI prototype and system-level finite-element method simulations, the electrothermal models are built for the most reliability-critical components, i.e., power semiconductor devices and capacitors. The dependence of the power loss on the junction/hotspot temperature is considered, the enclosure temperature is taken into account, and the thermal cross-coupling effect between components is modeled. Then, the long-term junction/hotspot temperature profiles are derived and further translated into components’ annual damages with the lifetime and damage accumulation models. After that, the Monte Carlo simulation and Weibull analysis are conducted to obtain the system wear-out failure probability over time. It reveals that both the mission profile and the thermal cross-coupling effect have a significant impact on the prediction of system wear-out failure, and the dc-link electrolytic capacitor is the bottleneck of long-term reliability. Finally, the multimode control with a variable dc-link voltage is proposed, and a more reliable dc-link electrolytic capacitor is employed, which results in a remarkable reliability improvement for the studied PV MI. [ABSTRACT FROM AUTHOR]

In this paper, a sliding-mode control (SMC) strategy is proposed for three-phase grid-tiedLCL-filtered voltage source inverters in the natural frame. The SMC in the natural frame is based on controlling the sliding surface functions of phase-legsaandb. The sliding surface function of phase-legcis obtained from the sliding surface functions of phase-legsaandb. This eliminates the need for sensing capacitor voltage and grid current of phase-legc. The capacitor voltage references are generated by the proportional-resonant (PR) controllers which result in zero steady-state error in the grid current. The feasibility and performance of the proposed SMC strategy is investigated under steady-state, transient, unbalanced, and distorted grid conditions. Experimental results taken from a 9.8 kW system are provided to demonstrate the validity of the proposed SMC strategy. [ABSTRACT FROM AUTHOR]

In this paper, a novel integrated interleaved dual-mode time-sharing inverter (IIDMI) is proposed for grid-tied transformerless photovoltaic (PV) applications. While the dual-mode time-sharing conversion technique ensures minimum losses, the IIDMI also retains the advantages of interleaved topologies, such as low total harmonic distortion of the ac current with reduced filtering requirements, increased power density, and reduced current and thermal stresses of power devices. The leakage current problem, which is a main concern with the transformerless PV inverters, is solved by increasing the frequency of the main side band of the common-mode voltage above the resonance frequency of the common-mode impedance, while avoiding high switching losses. The current control, especially at transitions between the buck and the boost modes of operation, is highly improved by utilizing a fast-response deadbeat control scheme. The working principles of the IIDMI are explained in detail, and a 2.2-kW experimental prototype is implemented to confirm the theoretical achievements. [ABSTRACT FROM AUTHOR]

This paper investigates dc-link capacitor optimization for three-phase photovoltaic-based microinverters. This concept minimizes the storage capacitance by allowing greater voltage ripple on the dc link. Therefore, the microinverter reliability can be significantly increased by replacing electrolytic capacitors with film capacitors. However, this intentionally increased voltage ripple can introduce harmonic distortion on the output current of the inverter stage if it is not mitigated by the dc-link voltage controller. For this purpose, a robust and accurate dc-link voltage control is proposed to filter this ripple while regulating the dc-link voltage without using any additional circuit components. The experimental results on a 400-W three-phase half-bridge microinverter prototype validate the theoretical analysis of the dc-link capacitor optimization and show that a significant reduction of the dc-link capacitor requirement can be achieved. The proposed high-accuracy dc-link voltage controller is also implemented on this prototype to demonstrate very low harmonic distortion of the inverter output current while tightly regulating the dc-link voltage even during transients. [ABSTRACT FROM AUTHOR]

Due to current sensor errors, tolerance of power switching devices, and asymmetry of PWM gating driving pulses, grid-connected inverters without isolation transformer usually have certain amount of dc components injected to the ac grid. Many efforts, such as using a blocking capacitor, a current dc component feedback control, and a voltage dc component feedback control have been introduced to try to suppress the dc injection to the grid. This paper proposes a novel control strategy of suppressing dc current injection to the grid for a three-phase inverter by accurately sensing the dc component of line voltages of three-phase inverter and adding a dc component control loop. A dc suppression control scheme is presented, and the suppression performance of the proposed dc rejection method is evaluated and compared with the traditional method. Finally, the control scheme is verified on a 20-kW three-phase grid-connected inverter. [ABSTRACT FROM AUTHOR]

In this paper, a three-level quasi-switched boost T-type inverter (3L qSBT2I) is proposed. A new pulse-width modulated (PWM) control method is presented to reduce the inductor current ripple of the qSBT2 I. In the introduced PWM technique, the shoot-through duty cycle is maintained constant to keep the modulation index as high as possible. Then, the only control parameters of the qSBT2I are the duty cycles of the two additional switches. By controlling the duty cycles of the two additional switches, the voltage gain of the proposed qSBT2 I can be improved to a value larger than that of the conventional 3L impedance source inverters. The steady-state analysis, operating principles, and comparisons with the impedance source-based 3L inverters are presented. A 1-kW prototype is constructed to verify the operating principle of the 3L qSBT2I. An indirect dc-link voltage regulator and a capacitor voltage-balance controller are applied to the proposed qSBT2I. Simulation and experimental results are presented. [ABSTRACT FROM AUTHOR]

The inverter control plays a critical role in microgrid (MG) hierarchical control structure. In this paper, a dominant dynamic elimination control is studied for the voltage-controlled MG inverter. A compact control structure is designed to include separated static state feedback and feedforward terms. Benefitting from the designed control structure, the dominant dynamic can be canceled by the static feedforward control via the fundamental zero-pole cancelation principle. Thanks to the cancelation of the dominant dynamic, the load disturbance-rejection performance is improved, and the approximate unity gain from the reference to output is also achieved from the perspective of the application control layer, thereby the performance of power control for the upper application is improved. Furthermore, the strong robustness to parameter variations and low total harmonic distortion are also achieved. Comparative simulations and experiments are adopted to verify the effectiveness and superiority of the designed approach. [ABSTRACT FROM PUBLISHER]

Multilevel cascade H-bridge (CHB) converters are one of the promising solutions for medium- and large-scale grid-connected photovoltaic power plants. However, there is a lack of a complete study about their operation during voltage sags. This paper proposes a flexible control strategy for the operation of photovoltaic grid-connected CHB inverters during unbalanced voltage sags. The key novelty is that the proposed strategy is able to inject both active and reactive powers to the grid with either balanced or unbalanced currents, while ensuring that all dc-link capacitor voltages remain balanced. The simulation and experimental evaluations of a 9-kVA grid-connected seven-level CHB illustrate and validate the performance of the proposed strategy for the operation of the grid-connected CHB converter during different unbalanced voltage sags. [ABSTRACT FROM PUBLISHER]

Microinverters operating into the single-phase grid from new energy source with low-voltage output face the challenges of efficiency bottleneck and twice-line-frequency variation. This paper proposed a multilevel inverter based on bridge modular switched-capacitor (BMSC) circuits with its superiority in conversion efficiency and power density. The topology is composed of dc–dc and dc–ac stages with independent control for each stage, aiming to improve system stability and simplify the control method. The BMSC dc–dc stage, which can be expanded to synthesize more levels, not only features multilevel voltage gain but also partially replaces the original bulk input capacitor and functions as an active energy buffer to enhance power-decoupling ability between dc and ac sides. In dc–ac stage, the control strategy of optimized unipolar frequency doubling sine-wave pulse width modulation is proposed to improve the quality of output waveform. Meanwhile, the multilevel voltage phase has been optimized to further reduce the power loss. Finally, a prototype has been built and tested. Associated with the simulation, the experimental results validate the practicability of these analyses. [ABSTRACT FROM PUBLISHER]

A new pulsewidth modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is proposed in this paper. A three-level NPC inverter is completely mature and very well-established topology in high-power applications. However, the three-level NPC inverter has an inheritance problem of the neutral-point voltage unbalancing due to the split dc-link capacitors. This structure can cause large neutral-point voltage ripple. Furthermore, output currents of the three-level NPC inverter are distorted by the neutral-point voltage ripple. Therefore, the neutral-point voltage must be controlled. In this paper, a new DPWM method using two different offsets for the neutral-point ripple reduction is proposed and the effectiveness of the proposed DPWM method is verified by using the simulation and the experimental results. [ABSTRACT FROM PUBLISHER]

This paper presents a transformerless inverter topology, which is capable of simultaneously solving leakage current and pulsating power issues in grid-connected photovoltaic (PV) systems. Without adding any additional components to the system, the leakage current caused by the PV-to-ground parasitic capacitance can be bypassed by introducing a common-mode (CM) conducting path to the inverter. The resulting ground leakage current is therefore well controlled to be below the regulation limit. Furthermore, the proposed inverter can also eliminate the well-known double-line-frequency pulsating power that is inherent in single-phase PV systems. By properly injecting CM voltages to the output filter capacitors, the pulsating power can be decoupled from the dc-link. Therefore, it is possible to use long-lifetime film capacitors instead of electrolytic capacitors to improve the reliability of the PV system. The mechanism of leakage current suppression and the closed-loop control of pulsating power decoupling are discussed in this paper in detail. A 500-W prototype was also built and tested in the laboratory, and both simulation and experimental results are finally presented to show the excellent performance of the proposed PV inverter. [ABSTRACT FROM PUBLISHER]

A strategy for fault detection and tolerance on the inverter that controls power flow in variable-speed permanent-magnet generators is proposed in this paper. The performance of the proposed strategy is analyzed in two different four-wire topologies. In the first topology, the neutral point of the generator is connected to the middle point of the dc-link capacitor bank, whereas in the second topology, it is connected to a fourth leg of the inverter. The main contribution of this paper resides in the control scheme, which allows a steady operation through a fault occurrence without the need of reconfiguring neither the inverter topology nor the control algorithm. In this way, transients and the use of extra hardware components are avoided. In addition, a control loop that allows limiting the generator losses at any operation point is presented in order to protect the machine. Finally, experimental results, obtained from a laboratory prototype, validate the practical feasibility of the proposed strategy. [ABSTRACT FROM PUBLISHER]

The quasi-Z-source cascade multilevel inverter (qZS-CMI) presents many advantages over conventional CMI when applied in photovoltaic (PV) power systems. For example, the qZS-CMI provides the balanced dc-link voltage and voltage boost ability, saves one-third modules, etc. However, the qZS-CMI still cannot overcome the intermittent and stochastic fluctuation of solar power injected to the grid. This paper proposes an energy stored qZS-CMI-based PV power generation system. The system combines the qZS-CMI and energy storage by adding an energy stored battery in each module to balance the stochastic fluctuations of PV power. This paper also proposes a control scheme for the energy stored qZS-CMI-based PV system. The proposed system can achieve the distributed maximum power point track for PV panels, balance the power between different modules, and provide the desired power to the grid. A detailed design method of controller parameters is disclosed. Simulation and experimental results verify the proposed system and the control scheme. [ABSTRACT FROM PUBLISHER]

An active method for double-frequency power ripple decoupling in single-phase inverters is presented in this paper, exhibiting the main advantage of not using additional power semiconductors besides the H-bridge. The proposed method requires only two capacitors placed between the midpoint and one end of each inverter leg. An original control solution of the inverter ensures the power ripple transfer toward the two decoupling capacitors without affecting the inverter output voltage. The simple design makes the proposed solution easy to adapt for single-phase inverters in H-bridge configuration. This paper focuses on the autonomous operation mode of the inverter, detailing its operating principle and the control analysis. The system performances, including the impact of the decoupling circuit on the inverter efficiency, are assessed by means of experimental results. [ABSTRACT FROM PUBLISHER]

This paper proposes the combination of a novel modified quasi-Z-source (MqZS) inverter with a single-phase symmetrical hybrid three-level inverter in order to boost the inverter three-level output voltage. The proposed single-phase MqZS hybrid three-level inverter provides a higher boost ability and reduces the number of inductors in the source impedance, compared with both the single-phase three-level neural-point clamped quasi-Z-source inverter and the single-phase quasi-Z-source cascaded multilevel inverter. Additionally, it can be extended to obtain the nine-level output voltage by cascading two three-level pulse width modulation switching cells with a separate MqZS and a dc source, which herein is called a single-phase MqZS cascaded hybrid five-level inverter (MqZS-CHI). A modified modulation technique based on an alternative phase opposition disposition scheme is suggested to effectively control the shoot-through state for boosting the dc-link voltage and balancing the two series capacitor voltages of the MqZS. The performances of both the proposed MqZS-CHI and the modulation techniques are verified through simulation and experimental results. [ABSTRACT FROM PUBLISHER]

This paper presents a nine-level active-neutral-point-clamped (ANPC) based multilevel inverter (MLI) topology for grid-connected applications requiring only ten switches. The envisaged structure comprises two parts, namely five-level ANPC unit, and a two-level converter leg whose midpoint is used as another ac terminal. An ad hoc switching state redundancy based modulation strategy is used to ensure that the voltage across the flying capacitor is tightly balanced and is implemented using a look-up table further simplifies the control complexity. The performance and effectiveness of the proposed topology with its control scheme are validated through simulations and experimental tests. Comparison with other MLIs is included to highlight the merits of the proposed topology. From the results, it will be shown that the proposed inverter requires the least part count as compared to other topologies with the same performance and output quality. [ABSTRACT FROM PUBLISHER]

Cascaded H-bridge (CHB) multilevel inverters (MLIs) have been widely used for power electronics systems. While high-voltage blocking across power switches is not a constraint for low voltage applications, the research trend has been oriented to the design of more compact module topologies as an alternative for CHB. Despite the generation of more voltage levels with reduced switch count, the existing module topologies in recent literature take no account of the freewheeling current path during dead-time, thus, inducing multistep jumps in voltage levels and giving rise to undesirable voltage spikes. Addressing this concern, this paper proposes two symmetrical compact-module topologies for cascaded MLI, where freewheeling current path during dead-time is provided for smooth transition between voltage levels to prevent voltage spikes. The proposed 7-level and 13-level compact-modules demonstrated low number of conducting switches for all voltage levels. Comprehensive analysis and comparison with the latest module topologies are conducted. To validate the operation of the proposed compact-module topologies, simulation and experimental results are presented. [ABSTRACT FROM PUBLISHER]

In order to reduce the cost and the size of a single-phase to three-phase power converter, an electrolytic capacitor-less single-phase to three-phase inverter is proposed. As the system does not have energy storage, such as an electrolytic capacitor, it results in source current harmonics due to the spatial harmonics of the motor. Adding an inductor for filtering the source current harmonics increases the cost and size of the system. In order to improve the source current waveform without adding passive components, it is necessary to reduce the source current harmonics via inverter control. However, when the inverter control reduces the source current harmonics, voltage saturation of the inverter causes source current distortion. At the rated speed and load, the voltage saturation region amounts to 40–50% of the source period, and the source current harmonics do not meet the guideline of IEC 61000-3-2. This paper proposes a direct dc-link current control (DDCCC) considering voltage saturation and the dq -axis current reference calculation for applying the DDCCC, which reduces the source current harmonics below the guideline. The effectiveness of the proposed method is verified through experiments. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel autonomous control scheme for equal load current distribution between $n$ parallel-connected, LCL-based, three-phase online uninterruptible power supply (UPS) modules. The control is based on regulating the reference voltage of the filter's capacitor of each inverter as a function of its own output current. The control is achieved without exchanging information between the inverters. The load voltage is maintained fixed at the specified reference value. The control method is fast, precise, and robust against load variations. The validity of the proposed method is verified experimentally and by simulation on a system of two parallel inverters under different load conditions, including step-load and nonlinear load. [ABSTRACT FROM AUTHOR]

A substantial pulsation of the second-order harmonic current ripple with angular frequency $2\omega$ is reflected at the input of a single-phase inverter when loads are supplied at its output with angular frequency $\omega$ . Moreover, this ripple back-propagates and injects into the source in the absence of a bulky dc-link passive filter, an active compensator or a suitable digital controller with a front-end converter in the two-stage converter. This paper proposes a new adaptive sliding mode control for a two-stage dc–dc–ac converter to reduce proliferation of ripple without compromising dynamic performance. The front-end boost converter in the considered two-stage converter interfaces a battery bank and single-phase inverter fed loads. The control shapes the output impedance of the boost converter to reduce the ripple component at battery input. Second, the proposed controller achieves good dynamic performance at line and load transients. A fast voltage recovery with small undershoot/overshoot can be achieved at transients using the proposed controller. The proposed technique is validated using a hardware of the 1-kW two-stage converter. [ABSTRACT FROM AUTHOR]

Active ripple decoupling technique of the single-phase inverter is a popular topic to minimize the dc-link capacitance. However, the existing control methods are based on tracking sinusoidal or predetermined voltage waveforms of the compensation capacitor, assuming the inverter outputs are pure sinusoidal voltage and current. Therefore, the performance of existing methods degrades when the inverter output voltage and current are not purely sinusoidal. Furthermore, the limited dynamic performance threatens the safety of dc-link capacitor when the load changes. This happens, because the inrush ripple power is injected into dc link with small capacitance and the dc-link voltage will suddenly rise up when the ripple power is not buffered during transients. In this paper, a direct instantaneous power predictive control is proposed for the decoupling circuit to buffer ripple power of the single-phase inverter, which combines instantaneous ripple power control with model predictive control to overcome the issues above. The proposed method tracks the instantaneous ripple power rather than voltage or current waveforms. In this way, it can fully buffer all ripple powers in the system even for distorted output voltage and current of the inverter and enables the full utilization of storage capacitor. In addition, model predictive control makes the proposed method have fast dynamic and perfectly compensate ripple power during transients and steady states. The buck-type active ripple decoupling circuit is chosen to implement the proposed method after comparing with another typical decoupling topology. The proposed method is also compared with conventional method using proportional-integral-resonant regulator to track the predetermined capacitor voltage waveform. Experimental tests verify the theoretical analysis and the proposed control method. [ABSTRACT FROM AUTHOR]

Compared with multilevel space vector modulation, level-shifted multicarrier sinusoidal pulsewidth modulation (SPWM) for nested neutral point-clamped (NNPC) inverters requires much less calculations and implementation efforts, but the existing conventional SPWM cannot suppress the severe flying-capacitor (FC) voltage ripples under low output-frequency conditions. In order to solve this problem, a multicarrier-based PWM strategy with complete voltage balance control (VBC) capacity is proposed in this paper. For NNPC inverters operating under low output-frequency conditions, two preprocessing steps, the zero-sequence injection and the modulation-signal rearrangement, are proposed before the comparisons between level-shifted carriers and modulating signals. These preprocessing steps make the average currents flowing through FCs zero, which is beneficial to greatly reduce the FC voltage ripples under low output-frequency conditions. Together with additional VBC, the proposed modulation can assure the FC voltages balanced under the entire output-frequency conditions. Principles and implementation processes of proposed modulation techniques and VBC methodsare elaborated in detail and compared with conventional modulation methods. Both simulation results from a 5-MVA system and experimental results based on a 5-kVA platform are presented to verify the effectiveness. [ABSTRACT FROM AUTHOR]

Microinverters for photovoltaic (PV) modules can improve the energy generation by reducing the effects of shading, since the energy harvesting of each PV module can be controlled individually. In this context, this paper presents a topology of single-stage transformerless grid-connected boost microinverter. It promotes high voltage gain without using a preregulator circuit or a high/low-frequency transformer. A 500 W laboratory prototype was implemented and experimental tests were carried out so that the proposed microinverter was evaluated in a grid-connected PV system. Experimental analysis was performed in order to corroborate the theoretical approach and to verify the effectiveness of the proposed modified Perturb and Observe “Gama” maximum power point tracking technique and the proportional-resonant (P-Res) grid current controller under different irradiation conditions and under partial shading. [ABSTRACT FROM PUBLISHER]

This paper proposes a high-efficiency two-stage three-level grid-connected photovoltaic (PV) inverter. The proposed two-stage inverter comprises a three-level step-up converter and a three-level inverter. The three-level step-up converter not only improves the power-conversion efficiency by lowering the voltage stress but also guarantees the balancing of the dc-link capacitor voltages using a simple control algorithm; it also enables the proposed inverter to satisfy the VDE 0126-1-1 standard of leakage current. The three-level inverter minimizes the overall power losses with zero reverse-recovery loss. Furthermore, it reduces harmonic distortion, the voltage ratings of the semiconductor device, and the electromagnetic interference by using a three-level circuit configuration; it also enables the use of small and low-cost filters. To control the grid current effectively, we have used a feed-forward nominal voltage compensator with a mode selector; this compensator improves the control environment by presetting the operating point. The proposed high-efficiency two-stage three-level grid-connected PV inverter overcomes the low efficiency problem of conventional two-stage inverters, and it provides high-power quality with maximum efficiency of 97.4%. Using a 3-kW prototype of the inverter, we have evaluated the performance of the model and proved its feasibility. [ABSTRACT FROM PUBLISHER]

This paper proposes a double modulation wave carrier-based pulse width modulation (CBPWM) strategy for the three-level neutral-point-clamped (NPC) inverter. This modulation strategy not only overcomes one of the main problems of the NPC inverter, which is the low-frequency voltage oscillation on the neutral point, but also reduces the common-mode voltage (CMV) generated by the inverter. Through the rigorous theoretical derivation, the unified duty cycles of each phase are derived, and the double modulation waves can be easily obtained according to different optimization objectives. However, in the previous double wave CBPWM work, the modulation strategy could not reduce the CMV, whose amplitude is still the same as that of the conventional CBPWM strategy. By rearranging the switching sequence, the vectors corresponding to the large CMV amplitude have been eliminated, and the amplitude of CMV can be reduced by half. Considering the occurrence of neutral-point voltage perturbations, a voltage controller is adopted to recover from the imbalance. Finally, the performance of the proposed modulation technique is verified by the experimental results. [ABSTRACT FROM PUBLISHER]

A well-known issue of fuel-cell-powered single-phase uninterruptible power supplies (UPS) is that the input current from the dc source is coupled with the second-order current ripple due to the ac-side instantaneous power pulsating at twice the line frequency. The low-frequency ripple component has been confirmed to have detrimental impacts on fuel cell's reliability and lifespan. To solve this issue, a boost inverter that can work in both differential mode (DM) and common mode (CM) operations is adopted by this paper. The DM operation achieves active power conversion and a well-regulated ac output voltage. Meanwhile, the CM operation ensures effective dc current ripple reduction. In addition to operating with linear loads, the proposed control method extends its working scope to nonlinear loads, where meticulously designed repetitive controllers are employed to handle the multiple low-harmonic situations. Moreover, the proposed control method also introduces an interleaved pulse-width modulation to further reduce the switching frequency ripple in the dc current. The stability of the proposed control system is stringently examined. Finally, presented experimental results validate the theoretical analysis as well as the effectiveness of the proposed method in current ripple reduction. [ABSTRACT FROM PUBLISHER]

This paper presents the design and implementation of a simple neutral point potential (NPP) regulator for a three-level diode-clamped inverter employing a sine-triangle regulator in conjunction with a closed-loop controller with reduced switching losses. The regulator principle is based on adding a continuous variable offset voltage which regulates the midpoint potential of the dc bus. The novelty of the proposed NPP regulator is in the determination of the magnitude of variable offset voltage based upon the average value, peak-to-peak amplitude, total harmonic distortions, and third harmonic content in NPP. Aside from maintaining dc-bus voltage balance, the proposed regulator leads to a significant reduction in the voltage distortion at the NP, resulting in the reduction of the required dc-bus capacitance. It also reduces the switching losses of the inverter by inserting the “no-switching” zone within each half cycle of the fundamental voltage wave. Analytical, computer simulation, and experimental results verifying the approach are presented in this paper for various load power factor angles. [ABSTRACT FROM AUTHOR]

In this paper, an immune algorithm (IA) is developed for optimization of the harmonic performance of a three-phase inverter under the space-vector pulsewidth-modulation (SVPWM) control strategy. The presented algorithm employs the immune approach as the search method for finding the best optimal control vectors and action time of the three-phase inverter. As a result, the optimal control vectors and action time are calculated to minimize the objective function of the weighted total harmonic distortion of the output voltage waveforms. In addition, an experimental platform based on DSP and field-programmable gate array is built. This paper provides a detailed performance analysis of the method with comparison to the conventional SVPWM. The simulation and experimental results verify the superiority of the best control sequences generated by IA compared with the existing conventional control strategies. [ABSTRACT FROM PUBLISHER]

A new pulse width modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is developed and presented in this paper. The proposed PWM scheme not only takes advantage of the special properties available in NPC inverters, but also reduces the switching loss of the inverter along with an inherent neutral point (NP) voltage control. Based on a circuit-level decoupling concept, the NPC inverter can be decoupled into two three-level Buck converters in every defined operating section, and thereby the controller design can be simplified. The salient features of the proposed scheme, as compared with the existing carrier-based DPWM strategies, are: 1) its reduced computational processing time, 2) its capability to balance the dc-link voltage without any additional control, and 3) its reduced complexity, e.g., only one carrier wave needed for pulse width modulating. Same as a space-vector modulation, the maximum modulation index, 1.1547, can be attainable by the proposed scheme. Moreover, compared to conventional continuous sinusoidal PWM, using this technique proposed here, the switching losses of the devices can be reduced by one third. In order to explain the operation of this topology properly, the decoupling principle including the driving signal synthesis and the NP potential variation are analyzed in detail in this paper. Finally, the viability and performance of the proposed modulation scheme are shown through simulation and experimental results in a laboratory prototype. [ABSTRACT FROM PUBLISHER]

This paper presents a novel soft-switching galvanically isolated buck-boost dc–dc converter as a module-integrated converter for photovoltaic (PV) applications. It features three major operating modes: boost, normal, and buck mode. Their proper distribution over the input voltage range enables wide voltage regulation capabilities, i.e., close to those of nonisolated power optimizers. The proposed control algorithm requires only one buck-boost switching stage that performs voltage regulation by means of the switching stage reconfiguration with smooth transition between the modes. The design guidelines and the digital control system for PV applications are provided. The module-integrated converter was verified experimentally with a solar array simulator. The converter showed good maximum power point tracking performance and a peak efficiency of nearly 97%. [ABSTRACT FROM PUBLISHER]

This paper proposes a unique carrier-based pulse width modulation strategy for a three-level neutral-point-clamped inverter that works satisfactorily and with uniform convergence time over the full power factor (PF) range of the load variation. It has excellent control over capacitor voltages and mitigates low-frequency oscillations in the neutral point for the full PF range. First, an investigation is made to see how the load currents get modulated to generate compensating neutral current causing charging and discharging of dc-link capacitors. It is observed that when an additional modulating voltage signal that is in phase with the corresponding phase current is added in each phase, a neutral current is produced in the right direction which can be used to compensate for any prior unbalance in capacitor voltages. It is demonstrated that the performance of this scheme is insensitive to the load PF variation (full range from zero to unity). It performs satisfactorily throughout the entire linear modulation range and eliminates any undesirable low-frequency harmonic component in the compensating neutral current. The effectiveness of the proposed scheme is verified through simulation and experimental results by varying load PF as well as modulation index with both passive and motor loads. [ABSTRACT FROM PUBLISHER]

The high number of power semiconductors in multilevel converters makes them susceptible to failure. Therefore, one of the main concerns in utilizing multilevel inverters is their reliability. This paper proposes a new simple fault-diagnosis and fault-handling method to increase the robustness and reliability of a flying capacitor multilevel inverter (FCMLI) which is one of the most prominent multilevel inverters. The proposed method is capable of diagnosing failed switch(es) and reconfiguring the switching sequence such that the output voltage is maintained similar to a normal operation condition. The proposed scheme identifies failed switch(es) by using the information about the charging state of the capacitors and the applied switching sequence. After identifying the failed switch(es), the algorithm bypasses the failed switch(es) and converts the control signals of the faulty leg from an M -cell L-level configuration to an (M-F)-cell L -level configuration (where F is the number of failed switches). The most attractive feature of the proposed control scheme is that any number of failed switches can be tolerated, as long as the number of functional switches is higher than the minimum number of cells required to build a full-binary L-level FCMLI. Simulation and experimental results are presented that verify the effectiveness of the proposed method. [ABSTRACT FROM PUBLISHER]

In this paper, the near-state pulse width modulation (NSPWM), adapted to be used in dual-voltage source inverter (VSI) fed open-end load, is introduced primarily aiming to appreciably minimize the voltage total harmonic distortion (THD). Within the framework of the proposed method, the active time of pulses at the second inverter is relatively adjusted within switching interval (compared to the first VSI). The phase voltage harmonics are formulated for dual-inverter modulated by NSPWM; then, optimal adjustment is identified via a three-dimensional curve of phase voltage THD versus modulation index (MI) and phase angle displacement (PAD). Due to the limitation of MI in NSPWM, the desired output voltage is synthesized with modifying not only MI but also PAD between references of two VSIs. Furthermore, NSPWM inherently takes advantage of better efficiency compared to conventional space vector modulation due to switching only two phases within an interval (by clamping one phase to positive/negative dc-rail). The dual-VSI supplied by two isolated dc sources is assembled in the laboratory to experimentally evaluate the THD reduction feature of the proposed method; also, the simulation results obtained by means of a MATLAB/Simulink environment show close agreement with experimental data. [ABSTRACT FROM PUBLISHER]

A novel flying-capacitor-clamped five-level inverter based on bridge modular switched-capacitor topology is proposed in this paper. The inverter features the switched-capacitor circuit with dc–dc boosting conversion ability and the multilevel inverter circuit with flying-capacitor-clamped performance. With the special composite structure, the number of components is cut down compared to the topology of the conventional cascaded multilevel inverter. Meanwhile, part of switches can be operated under line voltage frequency, resulting in switching loss reduction. Hence, the potential of system efficiency and power density is released due to embed switched-capacitor circuit. More importantly, the optimized carrier-based phase disposition pulse width modulation method is employed as a control strategy. Under this control strategy, the capacitor voltage self-balance can be realized and quality of output waveforms can be improved significantly. After simulation, the prototype is built to validate the correctness and practicability of the analysis. [ABSTRACT FROM AUTHOR]

This paper presents a closed-loop space vector modulation (SVM)-based sliding mode controller (SMC) for a three-level grid-connected neutral point clamped (3L-NPC) inverter. The nonlinear SMC based on Gao's reaching law has been designed to control the grid current and inject desired amount of active and reactive power into the network. Due to using single dc source at the NPC inverter dc bus, neutral point voltage is controlled through redundant switching states and instantaneous dc voltage feedback integrated into SVM technique. Meanwhile, there is no external voltage controller involved, thus no associated fine tuning issues are existed. The performance of the proposed hybrid controller to inject a desired active/reactive power to the grid is investigated through external perturbations such as change in the line current amplitude/phase shift, ac voltage fluctuation, as well as dc voltage variation. Full converter state-space model was developed and simulated. Experimental results are provided to verify the fast dynamic performance, low content of line current THD%, and good voltage balancing of dc bus capacitors of the NPC inverter. [ABSTRACT FROM AUTHOR]

This paper proposes a new configuration for static ground power unit (GPU) based on the novel 25-level hybrid active neutral-point-clamped (HANPC) converter. The superiority of the proposed converter, as compared with conventional and other suggested multilevel converters, is significant decreasing the number of switches and minimizing the number of flying capacitors (FC) in converter. This improvement is possible by using suggested low-voltage submodule converter to the ANPC converter and proposed modulation method. This results in reduction of the size and cost of converter and makes it more feasible and reliable. Applying the active voltage balancing method for FC in the proposed HANPC converter guaranties fast charging and voltage-level regulation of FC without using balance booster circuit. Improving output voltage spectrum leads to inductance reduction of output L–C filter which enhances static GPU performance. The simulation and experimental results verify the validity and feasibility of the proposed converter. [ABSTRACT FROM AUTHOR]