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This paper presents a 5-level inverter topology for open-end induction motor drives by using a single dc source. The open stator windings of the drive are supplied with a 3-level flying capacitor inverter from one end and capacitor-fed 2-level inverter from another end. The voltage ratio of the dc link to the capacitor in 2-level inverter is maintained at 4:1 ratio to generate five-level voltage output. The capacitor in 2-level inverter is balanced by the switching redundant vector combinations from both the inverters while the floating capacitors in the 3-level inverter are balanced by using redundant switching states. The proposed topology gives 5-level operation with less number of floating capacitors and power semiconductor switches compared to other existing topologies. Also, the balancing of the capacitors is independent of load power factor and modulation index. Further, the generalization of the proposed dual inverter scheme for any n-level inverter is also included in this paper. The experimental results and required analysis are also presented to validate the inverter scheme. [ABSTRACT FROM AUTHOR]

This paper presents a unified second-stage LC filter applied in the three-state switching cell buck–boost converter, which provides current and voltage with low ripple and low noise. The unified second-stage filter promotes a reduction in the number of devices while maintaining the filtering performance of the converter, with second-stage LC filters at the input and at the output. Moreover, the unified filter, when associated with a three-state switching cell buck–boost converter, allows a size reduction of filter devices, especially for designs with duty cycle range around 1/2. Furthermore, the unified filter arrangement provides nondissipative clamping of switching devices and reduce the system order when compared to the converter with second-stage LC filters. In this paper, the static and dynamic characteristics of the proposed converter in continuous conduction mode (CCM) are reported. Experimental data were obtained from a laboratory prototype with an input range of 32 $\sim$ 72 V, constant output of 48 V, a load of 150 W, and switching frequency of 45 kHz. The measured efficiency for the rated load was 97% for maximum input voltage. A comparison of the size and performance of the proposed filter with the topology that uses second-stage LC filters at the input and at the output is also presented. [ABSTRACT FROM AUTHOR]

In this paper, many impedance-source inverters with coupled inductors have been investigated to obtain a high step-up boost ratio. However, the leakage inductors in these topologies induce great voltage spikes at the dc link, which will increase the voltage stress of switches. Thus, the power level of inverters is limited. Furthermore, the efficiency of the inverters can be degraded by the losses associated with leakage inductors. To address abovementioned issues, this paper proposes a family of low-spike high-efficiency Y-source inverters. The proposed inverters have the ability of eliminating voltage spikes at the dc link and recycling the leakage energy via the additional diode and capacitor. In order to show the excellent characteristics of the proposed topologies, this paper compares the performances of the proposed inverters and the improved-Y-source inverter in many aspects. Simulation and experimental results have verified the abilities of the proposed inverters. [ABSTRACT FROM AUTHOR]

Reduced switch active phase converters (APC) are cost-effective solutions for running three-phase loads from single-phase grids. This paper proposes a novel auxiliary-capacitor-based APC (AC-APC) for this application. The combination of the topological location of the auxiliary capacitor and the control of the AC-APC reduces current stress on the semiconductor devices. In this paper, a selection criterion for the optimal auxiliary capacitor value is formulated to reduce the device currents in such a way that the overall efficiency is enhanced. This paper presents a comparative analysis of converter volt-ampere (VA) rating and device power loss for conventional H-bridge active front-end and inverter-based topology, APC, and AC-APC. To evaluate the efficacy of the proposed AC-APC, an experimental study is conducted on the APC and the AC-APC feeding a 3-hp three-phase induction motor. At a full load of $\text{2.5}\,\text{kW}$ and $\text{0.8 } \text{power factor}$ , the measured maximum efficiency of the AC-APC is $2\%$ higher than that of the APC. Analytical evaluation of converter currents and device power loss are in close agreement with experimental observations. [ABSTRACT FROM AUTHOR]

This paper proposes a capacitor voltage regulation method for the dual converter with a floating bridge for aerospace applications. This topology has previously been reported, but with a constrained voltage utilization factor due to the need for capacitor voltage regulations. In this paper, the effect of switching states on the voltage variation of capacitor is quantitatively modeled and an enhanced space vector modulation scheme with current feedback is proposed to achieve an active control of the floating capacitor voltages. This proposed method also allows further exploitation and utilization of converter voltage. The relationship between the allowed modulation index of dual converter and load power factor is obtained and expressed using a fitted polynomial equation. The advantages of the proposed method include boosted voltage utilization and superior performance in term of capacitor voltage balance. These advantages have been proven through simulation and experimental results on RL loads as well as with an open-end winding induction motor. The proposed modulation scheme can boost the converter voltage utilization by at least 10% while achieving full four-level operation. More importantly, the higher available voltage allows extending the constant torque region of the motor, the further beginning of field weakening operation could be postponed. [ABSTRACT FROM AUTHOR]

A trinary multilevel converter uses a few heterogeneous H-bridge submodules (SMs) to synthesize an output voltage with multiple levels. Two major limitations of this converter are that it needs multiple dc sources and it cannot operate under pulsewidth modulation (PWM). This paper addresses these limitations by adding a low-voltage H-bridge SM to this converter and proposing a new switching algorithm. The resulting PWM-based asymmetric cascaded H-bridge converter uses only one dc source and synthesizes a high-quality output voltage. This improved converter can be a potential choice for real and reactive power support in power system applications. This paper also proposes methods for stability analysis and design of this converter. Experimental case studies evaluate the performance of the proposed converter for both standalone and grid-connected modes of operation. [ABSTRACT FROM AUTHOR]

This paper proposes a new developed switched-capacitor converter to achieve high-voltage pulses with adjustable voltage level and frequency. The proposed topology generates repetitive high-voltage pulses by using low-voltage power supply with reduced number of components, including power semiconductors and capacitor. Therefore, a converter based on switched-capacitor units with high voltage gain and high efficiency can be achieved. Operation principles and design steps of the converter as well as comparative study with conventional converters are described in this paper. Finally, simulation and experimental results of a two-stage structure of the proposed circuit validate the operation principles and features of this topology. [ABSTRACT FROM AUTHOR]

This paper presents two capacitor voltage balancing (CVB) strategies for modular multilevel converter (MMC) applications. Both balancing schemes are based on model predictive control and are designed to efficiently solve a constrained optimal control problem, where the predicted capacitor voltage errors are included in the cost function with the demanded output voltage of a cluster being forced through an equality constraint. The first method proposed in this paper computes specific modulation indexes for each module using the explicit solution of a relaxed version of the original optimization problem. The second approach proposed in this paper reduces the complexity of the original problem by linearizing the objective function and using an optimal sorting network based on a greedy algorithm to solve this approximation. Considering the structures of both solution approaches, they are integrated into modulation schemes based on phase-shifted and level-shifted pulsewidth modulation algorithms, respectively. Experimental results obtained from a nine-cell single-phase MMC prototype demonstrate the good performance achieved with the proposed methodologies, as well as the implementation simplicity offered by the proposed CVB algorithms. [ABSTRACT FROM AUTHOR]

This paper proposes a new dc–ac converter with a reduced number of semiconductor switches and gate drive and control circuit components. A salient feature of this inverter is its pure sinusoidal line-to-line voltages with no need for output filter. Also, the proposed inverter improves the voltage utilization factor of the input dc supply compared to the four-switch three-phase inverter (first best topology in the literature from the number of switches point of view) and standard six-switch inverter with sine pulsewidth modulation. The proposed inverter is capable of operating with a wide range of output voltages from zero to the full value of the dc input voltage by appropriately altering the instantaneous duty cycle. A three-phase universal inverter with only three power switch has been proposed in this paper for the first time ever, to our knowledge. For the purpose of providing a good compromise between fast transient response and stability, a model predictive controller is proposed. All the design expressions have been derived. A comparison with other dc–ac converters is given to show the merits of the proposed converter. Finally, satisfactory circuit operation is confirmed by experimental results from a laboratory prototype. [ABSTRACT FROM AUTHOR]

In this paper, two structures are proposed for the switched-inductor quasi-Z-source inverter. In the proposed structures to extend the voltage gain of inverter, two new switched-inductor structures are used. In the proposed structures, voltage across the capacitors in the Z-source network and in the switched-inductor is symmetric and small. The other advantage of proposed inverters is known as achieving higher voltage gain per smaller duty cycle ratio (of shoot-through). Compared with a conventional continuous input current switched-inductor quasi-Z-source inverter at the same gain voltage, there is less of a ripple of input current in the proposed inverters. In this paper, at first the both the conventional and the proposed switched-inductor Z-source inventers are thoroughly investigated to find out their governing relations. Then, the proposed Z-source inverters are compared with the conventional ones by simulating them to assess their performance efficiency. Next, applying the simple boost pulse width modulation the simulation is carried out with PSCAD/EMTDC software. After that, to evaluate the obtained results, the prototypes of the proposed inverters with 48 Vdc input voltage are used. [ABSTRACT FROM PUBLISHER]

This paper analyzes the combination in a cascaded H-bridge multilevel inverter (CHBI) based on transformers with the different turn ratios for increasing the voltage level and proposes the switching method for achieving the output voltage distribution among H-bridge cells (HBCs). The transformers used in this paper are connected to the output of the respective HBCs, and the secondary sides of all the transformers are connected in series for generating the final output voltage. Only one of the transformers, in particular, has a different turn ratio for increasing the output voltage level. In this paper, the possible turn ratio of the special transformer with a different turn ratio is discussed in detail, and a switching method based on the level-shifted switching method for the topology used in this paper is proposed. To verify the effectiveness of the proposed method, a three-phase 21-level CHBI is experimentally tested. [ABSTRACT FROM PUBLISHER]

This paper presents a new multilevel converter topology based on a variable or multilevel dc-link stage. This stage is shared by all inverter output phases, thus increasing the number of output voltage levels while reducing the overall number of active devices compared to traditional topologies; therefore, it is called a reduced multilevel converter (RMC). The converter is not capable of reducing the blocking voltage of the devices; hence, unlike other multilevel converters aimed at medium-voltage applications, this converter is interesting for low-voltage- and high-power-quality-demanding applications such as photovoltaic inverters, wind energy conversion systems, and uninterruptible power supplies. The main novelty behind the proposed concept is the basic dc cell used to generate the variable dc-link voltage, which includes a controlled path through the floating capacitors to provide the necessary degree of control to enable a shared multilevel dc link for all the output phases of the converter. The dc cells are connected in a multicell structure to increase the number of levels of the converter. A five-level version of the RMC topology is briefly compared to other five-level converters such as the five-level active neutral-point-clamped converter and the five-level flying capacitor converter. This paper presents the structure of the new topology with its operating principle, switching states, main characteristics, and experimental validation using finite-control-set model-predictive control. [ABSTRACT FROM PUBLISHER]

In this paper, new half-bridge and full-bridge topologies for a switched-boost inverter are proposed. These topologies have a high boost factor in comparison with conventional types. In addition, the proposed topologies have continuous input current and can generate zero-voltage level in output. In this paper, the operation of the proposed inverters in different operating modes is analyzed. Then, the values of inductors and capacitors are designed. Moreover, the used switching pattern and its logical diagram are introduced. A comprehensive comparison between the proposed and conventional topologies in terms of the boost factor, the number of elements, and the efficiency shows the good features of the proposed inverters. Finally, to verify correct operation of the proposed topologies and derived equations, simulation and experimental results are presented. [ABSTRACT FROM AUTHOR]

This paper presents three unidirectional step-up ac–dc converter topologies with voltage multiplication on their outputs. The first topology is the hybrid boost rectifier and the other two are novel bridgeless structures, all based on the integration of boost rectifier and the ladder switched-capacitor (SC) cell. The new hybrid structures provide high voltage gain with low voltage stress across the switches, high-power factor, and output voltage regulation. This paper presents the principle of operation, steady-state and dynamic analysis, design methodology, and experimental verification. A different approach is also presented for the design methodology of the SC cell and for the analysis of its influence on the dynamic model. Three 1000-W prototypes with a 220-V input voltage, 800-V output voltage, and 100-kHz switching frequency were designed to corroborate the theoretical study. The best efficiency was 97.1$\%$ in the proposed bridgeless versions and the voltage stress across the switches stands around 400 V. Furthermore, a comparison between the proposed structures and previous topologies is also presented. [ABSTRACT FROM PUBLISHER]

In this paper, two topologies are presented for the enhanced-boost quasi-Z-source inverters (qZSI), namely continuous input current configuration and discontinuous input current configuration of enhanced-boost qZSI with two-switched impedance networks. Similar to enhanced-boost impedance-source inverters (ZSIs), these proposed inverter topologies possess very high boost voltage inversion at low shoot-through duty ratio and high modulation index to provide an improved quality output voltage. Compared to enhanced-boost ZSIs with two-switched Z-source impedance networks, these proposed inverter topologies share common ground with source and bridge inverter, overcome the starting inrush problem, and draw continuous input current and the lower voltage across the capacitors. Moreover, the input ripple current is negligible. This paper presents the operating principles and analysis of continuous input current configuration enhanced-boost qZSI with two-switched impedance networks and compares with ZSI, switched inductor ZSI, DA/CA-qZSI, and enhanced-boost ZSIs. The theoretical analysis is done and is validated through simulation and experimental results. [ABSTRACT FROM PUBLISHER]

This paper deals with a hybrid fault-tolerant converter topology. It is performed through the connection of a classical three-phase three-level neutral-point-clamped (3L-NPC) converter with a fourth three-level flying capacitor (3L-FC) leg. The 3L-FC leg actively balances the 3L-NPC neutral-point voltage. For normal operation mode, this paper proposes a mathematical design of the filter needed to connect these two different topologies. Experimentally, and thanks to the already existing decoupling capacitors of the 3L-NPC converter, this filter requires the addition of only one low size inductance. When one fault of the power switch of the 3L-NPC occurs, this paper proposes a hardware reconfiguration technique based on only two fuses and one thyristor per leg allows a safe postfault operation recovery. This is achieved thanks to a simple fault-detection method and a new technique that combines fault leg isolation and corresponding phase postfault connection to the neutral point. Also, a dedicated field-programmable gate array (FPGA)-based control of the reconfigured converter is synthetized to ensure power system availability under fault operation mode. The converter fault-tolerant capabilities are addressed through simulation results and original overall experimental validations of the fault detection and isolation and the postfault operation steps, carried out on a 15-kW prototype converter. [ABSTRACT FROM AUTHOR]

This paper proposes an effective sliding mode controller (SMC) for a grid-connected 7-level packed U-cell (PUC7) inverter. The aim is to design a simple controller that deals effectively with the complex control problem of the PUC7 inverter (multiobjective control problem). The selection of the control actions is achieved according to the system state error at every sampling time, regardless of the previous values, which makes the control technique model-independent. The control algorithm evaluates online two cost functions (one for each state error), which are derived on the basis of sliding mode theory, and it selects the optimal control input in order to satisfy the reaching conditions of the two cost functions. Compared with the existing solutions, the proposed SMC technique ensures lower average switching frequency by tuning the hysteresis bandwidth of the capacitor-voltage error. The fast implementation, needless of gains tuning, and simple design procedure are the main features of the proposed algorithm. Simulation and experimental results are presented to prove the effectiveness of the proposed technique in controlling the PUC7 inverter with high dynamic performance and robustness against disturbances and parameters mismatch. [ABSTRACT FROM AUTHOR]

This paper proposes a new multilevel inverter (MLI) topology that utilizes trinary sequence for the dc sources. It gives maximum output voltage level with minimum dc source and switch count when compared to other sequences, such as symmetric, natural, binary, and quasi-linear. This is due to the fact that the trinary sequence generates of all additive and subtractive combinations of input dc levels in the output voltage waveform. The concept is implemented on a 9-level asymmetric MLI using only four active devices. Multicarrier unipolar pulsewidth modulation technique is adopted to create the switching pulses. Theoretical calculation of total harmonic distortion in both voltage and current waveforms has been performed using asymptotic time domain formula. These values are compared with simulation and experimental values for different modulation indices. Power loss calculation for proposed topology is discussed with appropriate mathematical equations. [ABSTRACT FROM AUTHOR]

Circuit analysis and design criteria of a two-phase bidirectional converter with high voltage gain are presented in this paper. The operating principle of the forward or reverse mode is similar to that of the conventional buck or boost converter. Compared with the conventional converter, the switch stresses can be reduced significantly depending on the operating region of the voltage ratio in the two-phase converter. The power losses can also be reduced due to the use of low-voltage rating switches. The derivate converters are discussed to demonstrate the advantages of the proposed topology. A 200 W/1 MHz two-phase prototype converter with gallium nitride (GaN) devices is built and tested to verify the feasibility. [ABSTRACT FROM AUTHOR]

For photovoltaic applications, the flyback microinverter with pseudo-dc-link is popular as a simple topology but brings large transformer turns ratio and thus large leakage inductance, which would deteriorate the converter efficiency. To solve this issue, based on the nonisolated pseudo-dc-link structure, this paper proposed a hybrid boost–flyback/flyback (BF/F) microinverter. This new topology is operated at the BF mode for the most segment of a half grid cycle and the F mode for the rest. During the BF mode, high voltage gain with low voltage stress is easily available in minimized transformer turns ratio. Besides, the leakage energy is recycled and the turn-off voltage spike of the main switch is clamped, as a result of a passive snubber inherently contained in this mode. Given that the BF mode is lack of step-down function, the F mode is developed to regulate the output voltage even for values lower than the input voltage. The operation and characteristic of the hybrid BF/F microinverter in boundary conduction mode are analyzed in detail, and the mathematical expression of reference current is derived theoretically to guarantee high power quality. Finally, a 240 W prototype was implemented to validate the theoretical analysis and the benefits of the proposed topology. [ABSTRACT FROM AUTHOR]

Nanosecond pulse discharge plasma has many prospects in industrial applications, and high-voltage repetitive nanosecond pulse generators with compact design and light weight have become one of the key issues limiting its development in some applications. This paper presents a high voltage series-connected silicon carbide (SiC) metal-oxide -semiconductor field effect transistor (MOSFETs) module which can be served as the main switch in a repetitive high-voltage nanosecond pulse generator. This kind of series-connected MOSFETs module with only single external gate driver requiring very few components is very suitable for compact assembly. By analyzing the working principle, three topologies of series-connected MOSFETs module are proposed. The switching behaviors of the three different topologies with four SiC MOSFETs series-connected are compared experimentally. The variation of switching characteristics of series-connection SiC MOSFETs module with different numbers of devices are investigated. The layout is also optimized to shorten pulse front time and improve output pulse quality. Furthermore, a 10 kV SiC MOSFETs module with a turn-on transition time ∼10 ns is developed. The double pulse test result demonstrates excellent switching performances. Finally, a compact and high-voltage pulse generator composed of three 10 kV SiC MOSFETs module is tailored, with a typical rise time ∼40 ns and peak voltage of ∼30 kV. [ABSTRACT FROM AUTHOR]

This paper deals with the analysis of the input dc-link voltage ripple in multilevel inverter based on H-bridge and level doubling network (LDN). The LDN is basically a half-bridge fed by a floating capacitor, with voltage self-balancing capability, recalling the concept of a flying capacitor configuration. The amplitude of the LDN voltage ripple is analytically determined considering both the low-order and the switching harmonic components. In particular, peak-to-peak distributions of voltage ripples over the fundamental period are analytically determined, making possible the design of dc-link capacitor relying only on the dc-voltage ripple requirements. The case study makes reference to negligible switching ripple in the output current. It well represents either grid connection or passive load having almost sinusoidal currents. Numerical simulations carried out by MATLAB/Simulink and a complete set of experimental verifications are given to confirm the theoretical developments. [ABSTRACT FROM AUTHOR]

In this paper, a novel structure of switched capacitor converter (SCC) is proposed. First, the basic unit of the proposed SCC is presented. After that, a generalized structure of the proposed SCC is discussed. The presented SCC uses one dc source, several switches, diodes, and capacitors to produce multistep dc boosted output voltage. The capacitors in the SCC can be charged in trinary asymmetrical pattern. A detailed comparative study between the proposed and other recently developed SCC structures is presented. It is shown that the proposed SCC can produce an output voltage level with lower total standing voltage and lower maximum switch stress voltage as compared to most of the suggested SCC structures. Further, a switched capacitor multilevel inverter (SCMLI) based on cross-switched multilevel inverter has been developed and analyzed for symmetric and asymmetric dc source configurations. For fair comparison with the existing SCMLI structures, the overall cost of the structures is compared based on a cost function (CF). The proposed SCMLI provides lower cost function/output voltage level (CF/NL) in comparison with most of the other SCMLI structures for both symmetric and asymmetric dc source configurations. Extensive experimental studies validate the operation and performance of the proposed SCMLI structure. [ABSTRACT FROM AUTHOR]

Automated early detection and identification of switch faults are essential in high-voltage applications. Modular multilevel converter (MMC) is a new and promising topology for such applications. MMC is composed of many identical controlled voltage sources called modules or cells. Each cell may have one or more switches and a switch failure may occur in anyone of these cells. The steady-state normal and fault behavior of a cell voltage will also significantly vary according to the changes in the load current and the fault timing. This makes it a challenging problem to detect and identify such faults as soon as they occur. In this paper, we propose a real-time and highly accurate MMC circuit monitoring system for early fault detection and identification using adaptive one-dimensional convolutional neural networks. The proposed approach is directly applicable to the raw voltage and current data and thus eliminates the need for any feature extraction algorithm, resulting in a highly efficient and reliable system. Simulation results obtained using a four-cell, eight-switch MMC topology demonstrate that the proposed system has a high reliability to avoid any false alarm and achieves a detection probability of 0.989, and average identification probability of 0.997 in less than 100 ms. [ABSTRACT FROM AUTHOR]

In this paper, a novel noncoupled inductor high voltage gain single-ended primary-inductor converter (SEPIC) is presented. The proposed converter has various advantages, such as lower voltage stress on the switches, noninverting output voltage, high efficiency, and high voltage gain. Also, the introduced converter has a continuous input current which makes it suitable for renewable energy and fuel cell applications. Moreover, high voltage gain is achieved without using any transformer and coupled inductor, thus there is not any voltage overshoot for the switches during the turn-off process. This effect allows low conduction losses by using lower voltage rating switches and also additional clamping circuit is not needed. The control system of the presented converter is simple and the converter can be easily controlled in continuous conduction mode mode operation. Because, the gating pulses for both of the switches are the same and wide output voltage range is achieved only by changing the duty cycle. Furthermore, the number of the components compared to the other noncoupled inductor, SEPIC-based converters which provide near voltage gain to the proposed converter, is reduced. The detailed operation of the introduced converter and design considerations are discussed. Experimental results are presented to verify the performance of the proposed dc–dc converter. [ABSTRACT FROM AUTHOR]

This paper presents an approach for dealing with the control of five-level, diode-clamped rectifiers. The control of such converters is challenging, as voltage balancing among capacitors is not a trivial task. Some of the existing approaches that cope with this problem use specific modifications of one of the traditional modulation techniques, such as using redundant vectors in space vector modulation (SVM). The main feature of the proposed technique is that part of the modulation is considered in the system equations and, in this way, the voltage balance can be solved designing a specific controller for this problem. As a result, several levels are used within a switching period. Furthermore, it is shown that the proposed approach hardly affects the control of active and reactive powers and total dc-link voltage in such a way that the well-known direct power control can be applied. As a consequence, the resultant modulation stage is simpler than other techniques based on, e.g., SVM. The effectiveness and good performance of the system under the proposed control approach are validated by both simulation and experimental results. [ABSTRACT FROM AUTHOR]

Cascaded H-bridge (CHB) is a promising topology for medium-voltage high-power applications. CHB consists of low-power H-bridge modules in each phase, and these modules are connected in a cascade manner to achieve multilevel operation. However, CHB requires a phase-shifting transformer with multiple secondary windings to generate an isolated dc source for each module, and this requirement increases the overall system cost. In this paper, a series connection of low-power modules is employed to realize a new power converter called a series-connected multilevel converter. Each phase of the proposed topology requires a single isolated dc source. Hence, the required number of secondary windings is considerably reduced. This approach also minimizes the complexity and cost of the overall system. The operation of the proposed topology is presented by using three-level neutral point clamped modules in each phase. Model predictive control (MPC) is employed to control the dc-bus capacitor voltage and output currents of the proposed topology. A discrete-time mathematical model of the proposed topology is also developed to predict the future behavior of control variables. The performance of the proposed topology with MPC is verified through MATLAB simulations and a scaled-down laboratory prototype. [ABSTRACT FROM AUTHOR]

In this paper, a fully soft-switched bidirectional dc–dc converter is proposed. All semiconductor devices are soft switched, while its control circuit remains pulsewidth modulated. This condition is achieved only by one auxiliary switch. So, the proposed topology has less complexity in comparison with other similar structures. The energy conversion through the proposed topology during buck and boost modes is highly efficient due to achieved soft-switching condition. The auxiliary circuit operates once during each switching cycle. The converter is analyzed and a 250-W laboratory prototype of the proposed converter is constructed. The experimental results are presented that confirm the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper proposes two coupled-inductors-based Z-source networks, called the modified series and tapped switched-coupled-inductors quasi-Z-source networks (mSSCL-qZSN and mTSCL-qZSN, respectively). These networks offer high voltage gains with less-than-unity winding turn ratios $(n < {\text{1)}}$ , resulting in a reduced inductive element size. Other advantages include a less number of active components and their lower ratings and a higher efficiency. In addition, a lower magnetic core size is required for the proposed ZSNs due to the lower peak magnetizing current. The performance principles and detailed comparative analysis are provided and confirmed through experiments on a 200-W dc–dc converter. [ABSTRACT FROM AUTHOR]

In this paper, a new topology for half-bridge Z-source inverter is proposed. The proposed topology has only one impedance network. Unlike to the conventional half-bridge inverter, the proposed topology can provide zero voltage level at the output. It also increases output voltage level and stabilizes it in the desired value. Capacitor voltage stress in the proposed topology is low, and, therefore, nominal voltage of capacitor and cost decreases. In this paper, the steady-state analysis of the proposed inverter in two new operations which are named synchronous operation of diodes and asynchronous operation of diodes is conducted based on mathematics calculations. A method to obtain high-voltage gains by cascading the Z-network and combining middle inductors is presented that leads to cost, size, and weight reduction. Comparison among the proposed converter with conventional ones shows its excellent performance. The experimental results have good agreement with analytical analysis for the proposed topology. [ABSTRACT FROM PUBLISHER]

Zero-common-mode-voltage (CMV) operation of multilevel inverters results in reduced dc-bus utilization and reduced linear modulation range. In this paper, a method to increase the linear modulation range for zero-CMV operation without increasing the dc-bus voltage using a cascaded multilevel inverter with a single dc supply is presented. Using this method, the peak fundamental output voltage can be increased from 0.499 to 0.637  \textV\text{dc} with zero CMV inside the linear modulation range. Also, various pulse width modulation (PWM) switching sequences are analyzed in this paper, and the PWM sequence that gives minimum current ripple is used for the zero-CMV operation of the inverter. The inverter topology with single dc supply is realized by cascading a two-level inverter with two floating-capacitor-fed full-bridge modules. Simulation and experimental results for steady-state and dynamic operating conditions are presented to validate the proposed method. [ABSTRACT FROM AUTHOR]

In this paper, a new structure for symmetric and cascade multilevel converter is presented. This structure requires the least power electronic components, gate driver circuits, power diode, and dc voltage source. The number of output levels is high. Reduction of the number of power electronic switches against voltage levels is an important factor in multilevel converters due to safety in switches, circuit size, cost, installation area, and complexity in control. To maximize the number of output level in the proposed optimized structure in order to attain different goals, such as reduction of stress on switches, the result of comparing the proposed structure and other structures present. The proposed method is robust against the switching faults in multilevel converter for dc source and the equipment. The simulation and experimental results presented in this paper show the performance of the proposed method. [ABSTRACT FROM AUTHOR]

The large number of semiconductors typically implemented in multilevel converters generates large stray inductances in their commutation loops. As a consequence, high-voltage overshoots appear in the semiconductors during commutation which may limit the operation of the converter. The paper analyzes these overvoltages in the five-level active neutral-point-clamped (5L­ANPC) converter, one of the most popular five level converters and employed by ABB in its ACS­2000 drive. Experimental results show overvoltages almost three times higher than those corresponding to a two-level converter. In order to overcome this problem, the paper presents a new 5L­ANPC with the same characteristics (number of semiconductors, output waveform, switching frequency, efficiency, etc.), but with smaller overvoltages. This is achieved by adding some small capacitors to the busbar that behave like lossless snubbers but with a much simpler implementation. The experimental results illustrate the working principle of these capacitors and demonstrate the reduction of the overvoltages. As a result, the new converter can reach a higher output current or speed-up the commutations reducing, therefore, the losses and increasing the efficiency compared with the previous 5L­ANPC. [ABSTRACT FROM AUTHOR]

This paper presents a model predictive control technique applied to a dual-active bridge inverter where one of the bridges is floating. The proposed floating bridge topology eliminates the need for isolation transformer in a dual inverter system and therefore reduces the size, weight, and losses in the system. To achieve multilevel output voltage waveforms, the floating inverter dc-link capacitor is charged to the half of the main dc-link voltage. A finite-set model predictive control technique is used to control the load current of the converter as well as the floating capacitor voltage. Model predictive control does not require any switching sequence design or complex switching time calculations as used for space vector modulation; thus, the technique has some advantages in this application. A detailed analysis of the converter as well as the predictive control strategy is given in this paper. Simulation and experimental results to validate the approach are also presented. [ABSTRACT FROM PUBLISHER]

This paper presents a three-phase open-end winding induction motor drive. The drive consists of a three-phase induction machine with open stator phase windings and dual-bridge inverter supplied from a single dc voltage source. To achieve multilevel output voltage waveforms, a floating capacitor bank is used for the second of the dual bridges. The capacitor voltage is regulated using redundant switching states at half of the main dc-link voltage. This particular voltage ratio (2:1) is used to create a multilevel output voltage waveform with three levels. A modified modulation scheme is used to improve the waveform quality of this dual inverter. This paper also compares the losses in the dual-inverter system in contrast with a single-sided three-level neutral point clamped converter. Finally, detailed simulation and experimental results are presented for the motor drive operating as an open-loop v /f controlled motor drive and as a closed-loop field-oriented motor controller. [ABSTRACT FROM PUBLISHER]

This paper proposes a dual-function dynamic voltage restorer (DFDVR) with fault current-limiting capability. The new topology can operate under different modes: the short-circuit fault current-limiting mode and the compensation mode for voltage fluctuation. Different functions of the DFDVR are achieved by controlling a brake chopper circuit and antiparallel thyristors. During fault conditions, the antiparallel thyristors are deactivated to protect the dc-side capacitor, and the duration of the on- and off-periods of the semiconductor switch in the brake chopper circuit is controlled to adjust fault current amplitudes. During voltage sags, the antiparallel thyristors are activated, and the brake chopper circuit is turned off by controlling the gate turn-off thyristor in the brake chopper circuit, thus making the DFDVR similar to a conventional DVR. The control scheme and optimal parameter selection of the DFDVR are provided. The design methodology of the DFDVR was verified through simulations performed using the PSCAD/EMTDC software. The experimental results prove the capability and effectiveness of the DFDVR topology. [ABSTRACT FROM AUTHOR]

This paper presents a new reconfiguration module for asymmetrical multilevel inverters in which the capacitors are used as the dc links to create the levels for staircase waveforms. This configuration of the multilevel converter makes a reduction in dc sources. On the other hand, it is possible to generate 13 levels with lower dc sources. The proposed module of the multilevel inverter generates 13 levels with two unequal dc sources (2VDC and 1VDC). It also involves two chargeable capacitors and 14 semiconductor switches. The capacitors are self-charging without any extra circuit. The lower number of components makes it desirable to be used in wide range of applications. The module is schematized as two back-to-back T-type inverters and some other switches around it. Also, it can be connected as a cascade modular which leads to a modular topology with more voltage levels at higher voltages. The proposed module makes the inherent creation of the negative voltage levels without any additional circuit (such as H-bridge circuit). Nearest level control switching modulation scheme is applied to achieve high-quality sinusoidal output voltage. Simulations are executed in MATLAB/Simulink and a prototype is implemented in the power electronics laboratory in which the simulation and experimental results show a good performance. [ABSTRACT FROM AUTHOR]

This paper presents a generalized topology for multilevel converters based on flying capacitor multicell structure. The proposed topology consists of two modular high-frequency (HF) and low-frequency (LF) sections or cells. The HF cells consist of flying capacitors and semiconductor switches operating at carrier frequency. The LF cells consist of dc sources and semiconductor switches operating at line frequency and its multiples. The proposed topology can be implemented with arbitrary number HF and LF cells. An important advantage of the proposed topology is its reduced components when compared to other multilevel converter topologies in the same family. Another interesting feature is the relatively low blocking voltage requirement for HF switches, making it an attractive choice for high-power applications. A modulating algorithm is devised to generate the gating pulses for the HF and LF cells using phase-shifted carrier-based pulsewidth modulation. As a particular case, the operation of a 25-level topology is explained by the help of illustrating waveforms. A comprehensive comparative study is presented to illustrate the advantages of the proposed topology in terms of the number of components and other performance criteria. Various simulations are carried out to verify the operation of the proposed topology at different operating conditions. The theoretical analysis is experimentally verified using a scaled-down laboratory setup. [ABSTRACT FROM AUTHOR]

In this paper, a fixed switching frequency model predictive current controller is designed and implemented on a sensorless five-level packed U-cell (PUC5) inverter interfacing the utility. The predictive control methodology is based on a voltage vector generation technique for the cost function optimization by nullifying its derivative. The aim of the controller is to allow a fixed-frequency operation with no iterations while operating as a utility line current regulator. A pulsewidth modulator based on employing PUC5 redundant switching states fixes the PUC5 auxiliary dc bus capacitor voltage to its desired level with no necessity of a regulator; the overall technique reduces system complexity with less sensors and no loops in the predictive algorithm making it suitable for industrial applications. System discrete model is developed and experimental results verify the performance of the designed controller in making a fast response in regulating the grid current and balancing the capacitor voltage. [ABSTRACT FROM AUTHOR]

Switched-capacitor converter (SCC) featuring high efficiency and power density has attracted industry interest, but weak output voltage regulation hinders its application. This paper presents an optimized phase-shift (PS) control strategy for a bridge modular SCC, utilized in energy storage system, to obtain continuous conversion ratio and high-efficiency operation. By employing a small inductor as current buffer, the control strategy could be implemented to regulate output voltage conveniently with excellent steady and dynamic performance in step-down mode as well as step-up mode. Most importantly, the high-efficiency operation mechanism never reported before is revealed here. Correspondingly, the active circumfluence could be controlled through optimizing the range of PS time, which will avoid the loss in circuit self. Meanwhile, the soft-switching conditions of all the switches are comprehensively analyzed and soft-switching operations are achieved according to the logic timing control of the power devices, improving efficiency further. Finally, the prototype of the proposed converter was built and the experimental results validated the principle and features of the conversion method. [ABSTRACT FROM AUTHOR]

Discontinuous modulation applied to modular multilevel converters is an effective method for reducing the capacitor voltage ripples. In this paper, the discontinuous modulation is adapted and used in a motor drive application. For proper operation of the converter, a new energy controller is presented, which is suitable for operation with nonsinusoidal reference signals. Experimental results comparing the discontinuous modulation with other techniques operating at low motor speeds are shown. The results demonstrate the effectiveness of the discontinuous modulation on reducing capacitor voltage ripples and power losses. [ABSTRACT FROM AUTHOR]

This paper presents a modified modular multilevel converter with the three-terminal middle-cells inserted between arms and ac-side for medium voltage applications. It is intended to reduce the submodule capacitor voltage ripples by controlling the high-frequency powers flowing among arm branches for low-frequency output operations without common-mode voltage injected in ac-side. Due to the physical connection among the upper arm, the lower arm and ac-side, the middle-cell can be regarded as the excess degree of freedom to modify the dc-side and ac-side characteristics. Therefore, the common-mode voltage in ac-side can be eliminated by the inverse common-mode voltage produced by the middle-cell in ac-side. Moreover, owing to the unique structure of the middle-cell, the middle-cell capacitor voltage also results in a small ripple due to the high-frequency current flowing into it by proper control. The operation principle and control strategy of the middle-cell has been proposed in detail. Simulation and experimental results have verified the effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

Conventional two-level as well as multilevel voltage-source-inverter topologies with a hexagonal voltage-space vector structure generate low-order harmonics in the machine terminal voltages when operated beyond the linear modulation range in variable speed drive application. Progressing from hexagonal to a higher sided polygonal voltage-space-vector structure (VSVS) suppresses significant low-order harmonics throughout the modulation range. In addition, the linear modulation range will also be enhanced very near to the base speed. In this paper, for the first time, the generation of a multilevel 24-sided VSVS using a single dc source for induction-motor drives is proposed. A cascaded topology with a dc-source-fed flying-capacitor inverter and two low-voltage capacitor-fed H-bridge cells forms the power circuit. The features and advantages of the proposed scheme are validated through experimental results and discussions. [ABSTRACT FROM AUTHOR]

In this paper, a family of automatic interleaved Dickson switched-capacitor converters (AIDSCC) and its zero-voltage switching (ZVS) resonant configuration are proposed. Different from the traditional Dickson switched-capacitor converter, the AIDSCC has symmetrical configuration with the features of automatic interleaved input current, small output voltage ripple, and lower peak capacitor voltage stress. To improve the line regulation capability, one small resonant inductor is inserted and two bulky capacitor banks are replaced by two much smaller resonant capacitors, forming the resonant AIDSCC. The transistors are ZVS turned on and diodes are zero-current switching turned off by operating above the resonance. With frequency modulation within a reasonable range, the voltage-gain range of the resonant AIDSCC is expanded significantly, while sacrificing the maximum efficiency due to the higher conduction loss. A 3X AIDSCC and a 3X resonant AIDSCC below 140 W were built to verify the analysis. [ABSTRACT FROM AUTHOR]

This paper proposes a novel 11-level improved active-neutral-point-clamped (11L-IANPC) converter for ground power unit (GPU) application. This hybrid topology consists of the 5L-ANPC and the proposed low-voltage submodule. The proposed 11L-IANPC converter possesses only one flying capacitor (FC) and reduced number of high-frequency switches. Hence, voltage diversity and ratings, stored energy, and the number of costly and bulky FCs are significantly decreased. Moreover, operating the augmented submodule at the low voltage and power leads to doubling the number of output voltage levels, whereas the low extra cost and size are imposed on the proposed converter. In addition, suggested sensorless switching method leads to self-balancing of FC and significantly amends the output voltage frequency spectrum. These improvements cause significant reduction in control complexity of the proposed 11L-IANPC converter, remarkable decrease in size of the bulky and costly output LC filter, and improving the dynamic and steady-state performance of the proposed static GPU. The simulation and experimental results validate the feasibility of the proposed converter as well as its suggested modulation and control method. [ABSTRACT FROM AUTHOR]

Usually, the parallel-compensated inductive power transfer (IPT) topology fed by a current-source inverter is controlled through variable switching frequency and fixed 50% duty cycle method. This enables the system to operate at resonance frequency, which drifts due to load and other parameter variations. Owing to this control constraint, the load requirements are fulfilled by adding extra dc–dc chopper at the output. This paper presents a new control technique for a parallel–series/series IPT network, fed from a full-bridge current-source inverter to meet the load demand directly by an inverter. Therefore, the extra chopper stage at the output side of the converter is eliminated. The control goals are achieved through a two-loop control method, where the inner input current loop controls the source current and the outer output current loop meets the load requirements. The detailed steady-state operation, converter design, small-signal modeling, and control are reported, and experimental results obtained from a 1.6-kW lab prototype are included to verify the mathematical analysis. [ABSTRACT FROM AUTHOR]

The conventional design of voltage-source power converters is based on a two-level half-bridge configuration and the selection of power devices designed to meet the full application specifications (voltage, current, etc.). This leads to the need to design and optimize a large number of different devices and their ancillary circuitry and prevents taking advantage from scale economies. This paper proposes a paradigm shift in the design of power converters through the use of a novel configurable device consisting on a matrix arrangement of highly optimized switching cells at a single voltage class. Each switching cell consists of a controlled switch with antiparallel diode together with a self-powered gate driver. By properly interconnecting the switching cells, the switching-cell array (SCA) can be configured as a multilevel active-clamped leg with a different number of levels. Thus, the SCA presents adjustable voltage and current ratings, according to the selected configuration. For maximum compactness, the SCA can be conceived to be only configurable by the device manufacturer upon the customer needs. For minimum cost, it can also be conceived to be configurable by the customer, leading to field-configurable SCAs. Experimental results of a 6 × 3 field-configurable SCA are provided to illustrate and validate this design approach. [ABSTRACT FROM AUTHOR]

A new class of impedance networks is proposed in this paper. The proposed coupled-inductors-based impedance cells, called the series and the tapped switched-coupled-inductors, are employed within the (quasi) switched boost networks. The achieved impedance networks based on the proposed cells offer very high conversion gains with less-than-unity turn ratios (n < 1), which simplifies the realization of the magnetic element and at the same time reduces the number and size of passive components. The high boosting capability is achieved with small shoot-through durations that bring some additional advantages, such as low ratings of switching devices. The circuit analysis and operation concepts as well as a design procedure for the components of the proposed impedance networks are presented. Theoretical achievements are confirmed through experiments on a 220 W dc–dc converter laboratory setup. [ABSTRACT FROM AUTHOR]

In this paper, a new nonisolated high step-up dc–dc converter is proposed. Active–passive inductor cells (APICs) are used to extend the topology. The ability to achieve high gains is the main merit of the proposed topology. The proposed converter operates based on parallel charging and series discharging of the inductors. The converter also achieves high step-up voltage gain with appropriate duty cycle and low voltage and current stress on the power switches and diodes. The proposed converter is analyzed in operation modes. The main parameters of the converter such as voltage gain, voltage stress of semiconductor devices are calculated to compare with other structures. Considering the output voltage ripple and filter size, the proposed converter is designed. Moreover, the losses and efficiency of the converter are calculated. The performance of the proposed converter is validated by experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes an improved dc transformer (NDCT hereinafter) based on switched capacitor with reduced switches for the integration of low-voltage dc energy storage systems and medium-voltage dc power distribution grid. The topology, phase-shift (PS) shoot-through and multiple PS modulations, and voltage, current, and power characterizations, as well as commutation characterization and control strategy, are proposed and analyzed comprehensively. Compared with the traditional schemes, the proposed NDCT not only can enhance reliability and flexibility but can increase voltage adjustment and power transfer capabilities as well. Moreover, the current ripple performance and soft-switching performance are improved, and the number and capacity of switches are reduced, thereby increasing the efficiency and cost of the system. Finally, an NDCT prototype is built. Experimental results verify the correctness and effectively of the proposed solution. [ABSTRACT FROM PUBLISHER]