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Compensation of nonlinear effects generated by dead-time and semiconductors voltage drop has been widely studied in the literature about two-level converters. This paper takes a closer look at those analyses for multilevel converters, specifically for a cascaded H-bridge (CHB) converter modulated with phase-shifted pulse width modulation. The interaction between the cells is analyzed for a generic $n$ -cell converter, from which a general expression for the distortion generated by the nonlinearities has been obtained. Based on this expression, a compensation signal for the overall converter is calculated on each sample time, which is a fraction of the triangular carrier used to modulate each cell, thus significantly improving the quality of the output voltage signals. Experimental validation of the proposed compensation method is presented using a three-phase four-cell CHB converter prototype of 5.5 kW. [ABSTRACT FROM AUTHOR]

The five-level active neutral-point (NP)-clamped (ANPC) converter is a newly emerging topology which can overcome the drawbacks of traditional NP-clamped and flying-capacitor multilevel converters. This paper presents a comprehensive theoretical analysis of the NP potential balancing issue and demonstrates that the NP potential can be naturally balanced under ideal and steady conditions. An NP potential balancing method based on zero-sequence voltage injection is presented. By calculating the average NP currents of all key zero-sequence voltages, the most appropriate zero-sequence voltage is selected to generate the demanded NP current, which can also limit the switching frequency of the series-connected insulated-gate bipolar transistors to the fundamental frequency. A three-phase five-level ANPC inverter prototype is built up, and both steady and dynamic experimental results are presented to verify the validity of this method. [ABSTRACT FROM PUBLISHER]