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Part I of this paper has proposed a duty-cycle-space-vector (DCSV)-based modulation strategy for three- and four-leg matrix converters (MCs). This paper develops a digital DCSV-based modulation strategy for the three- and four-leg MCs based on the results of Part I of this paper. The digital DCSV-based modulation strategy is implemented in a DSP–field programmable gate array (FPGA) platform. The objective is to reduce the calculation time of the modulation algorithm by performing the following: 1) reducing the total number of instructions needed to implement the modulation algorithm in the DSP and 2) implementing parts of the modulation algorithm in an FPGA to generate the switching pattern. Therefore, the calculation process of the modulation algorithm is split between the DSP and the FPGA. [ABSTRACT FROM PUBLISHER]

Automotive light-emitting-diode (LED) drivers require special design considerations, which includes voltage step-up and step-down function, high energy efficiency, and fast current reference tracking capability. Unlike the conventional efficiency improvement methods, which is based on cumbersome circuit/component optimization and/or modification for a single operating point, this paper proposes a simple approach based on topology transition which can achieve a high efficiency for a wide input voltage range. In particular, the topology of the LED driver can change between buck, boost, and buck–boost converter according to the level of the input voltage. In addition, a novel current mode controller is proposed, such that 1) compatibility to different topologies, 2) seamless topology transition, and 3) fast current reference tracking can be concurrently achieved. The feasibilities of the proposed topology transition method and its control has been experimentally verified through a four-switch buck–boost converter prototype with 7–45 V input, 25 V/1 A LED strings output. It is shown that there is more than 5% efficiency improvement as compared to the conventional four-switch buck–boost converter. Full range (0%–100%) and precise (1% dimming precision) pulse-width-modulated dimming has also been demonstrated. [ABSTRACT FROM PUBLISHER]

During the design phase of a modular multilevel converter (MMC), an accurate loss evaluation of the submodule (SM) plays an important role. In this paper, a method based on the analytical description of the MMC key waveforms that allows to directly obtain the average semiconductor and capacitor losses that each SM will experience is introduced, under different operating conditions or control schemes. To verify the proposed concept, the results are compared with the losses obtained from a switched model with closed-loop control, where the analytical MMC key waveforms are approached in steady state. The proposed method provides a great flexibility and a significant reduction of the simulation/computational time otherwise needed to evaluate SM losses under various operating conditions. [ABSTRACT FROM PUBLISHER]

Multilevel cascaded H-bridge converters have become a mature technology for applications where high-power medium ac voltages are required. Normal operation of multilevel cascaded H-bridge converters assumes that all power cells have the same dc voltage, and each power cell generates the same voltage averaged over a sampling period using a conventional phase-shifted pulse width modulation (PWM) technique. However, this modulation method does not achieve good results under unbalanced operation per H-bridge in the power converter, which may happen in grid-connected applications such as photovoltaic or battery energy storage systems. In the paper, a simplified mathematical analysis of the phase-shifted PWM technique is presented. In addition, a modification of this conventional modulation method using variable shift angles between the power cells is introduced. This modification leads to the elimination of harmonic distortion of low-order harmonics due to the switching (triangular carrier frequency and its multiples) even under unbalanced operational conditions. The analysis is particularized for a three-cell cascaded H-bridge converter, and experimental results are presented to demonstrate the good performance of the proposed modulation method. [ABSTRACT FROM PUBLISHER]

This paper presents a new active capacitor voltage balancing control method for the flying capacitor multicell (FCM) converters which is fully implemented using logic-form equations. The proposed active capacitor voltage balancing control technique, measures output current and flying capacitor (FC) voltages to generate the switching states in order to produce the required output voltage level and to balance FCs’ voltages at their reference values. Output voltage of the FCM converter controlled with proposed active capacitor voltage balancing method can be modulated with any pulse width modulation (PWM) technique such as the phase-shifted-carrier PWM or level-shifted-carrier PWM. An advantage of the proposed active capacitor voltage balancing control method is its simplicity as it does not require any complex computations and tedious optimization calculations. Simulation results and experimental measurements of a three-cell four-level and four-cell five-level FCM converters are presented to verify the performance of the proposed active capacitor voltage balancing control technique. [ABSTRACT FROM AUTHOR]

This paper proposes a novel active capacitor voltage balancing technique for stacked multicell (SM) converters. The proposed active capacitor voltage balancing control method detects the direction of the load current and measures the voltage of flying capacitors (FCs) to generate a proper switching state in order to form the required output voltage level and regulate the FC voltages at their desired reference levels. The proposed active capacitor voltage balancing control technique can modulate the output voltage through any of the pulse-width-modulation (PWM) techniques such as the phase-shifted carrier PWM or the level-shifted-carrier PWM. The foremost advantage of the proposed active control technique is that it does not demand any complex computations because it is not based on the optimization of the FC voltage-deviation cost functions. A thorough set of simulation results and experimental measurements for the five-level and seven-level SM converters are provided to validate the proposed active capacitor voltage balancing control method. [ABSTRACT FROM AUTHOR]

In an asymmetrical pulse-width-modulated half-bridge (APWM HB) series resonant converter, an auxiliary LC network is provided for ensuring zero-voltage switching (ZVS) over a wide range of line and load variations. However, it comes at the cost of increased number of components and reduced efficiency and reliability. This paper presents a novel design methodology for the standard APWM HB resonant topology, which uses the magnetizing current and eliminates the need for extra components. The converter with the proposed design methodology operates at the resonant frequency of the tank and features load-independent ZVS for a wide range of input voltage variation with minimal magnetizing current. Empirical formulae are derived to design the resonant network and the magnetizing inductance of the high-frequency transformer systematically in a flowchart-based manner. The proposed design is validated by using simulations as well as experiments and is compared with a reference APWM HB series resonant converter design that uses an auxiliary LC circuit for ZVS. Two separate experimental prototypes of the two converters rated for 30 W, 48 V/5 V with a switching frequency of 500 kHz were built and tested in the laboratory. It was found that the converter with the proposed design methodology, apart from having lower component count, is about 3% more efficient than the reference topology at the rated power. [ABSTRACT FROM PUBLISHER]

This paper proposes a unique carrier-based pulse width modulation strategy for a three-level neutral-point-clamped inverter that works satisfactorily and with uniform convergence time over the full power factor (PF) range of the load variation. It has excellent control over capacitor voltages and mitigates low-frequency oscillations in the neutral point for the full PF range. First, an investigation is made to see how the load currents get modulated to generate compensating neutral current causing charging and discharging of dc-link capacitors. It is observed that when an additional modulating voltage signal that is in phase with the corresponding phase current is added in each phase, a neutral current is produced in the right direction which can be used to compensate for any prior unbalance in capacitor voltages. It is demonstrated that the performance of this scheme is insensitive to the load PF variation (full range from zero to unity). It performs satisfactorily throughout the entire linear modulation range and eliminates any undesirable low-frequency harmonic component in the compensating neutral current. The effectiveness of the proposed scheme is verified through simulation and experimental results by varying load PF as well as modulation index with both passive and motor loads. [ABSTRACT FROM PUBLISHER]

This paper presents a new high-frequency modulation method for multilevel converters. The proposed method provides a broad linear operating range and can be digitally implemented with minimal computational effort. This modulation method creates a phase voltage composed of a rectangular component superimposed on the top of a quasi-square-shaped reference function. The reference functions are defined such that the utilization of the dc-link voltage is maximized in any modulation index, while the dv/dt of the switches is always the minimum possible value. In order to implement the proposed method, an update time that is much shorter than the fundamental period is defined in the algorithm for updating the rectangular components of the reference voltage. The high-frequency rectangular component can then be imposed on the reference function to generate the final switching function by switching between two voltage levels during the time between two update instances. Several experimental results are provided to evaluate the performance of the proposed method and to compare its operation to conventional methods. [ABSTRACT FROM PUBLISHER]

In this paper, the near-state pulse width modulation (NSPWM), adapted to be used in dual-voltage source inverter (VSI) fed open-end load, is introduced primarily aiming to appreciably minimize the voltage total harmonic distortion (THD). Within the framework of the proposed method, the active time of pulses at the second inverter is relatively adjusted within switching interval (compared to the first VSI). The phase voltage harmonics are formulated for dual-inverter modulated by NSPWM; then, optimal adjustment is identified via a three-dimensional curve of phase voltage THD versus modulation index (MI) and phase angle displacement (PAD). Due to the limitation of MI in NSPWM, the desired output voltage is synthesized with modifying not only MI but also PAD between references of two VSIs. Furthermore, NSPWM inherently takes advantage of better efficiency compared to conventional space vector modulation due to switching only two phases within an interval (by clamping one phase to positive/negative dc-rail). The dual-VSI supplied by two isolated dc sources is assembled in the laboratory to experimentally evaluate the THD reduction feature of the proposed method; also, the simulation results obtained by means of a MATLAB/Simulink environment show close agreement with experimental data. [ABSTRACT FROM PUBLISHER]

Parallel three-level T-type inverters (3LT2Is) can effectively increase the power rating. However, when multiple 3LT2Is are connected to a single dc bus, the zero-sequence circulating current (ZSCC) will occur. The ZSCC will distort the output currents and increase the system loss. To overcome this drawback, this paper proposes a novel deadbeat control scheme for the ZSCC suppression. A generalized model for analyzing ZSCC in parallel 3LT2 Is is developed for designing the deadbeat control method. The proposed deadbeat control scheme is realized by real time adjusting the dwell time of small vectors in each space vector modulation. Compared to the conventional PI control method, the influence of different sector is eliminated, thus, improving the output current waveform and reducing the ZSCC. The effectiveness of the proposed method is verified by simulation and experiments. [ABSTRACT FROM AUTHOR]

This paper presents a new multicell topology based on flying capacitor (FC) structure suitable for multilevel converters. The proposed topology employs the concept of phase-shifted carrier pulse width modulation (PWM) with modified modulating signals to generate appropriate PWM signals. The modulation strategy along with all possible switching states are explained. The implementation of the proposed PWM technique is shown by the help of illustrating waveforms. To show the advantages of the proposed structure, different performance criteria are compared with other FC multicell (FCM) structures. Simulation results are used to further evaluate the potential merits of the proposed topology. It is shown that the proposed structure is superior to other FCM-based structures from different standpoints. Specifically, it reduces the number of high-frequency switches, the number of FCs, and at the same time improves the quality of output voltage. A laboratory-type experimental setup is used to validate the modulation strategy and other theoretical findings. [ABSTRACT FROM AUTHOR]

This paper presents a nine-level inverter topology for an open-end induction motor drive requiring only eight switches per phase, using two three-level inverters with two isolated dc links in a 3:1 ratio. A space-vector-based formulation is used to determine pole voltages such that both inverters supply power to the load over the full modulation range, eliminating the possibility of dc bus overcharging. Proper selection of switching states ensures that all floating capacitor voltages are kept tightly balanced. A digital state machine is used to select sequences of switching states in order to eliminate deadtime-induced pole voltage transients, further improving the output-voltage quality. A level-shifted carrier-based pulse width modulation scheme is used. The steady-state and transient performance of this topology were verified and the experimental results are included. [ABSTRACT FROM AUTHOR]

In grid-connected inverters, a feedforward controller accurately compensates for a large number of the harmonic components of the injected current. This controller is fast and directly tackles the grid dynamic voltage disturbances without doing any further harmonic analysis. A feedforward controller was introduced to a three-phase grid connection with a wye configuration; however, for the widespread delta connections, such a scheme is less established. Moreover, the nonsinusoidal profile of the grid voltage waveform makes the online conversion of line-to-line values into phase values impossible. In this paper, implicit zero-sequence discontinuous pulse width modulation (IZDPWM) based feedforward control is implemented on the two-level grid-connected inverter. Regardless of the grid topology, the IZDPWM-based controller ensures sinusoidal current injection to the grid under balanced, unbalanced, and distorted conditions. [ABSTRACT FROM PUBLISHER]

A bilevel driving approach was proposed in the literature for mitigating the energy wastage associated with driving LEDs at high peak current. The main idea is to introduce two drive parameters, i.e., high/low PWM current levels and duty cycles, that give rise to a 2-D luminosity control capability. The same idea was later generalized to an n-level driving approach for maximizing the electrical-to-light conversion efficiency of LEDs. Although previous uses of the n-level driving approach have been focusing on improving the luminous efficacy of LEDs, it is shown in this paper that its 2-D luminosity control feature can also lead to a significant improvement in color resolution when applied to driving RGB LEDs, hence making it well suited for applications in large-area LED display panels. In comparison to the first prototype driver proposed by the inventor of the driving approach, a more practical implementation of the complex 2-D driving approach with digital microcontroller is demonstrated. The various technical aspects of the driving approach, including luminous efficacy, color resolution, and color stability over dimming, are discussed in this paper with the aid of experimental results. [ABSTRACT FROM PUBLISHER]

Cascaded converters are adopted in many power systems to manage sources and loads at different voltage levels simultaneously. DC bus capacitor is one of the key components in these converters due to its energy storage and fast response capabilities. However, the ripple current through the capacitor will influence its lifetime and the overall efficiency of the converter. Previous studies showed that the capacitor current of ac systems is optimized when the duty cycles are synchronized under in phase or antiphase condition. In this paper, the bus capacitor ripple current of cascaded two-stage converters for dc systems with different combinations of duty cycles is analyzed. It is found that the optimum capacitor current ripple varies depending on the values of individual duty cycles and the phase-shift angle between them. By properly adjusting the phase shift, the capacitor RMS current value can be reduced without affecting the converter normal operation or the need for extra sensing circuits, hence improving the energy conversion efficiency and prolonging the capacitor lifetime with relatively simple implementation. To illustrate, a case study of a two-stage dc/dc converter is carried out. A laboratory prototype converter confirmed a maximum efficiency improvement of 2.8% if the phase shift is adjusted properly when compared to the same converter with the worst case phase-shift angle. [ABSTRACT FROM AUTHOR]

Multilevel active neutral-point-clamped (ANPC) converter is popularly known for its higher medium voltage drives up to 6.9 kV. However, common-mode voltages (CMV) are generated when using the well-established carrier-based pulse width modulation (PWM) modulation technique. As a result, CMV will become the major cause of the premature bearing failures and the conducted electromagnetic interferences. In this paper, a reduced CMV strategy is proposed for the ANPC which employs an alternatively new hybrid carrier-based modulation named as interleaved sawtooth carrier phase-disposition PWM (ISC-PD-PWM). By doing so, enhanced harmonic profile is achieved as compared to the typically used classical phase-shifted carrier PWM (PSC-PWM). Therefore, a comparative evaluation of the seven-level (7L) ANPC performance using the proposed reduced CMV approach is made between the novel hybrid ISC-PD-PWM and the conventional PSC-PWM in terms of harmonic analysis. The experimental results have proven the feasibility of the proposed concepts with the CMV effectively reduced. Such perceived merits make ANPC be more attractive for its motor drives. [ABSTRACT FROM AUTHOR]

This paper introduces a combination of two proposed efficiency improvement techniques for a microinverter with current mode control zero-voltage switching output stages. The first technique is dynamic dead-time optimization wherein pulse width modulation dead times are dynamically adjusted as a function of load current. The second method is advanced phase skipping control which maximizes inverter efficiency by controlling power on individual phases depending on the available input power from the photovoltaic source. Neither of the techniques requires any additional circuit components and both can be easily implemented in digital controller firmware. The two techniques were designed and implemented in a 400-W three-phase microinverter prototype. The experimental results validate the theoretical analysis of these techniques and demonstrate that a significant efficiency improvement can be achieved by combining the two proposed control techniques. [ABSTRACT FROM AUTHOR]

This paper proposes a new three-phase modular multilevel inverter (MMLI). The proposed inverter consists of repeated modular primary cells that are connected in series configuration. Therefore, the proposed topology can be extended to get more output voltage levels by adding additional cells without increasing voltage stresses across power switches. Both sinusoidal pulsewidth modulation (SPWM) and staircase modulation are successfully applied to the proposed inverter. The proposed inverter features many advantages such as reduced number of semiconductor power switches, driver circuits, dc-voltage sources, simplified control algorithm, and reduced voltage stresses across the switches independent of output voltage level. Furthermore, the performance of the proposed inverter is studied under both open-loop and closed-loop operations for highly inductive load. Beside the obtained simulation results, a laboratory prototype has been carried out and tested to verify the control techniques and performances of the topology. Simulation and experimental results are compared together to highlight the similarity and consistence of them. [ABSTRACT FROM AUTHOR]

Compensation of nonlinear effects generated by dead-time and semiconductors voltage drop has been widely studied in the literature about two-level converters. This paper takes a closer look at those analyses for multilevel converters, specifically for a cascaded H-bridge (CHB) converter modulated with phase-shifted pulse width modulation. The interaction between the cells is analyzed for a generic $n$ -cell converter, from which a general expression for the distortion generated by the nonlinearities has been obtained. Based on this expression, a compensation signal for the overall converter is calculated on each sample time, which is a fraction of the triangular carrier used to modulate each cell, thus significantly improving the quality of the output voltage signals. Experimental validation of the proposed compensation method is presented using a three-phase four-cell CHB converter prototype of 5.5 kW. [ABSTRACT FROM AUTHOR]

Space vector modulation (SVM) control of multilevel inverters (MLIs) is very popular. However, it gets extremely challenging with the increase in the number of output voltage levels due to the emergence of subtriangles in the various sectors of the hexagon, which results in increased computational complexity and storage requirements of switching states and corresponding pulse durations. Currently, this is handled through laborios offline computations in conjunction with the visual inspection of the space vector hexagon and its various sectors. This paper aims to simplify the implementation of the SVM scheme for an n-level MLI by proposing generalized equations that not only facilitate direct online computation of control pulses and obviate the requirement of lookup tables but also result in optimized switching. Yet, the on-time computations of the various MLI switches are still based on simple two-dimensional Cartesian co-ordinate system combined with the basic two-level inverter implementation. The proposed scheme makes use of a unique l-factor approach, which directly identifies the location of the various subtriangles in the space vector hexagon and leads to direct online computations of the control pulses. The proposed scheme is validated by simulations and experimental results for three- and five-level diode clamped MLI. [ABSTRACT FROM AUTHOR]

In high-power traction drive systems, the switching frequency of the inverter is strictly limited owing to the restrictions on switching losses and cooling conditions. In this case, the multimode modulation strategy is usually adopted. Based on the analysis of a modified 24-sector space vector pulse width modulation (SVPWM) technique, several synchronous modulation strategies with different pulse numbers are proposed in this paper, which can be applied to the two-level six-phase voltage-inverter-fed asymmetrical dual-stator induction machines. By comparing the harmonic performance of the synchronized modulations, the authors present a set of multimode SVPWM strategy, which is suitable for the high-power traction drive systems under low switching frequency. At the same time, the switching strategy for transitions between different modulation modes is proposed as well. Simulation and experimental results verify the validity and effectiveness of the proposed synchronized modulation strategies and the switching strategy between different modulation modes. [ABSTRACT FROM AUTHOR]

Several pulsewidth modulation (PWM) strategies have been proposed for three-phase multilevel converters. Typically, these PWM methods can be either space-vector or carrier-based implemented, where the carrier-based implementation usually presents a lower computation complexity. In this paper, a novel approach for the carrier-based implementation of different existing PWM methods is proposed for three- (3L) and four-level (4L) dc–ac converters, which can be easily extended to any number of levels. The main features of the proposed approach are its reduced computation complexity and computation time. On the other hand, the proposed approach suggests the derivation of novel PWM strategies which can potentially present improved performance features. As an example, two new discontinuous PWM (DPWM) strategies are proposed for the 4L converter. One of these DPWM strategies presents lower weighted total harmonic distortion than other previously proposed strategies. Simulation and experimental results verify the effectiveness of the proposed approach and novel DPWM strategies. [ABSTRACT FROM AUTHOR]

A new single-phase \uppi-\texttype 5-level inverter using 3-terminal switch-network (3TSN) is proposed in this paper. The topology is considered as a variant of T-type 3-level structure or dual-buck inverter with coupled inductors. This new inverter is suitable for multilevel power inversion with low dc-bus voltage. The merit of the proposed topology is to apply only four active power switches to achieve 5-level operation. Other benefits include double frequency operation of output inductor and equal division of the current that flows through power switches and filter inductor. Hence, it leads to high efficiency and low harmonics. These characteristics allow improvement of losses distribution and volume reduction of output filter inductor. The operation scenario with sinusoidal pulsewidth modulation (SPWM) is described in details. Meanwhile, the magnetic analysis and design are studied and discussed. Finally, a prototype is built to verify the theoretical analysis and demonstrate the benefits of the proposed topology. [ABSTRACT FROM AUTHOR]

A single-phase inverting buck–boost ac–ac converter is proposed in this paper. The proposed converter has no shoot-through and dead-time problems and, like conventional dc–dc converters, it can be operated with simple pulse width modulation (PWM) control. It offers high frequency and high efficiency operation because high speed mosfet can be used as switching device without the reverse recovery issues and losses of its body diode. The proposed converter features quasi-continuous input and output currents, high input power factor, low total harmonic distortion of input and output currents, and high efficiency. A 460 W laboratory prototype was constructed and tested with interleaved and complementary PWM controls using a resistive and inductive load. Detailed experimental results are provided to show the novelty of the proposed converter. Experimental results confirmed that the proposed converter can obtain 93.8% efficiency at 60 kHz switching frequency. [ABSTRACT FROM PUBLISHER]

In this paper, an improved model predictive control (MPC) of the modular multilevel converter (MMC) with reduced computational burden is proposed. A mathematical model of the MMC system based on the sum and difference of arm voltages are derived. Instead of determining the switching state of individual submodule (SM), the voltage levels of MMC are considered as control options based on the assumption that the SM capacitor voltages are well balanced. The further reduction of calculation effort is realized by using the tolerance band of capacitor voltages. The proposed MPC has a hierarchical structure. The cost function taking into account the ac-side current control, circulating current elimination and arm energy balancing is presented. The optimal voltage level, selected by the cost function, provides the voltage reference for the pulse width modulation modulator. The SM capacitor voltage balancing is done using a separate control loop. The proposed control strategy is investigated using an MMC high-voltage direct current system with 200 SMs in each arm in real-time simulation and hardware-in-the-loop tests. The performance of proposed method is verified by both steady-state and transient-state operations. [ABSTRACT FROM PUBLISHER]

This paper presents a review of the most popular control and modulation strategies studied for matrix converters (MCs) in the last decade. The purpose of most of these methods is to generate sinusoidal current on the input and output sides. These methods are compared considering theoretical complexity and performance. This paper concludes that the control strategy has a significant impact on the resonance of the MC input filter. [ABSTRACT FROM AUTHOR]

This paper proposes a unified PWM method for matrix converters so as to establish a common platform which can generate various types of PWM methods in real time by adjusting the free parameters in the modulation algorithm. As a foundation for unification, the general form of the modulation functions for matrix converters is derived using geometric transformation approach. All eligible direct modulation matrices are shown to be of indirect form and are expressed in terms of instantaneous phase quantities. This paper also presents a new viewpoint to consider a matrix converter as a generalized three-level inverter and to apply the double-carrier-based dipolar modulation technique of the three-level inverter to the matrix converter. Several concepts of the two-level PWM inverters are then generalized to the matrix converters for better visualization and understanding of the modulation process. [ABSTRACT FROM AUTHOR]

This paper proposes a new space-vector pulsewidth modulation (SV-PWM) strategy for a three-level neutral point clamped inverter. The presented SV-PWM strategy makes it possible to control the neutral point voltage by optimum choice of switch sequence for any position and length of output voltage vector. The proposed solution takes into consideration the unbalance of the dc-link voltages. It also analyzes the influence of vector sequences on the predicted unbalance of the dc-link voltage. The solution allows selecting optimum vectors and their on-time durations in order to reduce quickly the dc-link voltage unbalance. The calculation of the space vector area proposed in this paper takes into consideration voltage unbalance and its influence on the length and position of vectors. The proposed approach assures properly generating the voltage output vectors, even in the case of the existing large voltage unbalance in the dc-link. The results of the experimental investigation of the proposed modulation strategy are presented in this paper. [ABSTRACT FROM PUBLISHER]

This paper presents a novel topology for a direct ac–ac power converter, called as the “three-to- k” phase matrix converter. The input to the proposed matrix converter configuration is a three-phase fixed voltage and a fixed frequency supply from the grid. The output is a variable voltage and variable frequency ac supply of any number of phases (k phase). However, the discussion is limited here for a k that is equal to odd number of phases. As an example, a “three-to-five” phase matrix converter is utilized for discussion and analysis. This paper also proposes two pulsewidth modulation (PWM) control techniques for the general topology of the “three-to- k” phase matrix converter. This is based on the so-called direct duty ratio PWM (DPWM). In one presented technique, the output voltage is limited to one half of the input voltage. For the other proposed scheme, the output voltage is enhanced to 78.86% of the input voltage. The proposed control algorithm is validated using simulation and an experimental approach. [ABSTRACT FROM AUTHOR]

This paper presents a current soft-commutation pulsewidth modulation (PWM) scheme for three-phase current source converter. With the presented PWM scheme, the incoming switch has a positive collector-to-emitter voltage while the outgoing switch has a negative collector-to-emitter voltage during current commutations. Therefore, natural soft commutations for switching transitions are achieved, while current-commutating durations are also lessened. Moreover, some particular advantages can also be obtained such as reduced switching frequency, high dc current utilization ratio, and in-phase transfer between line currents and their references. For more efficient control, this paper then designs logic equations for mapping out the assignments from references to gating signals, allowing a simple implementation using a digital signal processor or a programmable logic device. The theoretical analysis is verified by experimental results. [ABSTRACT FROM AUTHOR]

AC–DC–AC converter-fed induction motor (IM) drive is mainly realized by back-to-back three-phase converters. However, fault in a single semiconductor switch will make it inoperative. To enable continued controllable operation in case of the faults occurring in the converter, the five-leg converter with a shared leg between the grid and load sides is a possible solution. However, this topology poses an inherent two-objective control problem, because its grid and load sides should be controlled simultaneously. More importantly, the potential increase of the shared-leg current may destroy the converters. In this paper, a new control scheme based on the FCS-MPC combined with intrinsic characteristic of the five-leg converter is proposed for independent control of the rectifier and inverter subsystem with the shared-leg overcurrent constraint. The condition for independent control is analyzed. In order to give a complete evaluation of the proposed control scheme, the conventional pulsewidth modulation (PWM) control scheme is conducted for comparison. Experimental results are provided to validate the effectiveness of the proposed scheme. [ABSTRACT FROM PUBLISHER]

Semiactive quadrupler rectifiers (SAQRs) are proposed in this paper to serve as the secondary rectification circuits, which make the secondary-side voltages to be controllable and help reduce current stress and conduction losses. An interleaved isolated boost converter is developed based on the proposed SAQRs. By utilizing the pulse-width modulation (PWM) plus phase-shift (PPS) control strategy, the primary- and secondary-side voltages are well matched to reduce the current values and circulating conduction losses. With the proposed SAQRs, the voltage gain is extended and the voltage stresses on power devices and passive components used in rectification circuits are reduced to the half of the high output voltage. Hence, the efficiency is improved by using a transformer with a smaller turns ratio and reduced parasitic parameters, and by employing low-voltage rating devices with better switching and conduction performance. With optimal design, lower voltage, and current stresses on the primary-side switches, minimized input current ripple can be realized. Moreover, the zero-voltage turn on switching of the active switches and the zero-current turn off switching of the diodes can be achieved over a wide load and voltage range by the proposed SAQR-based converter and the control strategy. Meanwhile, the higher voltage gain, the lower voltage, and the current stresses on power devices can be obtained with the proposed SAQR-based converter compared with passive quadrupler rectifier-based converter. The feasibility and effectiveness of the proposed SAQRs and the derived converter are verified by a 380-V output prototype. [ABSTRACT FROM PUBLISHER]

This paper addresses theoretical calculation of a single-phase multilevel pulsewidth modulation (PWM) inverter current total harmonic distortion (THD). Analytical approach introduced in late 1980s for a two-level inverter is generalized for an arbitrary level count for a single-phase inverter. Although the obtained closed-form piecewise analytical solutions assume (infinitely) large ratio of switching and fundamental frequencies and pure inductive load, they are practically very accurate for the ratios of (apparent) switching and fundamental frequencies larger than 25–30 and inductance-dominated loads. Along with strict mathematical solutions, simple accurate Bessel function approximation and hyperbolic average trend one are suggested. The formulas clearly reveal a single-phase PWM inverter current THD dependence on modulation index for an arbitrary voltage level count and are easily modified to cover grid-connected cases. [ABSTRACT FROM PUBLISHER]

Interleaving of voltage-source converter (VSC) legs enables higher output currents per phase, effectively increasing the power rating without increasing semiconductor ratings. However, the interleaved operation results in circulating currents between each phase converter legs as well as a zero-sequence circulating current (ZSCC), which become quite prominent when the converters operate with low switching frequencies. This paper demonstrates the interleaved operation of three-level converters under selective harmonic elimination pulsewidth modulation (SHE-PWM). A controller for the circulating current within the legs of each phase is also proposed. The controller is used in combination with optimally selected SHE-PWM patterns to generate the maximum number of voltage levels and minimize the peak value of the circulating current. Simulation and experimental results show the interleaved operation and the effect of SHE-PWM pattern selection in the overall system. [ABSTRACT FROM PUBLISHER]

The cost reduction of power-electronic devices, the increase in their reliability, efficiency, and power capability, and lower development times, together with more demanding application requirements, has driven the development of several new inverter topologies recently introduced in the industry, particularly medium-voltage converters. New more complex inverter topologies and new application fields come along with additional control challenges, such as voltage imbalances, power-quality issues, higher efficiency needs, and fault-tolerant operation, which necessarily requires the parallel development of modulation schemes. Therefore, recently, there have been significant advances in the field of modulation of dc/ac converters, which conceptually has been dominated during the last several decades almost exclusively by classic pulse-width modulation (PWM) methods. This paper aims to concentrate and discuss the latest developments on this exciting technology, to provide insight on where the state-of-the-art stands today, and analyze the trends and challenges driving its future. [ABSTRACT FROM PUBLISHER]

In this paper, a new inverter topology is proposed for generating a multilevel dodecagonal voltage space vector structure for open-end winding induction motor (IM) using a single dc source. Dodecagonal voltage space vector structure eliminates fifth- and seventh-order harmonic voltages from phase voltage output and hence eliminates the fifth- and seventh-order harmonic currents through the motor leading to removal of the dominant sixth-order torque ripple generation in the motor over the entire modulation range. Multilevel space vector structure generates output voltage with better THD and low dv/dt. In the proposed topology, two three-level inverters drive an open-end winding IM, one inverter from each side. DC-link of primary inverter is from a dc source which delivers the entire active power, whereas the secondary inverter dc-link is maintained by a capacitor, which is self balanced during the inverter operation. The PWM scheme implemented ensures low switching frequency for primary inverter. Secondary inverter operates at a small dc-link voltage. Hence, switching losses are small for both primary and secondary inverters. Experimental results show the elimination of fifth- and seventh-order harmonic voltages over the entire modulation range, validating effectiveness of the proposed multilevel inverter scheme. [ABSTRACT FROM PUBLISHER]

A four-level open-end winding induction motor (OEWIM) drive is known to suffer from two perennial problems. One is the problem of zero-sequence currentin the motor phases, which is caused by the existence of zero-sequence voltage in them. The other is the overcharging of the dc-link capacitor of theinverter operated with lower dc-link voltage by its counterpart operated with a higher dc-link voltage. This paper investigates the applicability of aspecial variant of space vector pulse width modulation (SVPWM) scheme for a recently proposed power circuit configuration, in which arectifier–inverter combination is nested within the conventional two-level inverter configuration to achieve four-level inversion. This PWM schemeis named as the sample-averaged zero-sequence elimination (SAZE) SVPWM scheme, wherein the zero sequence voltage is suppressed in each sampling timeperiod in the average sense. Both of the aforementioned problems encountered in this drive are successfully overcome for this power circuit configurationby resorting to the proposed SVPWM strategy. [ABSTRACT FROM PUBLISHER]

In an electric drive vehicle (EDV), the available voltage on a dc-link is limited, and so the inverter output voltage and, consequently, the line motor maximum speed are limited. The fundamental voltage of the inverter output is increased approximately 27% using a square wave (SW) switching pattern instead of a sine wave switching pattern. However, this pattern can only be used at high speeds, and at lower speeds a pulsewidth modulation (PWM) pattern should be used. In order to achieve proper control, the switching pattern should be changed seamlessly. In the present paper, a new PWM scheme for single-mode seamless control of Vernier motors is proposed. In the proposed scheme, the reference voltage is modified to change the switching pattern continuously so that the voltage changes smoothly from a high-frequency pattern to an SW and voltage discontinuity does not occur. Experimental results reveal that the inverter-switching pattern changes smoothly from a sinusoidal PWM pattern to an SW pattern, and so seamless control from the constant-torque region to the constant-power region, and vice versa, is achieved. Since the proposed scheme is a single-mode control, it is much simpler than current technologies, which are based on multimode controllers. Also the proposed method has a lower total harmonic disturbance (THD) as well as a lower harmonic distortion factor (HDF) compared to some existing methods. [ABSTRACT FROM PUBLISHER]

Multilevel inverters are gaining more attention in ac drive application due to their many attractive features. In the case of conventional neutral-point-clamped (NPC) or flying capacitor multilevel inverter configurations, active switches are connected in series to produce multilevel output voltage waveform. Therefore, if any one switch fails, the entire configuration has to be shut down; this will reduce the reliability of the system. A dual three-level inverter configuration for induction motor drive is proposed in this paper to improve reliability of the system. This topology is developed by feeding four-pole induction motor stator winding with four conventional two-level inverter modules. A level-shifted carrier-based third harmonic injection pulsewidth-modulation technique is used to produce the gating signals for the proposed configuration. By providing proper phase shift between carrier waves, multilevel voltage waveform is produced across the total motor phase winding, and first center band harmonics are also canceled. Thereby, the torque ripple will be considerably reduced compared with conventional NPC five-level inverter-driven induction motor drive. Finite-element analysis (FEA) is used to estimate the torque ripple when induction motor is supplied by the proposed configuration and conventional five-level NPC inverter configuration to show the effectiveness of the proposed converter. The proposed configuration is simulated using MATLAB/Simulink and experimentally verified using a laboratory prototype with a 5-hp four-pole induction motor drive. [ABSTRACT FROM PUBLISHER]

It is known that the ripple-based control of a switching dc–dc converter benefits from a faster transient response than a conventional pulse width modulation (PWM) control switching dc–dc converter. However, ripple-based control switching dc–dc converters may suffer from fast-scale oscillation. In order to achieve fast transient response and ensure the stable operation of a switching dc–dc converter over a wide load range, based on a conventional pulse train (PT) control technique, a peak capacitor current PT (PCC-PT) control technique is proposed in this paper. With a buck converter as an example, the operating modes, steady-state performance, and transient respond performance of a PCC-PT controlled buck converter are presented and assessed. To eliminate fast-scale oscillation, circuit and control parameter design considerations are given. An accurate discrete iteration model of a PCC-PT controlled buck converter is established, based on which the effects of circuit parameters on the stability of the converter operating in a discontinuous current mode (DCM), mixed DCM-continuous conduction mode (CCM), and CCM are studied. Simulation and experimental results are presented to verify the analysis results. [ABSTRACT FROM PUBLISHER]

The most recent literature on multiphase machine drives is based on voltage-source converter (VSC) systems utilizing different modulation techniques. Very little attention is given to the multiphase current-source converters (CSCs). Applying CSCs in high-power multiphase drive systems is promising and can effectively solve many technical problems associated with conventional VSC-based systems. This paper proposes a space vector pulsewidth-modulation (SVPWM) scheme suitable for a five-phase CSC. Generally, in SVPWM-CSCs, a current path should be provided for the dc-link current by ensuring that one pair of upper and lower switches is always on. Applying this constraint yields 25 different space vectors, which are mapped into two concentric decagons with ten equal sectors in the $\alpha\beta$ and $xy$ sequence planes. Each sector has two active-large vectors, two active-small vectors, and a null vector. Moreover, the active-large vectors in the $\alpha\beta$ plane are active-small vectors in the $xy$ plane, and vice versa. In the proposed scheme, the ampere-second concept is utilized to determine the ratio between the dwelling times of the large and small vectors such that the $xy$ current components are nullified, the utilization of the input dc-current is maximized, and the switching transitions are minimized, which, in turn, minimizes the CSC switching losses. The proposed scheme can effectively provide sinusoidal converter currents, which is suitable for motor drives and energy conversion applications. The proposed scheme is verified using a 1-kW prototype five-phase induction motor fed by a five-phase CSC. [ABSTRACT FROM PUBLISHER]

In this paper, three overmodulation techniques for the three-to-five-phase indirect matrix converter (IMC) are proposed. The first technique utilizes only the adjacent large vectors in the sector in which the reference output voltage vector lies. The second technique improves on that by continuously adapting vector elimination in the d_2-q_2 vector space based on the output voltage requirements. The third technique utilizes the ripple in the dc link to further reduce the modulation index of the inverter stage during overmodulation. All three techniques increase the voltage transfer ratio of the three-to-five-phase IMC from 0.788 to 0.923, but with the addition of harmonics generated by a vector in the d_2-q_2 vector space of the inverter stage. Simulation and experimental results from a prototype three-to-five-phase IMC validate the three proposed overmodulation techniques. [ABSTRACT FROM AUTHOR]

In this paper, a modified zero-voltage-switching pulsewidth-modulation inverter with a digital-signal-processor-based proportional–integral–derivative (PID)-like fuzzy controller (PIDFC) is implemented. The switches of the inverter can achieve a soft-switching feature that can largely reduce switching losses and improve the converting efficiency. In order for the online control of the proposed dc–ac inverter to be feasible, a fuzzy control is designed to be a PID-like fuzzy mechanism with the complexity significantly reduced. From the results, it is shown that the PIDFC can not only stabilize the output at 110 V rms but can also improve the performance when the system load has been changed from 600 to 100 $\Omega$. Comparing with a traditional PID controller, the responding speed can be improved by 75% in the simulation, and the speed can still be improved by 35% in the practice experiment. [ABSTRACT FROM AUTHOR]

Carrier-based pulsewidth-modulation (CBPWM) techniques are popular due to their simplicity, and have been widely researched for various three-phase inverter configurations. In this paper, two CBPWM techniques are proposed to reduce the common-mode (CM) voltage generated by the five-phase inverter. The five-phase inverters have more flexibility in reducing the CM voltage than their three-phase counterparts because they have more phase legs, hence finer control over the star-point voltage of the load. Two methods are proposed for the conventional two-level five-phase inverter to reduce the CM voltage; one utilizing adjacent modulating waveforms and the other utilizing nonadjacent modulating waveforms. The coupled inductor inverter (CII) uses coupled inductors to generate multilevel outputs. As the volt-second balance must be maintained across each coupled inductor, direct application of the proposed methods on the CII inverter will result in overcurrents in the coupled inductors. Hence, the proposed methods are further improved to ensure the volt-second integral over each switching period is zero. Moreover, the two proposed methods are designed to reduce switching events and prevent unexpected states occurring during the switching transitions. The performance and the switching strategy of both methods are verified by both simulations and experiments on a prototype of five-phase CII. [ABSTRACT FROM AUTHOR]

This paper proposes an indirect matrix converter (IMC) topology to supply a five-phase load directly from three-phase ac power sources without bulky electrolytic capacitors and explains its operating principle. Using the emerging topology, which combines the five-leg inverter into the rectifier stage of the conventional IMC, the three-to-five-phase IMC topology reduces the number of power switches and results in a simpler commutation compared with the conventional three-to-five-phase direct matrix converter. In addition, a simple approach to realize the carrier-based pulsewidth modulation (CBPWM) method for a three-to-five-phase IMC is presented, and the proposed CBPWM method is analyzed based on the space-vector approach. As a result, the IMC with the proposed CBPWM method can be more easily implemented compared with IMCs with the space-vector PWM method. A three-to-five-phase IMC control platform is realized by coordinating a TMS320F28335 DSP (Texas Instruments) with an EPM7128SLC84-15 field-programmable gate array (Altera). The simulation and experimental results are provided to verify the effectiveness of the CBPWM strategy. [ABSTRACT FROM AUTHOR]

A novel complementary phase disposition pulsewidth modulation method for the modular multilevel converter (MMC) with a limited number of submodules is proposed in this paper. Compared with the previous works, more practical issues have been considered, and the corresponding solutions have been provided. First, a new preset PWM signal mapping sequence and an improved virtual loop mapping (VLM) are used in the modulation. This method not only achieves a favorable capacitor voltage balance in the symmetry system but lowers the switching frequency of MMC's devices. Second, to further reduce the switching frequency, the unbalance margin of capacitor voltages is adopted to achieve the switching between the VLM and the selective VLM (SVLM). Moreover, the system robustness has been improved by considering the situation of symmetry losing, like cell fails; in these cases, the capacitor voltages of the upper and lower arms are balanced through the collaboration of the SVLM and the reconfigurable VLM. Finally, the effectiveness of the proposed method has been verified with simulation and experimental studies. [ABSTRACT FROM AUTHOR]

In this paper, a family of three-phase direct pulse-width modulated (PWM) ac–ac converters consisting of buck, boost, and buck–boost converters is proposed. The proposed converters have no commutation problem even if all of the switches are turned on or off simultaneously. They do not use lossy snubbers and do not sense the voltage polarity for commutation, and produce high-quality output voltage waveforms. The proposed converters allow the use of power MOSFETs and fast recovery freewheeling diodes independently. The use of power MOSFETs as active switches and freewheeling diodes with extremely fast recovery features lower the switching losses and enable us to reduce the volume of passive components by increasing switching frequency. The input (or output) filter inductor experiences twice of the converter switching frequency and thus can be designed with minimum size. To increase power density of the proposed converters, a three-phase three-limb coupled inductor is proposed. Three-phase coupled inductor integrates three separate coupled inductors of the proposed converters in one three-limb core. In comparison with separate coupled inductors, the three-phase coupled inductor has a smaller size with large current-handling capability. Experimental results obtained for the boost-type converter show the robustness of the proposed three-phase ac–ac converters. [ABSTRACT FROM AUTHOR]

This paper proposes a hybrid modulation strategy for asymmetrical cascaded multilevel converters operating under normal and faulty conditions on power cells. The proposed algorithm explores the advantages of both space vector (SV) and carrier-based modulation approaches. An SV is used for higher voltage cells to properly choose their voltage vectors in a way such as to avoid converter saturation, particularly under fault conditions. A generic algorithm to identify the domains of higher voltage vectors in which a reference lies, without the need for separation lines, is proposed. Then, to simplify the implementation of the algorithm, carrier-based modulation is employed for lower voltage cells, which switch with pulsewidth modulation. This suppresses the need for defining multiple switching sequences for different operational conditions, and it avoids converter saturation as much as possible, particularly under fault conditions on power cells. Simulation and experimental results for normal and faulty operational conditions are given, validating the theoretical analysis and demonstrating the good performance of the proposed hybrid modulation approach. [ABSTRACT FROM AUTHOR]

The Vienna rectifier, which is a nongenerative-boost type rectifier, is used in many applications such as telecommunication systems and wind turbine systems. The Vienna rectifier has a special operating requirement. Many switching methods considering this requirement were proposed. These methods generally take into account the Vienna rectifier's operation with the unity power factor because the Vienna rectifier aims to provide the power to the load. However, as the applications for the Vienna rectifier are diversified, control requirements have been suggested, including the dc-link voltage balance control and the novel control under severely unbalanced grids. In this paper, we propose a carrier-based pulse-width modulation (CB-PWM) method for Vienna rectifier operation with a variable power factor. The proposed CB-PWM method adds the compensation voltage to the three-phase reference voltages, depending on the power factor, to maintain the sinusoidal input currents of the Vienna rectifier. The performance and effectiveness of the proposed CB-PWM method are verified by simulation and experiment. [ABSTRACT FROM AUTHOR]