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Soft-switching techniques of transformerless photovoltaic grid-connected inverters (TLIs) can significantly reduce switching losses, as well as soften switching processes. Conventional dc–ac soft-switching configurations proposed by Dr. Deepakraj M. Divan are invalid in TLIs because of the leakage current problem. In order to develop soft-switching techniques in TLIs, this paper proposes a new soft-switching configuration and a procedure to guide the invention of soft-switching TLIs. First, this paper proposes two basic resonance tanks related to dc bus polarities, and then, uses these basic tanks to elevate four popular full-bridge-type TLIs according to the proposed guideline. As a result, four soft-switching TLIs are gained. Second, this paper picks obtained soft-switching highly efficient and reliable inverter concept (HERIC) as example to analyze its soft-switching operation principle and performance. As a consequence, all active switches of the gained soft-switching HERIC circuit are switched under both of zero-current turn-on and turn-off conditions; the reverse recovery problem of freewheeling diodes is alleviated owing to the zero-current turn-off of diodes; meanwhile, the common-mode voltage at the switching frequency scale is still constant. Finally, some experimental results from a 3-kW universal prototype at 50-kHz switching frequency are provided to verify the effectiveness of the main contributions of this paper. [ABSTRACT FROM AUTHOR]

Unipolar sinusoidal pulsewidth modulation (SPWM) full-bridge inverter brings high-frequency common-mode voltage, which restricts its application in transformerless photovoltaic grid-connected inverters. In order to solve this problem, an optimized full-bridge structure with two additional switches and a capacitor divider is proposed in this paper, which guarantees that a freewheeling path is clamped to half input voltage in the freewheeling period. Sequentially, the high-frequency common-mode voltage has been avoided in the unipolar SPWM full-bridge inverter, and the output current flows through only three switches in the power processing period. In addition, a clamping branch makes the voltage stress of the added switches be equal to half input voltage. The operation and clamping modes are analyzed, and the total losses of power device of several existing topologies and proposed topology are fairly calculated. Finally, the common-mode performance of these topologies is compared by a universal prototype inverter rated at 1 kW. [ABSTRACT FROM AUTHOR]