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DC shipboard power systems have been considered as a promising solution for stricter environmental regulations on ships due to their main benefits in fuel savings with variable speed engines and easy integration of energy storage systems. In order to employ the dc solution in the shipboard power systems, the dc power systems have to be protected from a system fault with protection selectivity to minimize impacts of the fault or to avoid other undesirable situations in the system. For low-voltage dc shipboard power systems, a three-level protection has been proposed: 1) fast action (first)—bus separation by solid-state dc bus-tie switch; 2) medium action (second)—feeder protection by high-speed fuse; and 3) slow action (third)—generator–rectifier fault controls. This paper proposes a new method by means of additional bus capacitance added in main dc buses to help reliable operation of the three-level protection. The principle of the proposed method is introduced and the sizing of the additional bus capacitance is addressed in this paper. With the modeling of the dc shipboard power systems, the analyses of voltage drops for the bus separation failure and fault clearing time for the feeder protection are carried out to verify the proposed method. The results show that the proposed method not only mitigates the voltage drop for the bus separation failure, but also achieves the selectivity and the sensitivity for the feeder protection. [ABSTRACT FROM AUTHOR]

In this paper, the conventional I- and T-type three-level neutral-point-clamped (3L-NPC) inverter for low-voltage renewable energy systems is first investigated. Literature research shows that the T-type inverter improves I-type's insulated-gate bipolar transistor (IGBT) $+$ IGBT current paths. However, the IGBT $+$ diode paths are the same. The calculation in this paper further reveals that the IGBT $+$ diode current paths dominate the conduction losses and even the whole semiconductor losses. Based on the aforementioned recognitions, a novel T-type inverter is presented as an alternative to be applied in the low-voltage renewable energy systems. In the proposed 3L-NPC, four CoolMosfets replace the IGBT $+$ diode middle bidirectional switch. In the proposed topology, there is no diode involved in the current path supposing the unity power factor. In this way, the conduction loss is expected to be reduced compared with that from the conventional T-type 3L-NPC, particularly in the low and medium power ranges. [ABSTRACT FROM PUBLISHER]

This paper characterizes the sampling effect in digital sinusoidal pulse width modulation (SPWM) of voltage source inverter (VSI). The time-domain analysis presented in this paper establishes the relation between the fundamental frequency, carrier frequency, and the sampling frequency at different modulation indices of the SPWM. The analysis investigates the effect of sampling frequency of the digital controller on the output of the VSI. It is shown that the low-frequency harmonic components appear in the frequency spectrum of the VSI output voltage due to sampling. As a result, the output current of digitally controlled VSI is stepped in nature. The double Fourier integral solution of the switched waveform for inner and outer integral limits has been used to derive the expression. The integral solution is obtained using Jacobi-Anger expansions. The generalized results developed in this paper are useful to investigate the sampling effect in high switching frequency DSPWM. The proposed sampling effect has been analyzed for SPWM of single-phase H-bridge inverter. The analytical results are verified using simulation and experimental results. The experimental results have been obtained with the use of field-programmable gate array (FPGA) as a digital controller. [ABSTRACT FROM PUBLISHER]

A space vector modulation (SVM) technique of a dual-inverter system for an open-end winding motor drive is described in this paper, where one inverter has a battery power source and the other has an only capacitor across the dc bus. The SVM must be achieved to operate the motor with field-oriented control and simultaneously to control the capacitor voltage at a constant value by using redundant switching states of the dual-inverter system. The control of the capacitor voltage is carried out by selecting a charging or a discharging mode in each redundant switching state, taking the instantaneous motor power factor into account. In addition, it is also required to reduce the error voltage pulses, which are generated in output multilevel voltage waveforms during the dead time. The compensation method of the existing dead-time scheme and the improved SVM sequence to reduce the error voltage vectors are proposed in this paper. The proposed methods are examined through several experimental tests and are confirmed to generate superior output voltage waveforms from the viewpoint of the measured total harmonic distortion and dv/dt. [ABSTRACT FROM AUTHOR]

The aim of this paper is to study the dynamics of a permanent magnet direct current (PMDC) brushed motor while two crucial space-domain effects, namely, slotting effect and commutation phenomenon are taken into account. Semi-analytical dynamic time-domain PMDC brushed motor model inclusive of these space-domain effects is used to analyze and investigate the dynamics. Pulse width modulation operated discontinuous current PMDC brushed motor drive with steady duty cycle is employed to acquire the bifurcation patterns. The chaotic nature due to slotting effect and commutation is identified from the bifurcation patterns and reported. It also has to be admired that such nonlinear dynamical behavior with the same set of parameters at similar operating condition has not been observed when a conventional PMDC brushed motor dynamic model is considered. These space-domain effects, namely, slotting effect and commutation also have a prominent impact to make some time-domain states of a PMDC brushed motor drive chaotic. The role of slotting effect and commutation phenomenon to analyze the chaos over time-domain state variables of the PMDC brushed motor drive is investigated and validated experimentally in this paper. [ABSTRACT FROM PUBLISHER]

In this paper, a single-inductor dual-output (SIDO) dc–dc converter is proposed. The significant feature of the proposed converter is feeding a constant power load in low-voltage side (LVS) port, where even feeding a variable load at LVS does not have any cross regulation to high-voltage side port with the desired approximation. Magnificently, both merits are obtained in open-loop manner, which is an outstanding characteristic in comparison with that of the existed converters. In this paper, soft commutation and soft switching of switches and diodes are investigated along with the aforementioned main novelty. Moreover, detailed theoretical analyses of the proposed SIDO dc–dc converter in continuous conduction mode are presented besides the comparisons with some other structures. Finally, theoretical analyses are verified through a 1500 W experimental prototype results. [ABSTRACT FROM AUTHOR]

In this paper, a series-capacitor-based interleaving buck power factor correction (PFC) converter is proposed, the intermediate energy storage capacitance of which is operated at discontinuous capacitor voltage mode (DCVM), and automatic power factor (PF) correction for this converter is obtained. Moreover, the voltage across the series capacitor of the proposed PFC converter is clamped at the input voltage, and thus peak voltage stress existed in the traditional DCVM buck PFC could be relieved. By effectively regulating the charge/discharge time for the series capacitor, ultrahigh step-down conversion ratio of the proposed converter is achieved, the conversion ratio of which is independent of the duty cycle and only related to the switching frequency and circuit parameters. Therefore, high PF can be obtained due to very narrow deadtime of the input current. Meanwhile, the proposed PFC converter can realize the soft turn-on of part power switch and soft turn-off of part power diodes. In addition, comparing with the traditional discontinuous inductor current mode PFC, the input current of the proposed PFC converter is continuous so that the peak value and root-mean-square value of input current can be reduced. The operational principle, performance analysis, and parameter design principle are given in this paper. The analysis results show that the PF and total harmonic distortion are also independent of the duty cycle. Finally, a 220-Vac input, 60 W/15 V output experimental prototype is built to verify the validity of the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper proposes a visible light communication (VLC) system consisting of a single-stage buck–boost power factor correction converter operating in the discontinuous conduction mode with dimming capability. Additionally, this paper proposes the on–off M-frequency shift keying modulation for the VLC system. This modulation allows for the transmission of more than a single bit for each switching period without affecting the dimming characteristics of the light-emitting diode luminaire. The design of the whole system is discussed in detail, including both transmitter and receiver modules. A 20-W laboratory prototype was built in order to verify the proposed modulation scheme. The experimental evaluation showed a good performance of the transmitter, which was able to perform simultaneously the desired functions, namely power factor correction, dimming, and data transmission. The receiver also achieved the desired performance with a low bit error rate (BER). The results showed that the proposed system was able to transfer data between emitter and receiver with a bit rate of 1.11 Mb/s at a frequency of up to 375 kHz over a distance of 10 m, and with a BER lower than $10^{-3}$ under the influence of external lighting sources with illuminance levels up to 500 lx. [ABSTRACT FROM AUTHOR]

To reduce the common-mode voltage (CMV) and eliminate the CMV spikes for two-level voltage source inverters (2L-VSIs), an improved model predictive control (MPC) based CMV reduction method is proposed in this paper considering dead-time effects. First, an improved voltage vector (VV) preselection strategy is proposed to reduce the CMV spikes caused by the dead time. Second, a new hybrid VV preselection strategy based on a delay compensation strategy and a modified current sector division strategy is proposed to completely eliminate the CMV spikes. As the proposed hybrid VV preselection based MPC strategy makes full use of the six nonzero VVs of the 2L-VSI, the current total harmonic distortions and ripples are reduced. The simulation and experiments are carried out to verify the effectiveness of the proposed strategy. [ABSTRACT FROM AUTHOR]

In this paper, a cascaded H-Bridge (CHB)-multilevel converter (MC)-based photovoltaic (PV) system with no voltage or current sensors at the dc-side is proposed. Eliminating the dc-side sensors simplifies the hardware, leading to lower cost and higher reliability of the PV system. A novel scheme estimating the capacitors’ voltages from the ac output voltage of the inverter is developed. The scheme allows replacing all dc-side voltage sensors by a single-voltage sensor at the ac-side of the converter. Furthermore, the dc current sensors, conventionally required for the maximum power point tracking (MPPT), are also eliminated. Instead, the outputs from the capacitors’ voltage control systems are utilized for the MPPT. The effectiveness of the proposed dc-side sensorless system is experimentally demonstrated on a 2-kW single-phase seven-level CHB converter-based PV system. [ABSTRACT FROM PUBLISHER]

This paper presents a uniform control strategy for the bidirectional ac/dc interlinking converter (BIC) in hierarchical controlled hybrid microgrid. The uniform control strategy unifies different control structures for multifunctional BIC in terms of power management, ac and dc voltage support. With the unified control structure, various triggering mechanisms for BIC mode-switch are not compulsory in response to the relevant scenario changes in the power network. Therefore, the negative consequences, such as unsmooth transition and system collapse due to the inaccurate or slower mode switch, can be avoided. Moreover, the uniform control strategy is also applicable for the hierarchical controlled hybrid microgrid, whose control architecture is typically comprised of the centralized and decentralized levels. This enables the communication fault ride-through capability and the impact from the communication failures can thus be mitigated. To sum up the above two features, the proposed control strategy is able to provide a smooth operation for the BIC without control mode switch in the event of unintentional scenario changes in power or communication network. To verify the validity of the proposed uniform control strategy, the controller hardware-in-the-loop experimental results have been provided in this paper. [ABSTRACT FROM PUBLISHER]

In this paper, two structures are proposed for the switched-inductor quasi-Z-source inverter. In the proposed structures to extend the voltage gain of inverter, two new switched-inductor structures are used. In the proposed structures, voltage across the capacitors in the Z-source network and in the switched-inductor is symmetric and small. The other advantage of proposed inverters is known as achieving higher voltage gain per smaller duty cycle ratio (of shoot-through). Compared with a conventional continuous input current switched-inductor quasi-Z-source inverter at the same gain voltage, there is less of a ripple of input current in the proposed inverters. In this paper, at first the both the conventional and the proposed switched-inductor Z-source inventers are thoroughly investigated to find out their governing relations. Then, the proposed Z-source inverters are compared with the conventional ones by simulating them to assess their performance efficiency. Next, applying the simple boost pulse width modulation the simulation is carried out with PSCAD/EMTDC software. After that, to evaluate the obtained results, the prototypes of the proposed inverters with 48 Vdc input voltage are used. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel fuzzified mechanical sensorless speed estimation technique for permanent magnet direct current (PMDC) brushed motor operated with pulse width modulation (PWM) based terminal voltage. For replacement of conventional mechanical speed sensors, few mechanical sensorless speed estimation techniques have been reported recently in the field of PMDC brushed motor. In this paper, a novel technique is applied over a recently reported semianalytical dynamic time-domain PMDC brushed motor model incorporating space-domain effects, namely slotting effect and commutation phenomenon to simulate the proposed estimation process. Ripple and back electromotive force based standalone estimation approaches are hybridized in order to eliminate uncertainties in all regions of estimation. In this paper, a discrete fuzzified hybrid speed estimation model has been proposed with adequate dynamic simulation responses. Further the proposed discrete speed estimation model has been applied experimentally over a PWM-driven 24-V, 12-teeth, 100-W PMDC brushed motor and various dynamic real-time responses have been compared with conventionally captured speed samples to validate the proposed model. [ABSTRACT FROM PUBLISHER]

In this paper, new half-bridge and full-bridge topologies for a switched-boost inverter are proposed. These topologies have a high boost factor in comparison with conventional types. In addition, the proposed topologies have continuous input current and can generate zero-voltage level in output. In this paper, the operation of the proposed inverters in different operating modes is analyzed. Then, the values of inductors and capacitors are designed. Moreover, the used switching pattern and its logical diagram are introduced. A comprehensive comparison between the proposed and conventional topologies in terms of the boost factor, the number of elements, and the efficiency shows the good features of the proposed inverters. Finally, to verify correct operation of the proposed topologies and derived equations, simulation and experimental results are presented. [ABSTRACT FROM AUTHOR]

The nine-switch converter is a multiport converter having two three-phase terminals and a dc-link, just like a 12-switch back-to-back (BTB) converter, but with 25% reduction of active switch count. However, the reduction from 12-switch to 9-switch may not always be an efficient choice considering losses in the switches. Only the load–source combination for the ac–ac common frequency mode and the source–source combination for the ac–dc different frequency (ac–dc DF) mode have been reported, so far, to yield relatively lower loss for the nine-switch converter. This paper shows that the nine-switch converter can have relatively lower loss even with a load–source combination, instead of only source–source combination in its ac–dc DF mode—when the upper terminal is connected to a dc load and the lower terminal is connected to an ac source. Mathematical proof is presented with derivation of the particular operating parameters for which the nine-switch converter will have comparatively lower losses. The analysis is validated with simulation and experimental results of a 1-kW system. Finally, the benchmark of the application criteria of the nine-switch converter for having lower conduction loss than the BTB converter is updated in this paper. [ABSTRACT FROM AUTHOR]

For power converters with inductive loads, a freewheeling path is needed for the current due to reactive power. The MOSFET synchronous rectification (SR) is widely used to reduce the conduction loss during the freewheeling period. Due to the wide band gap of silicon carbide (SiC), the intrinsic body diode of SiC MOSFET exhibits a high voltage drop. Hence, an antiparallel SiC Schottky diode is normally implemented to eliminate its conduction. However, the external SiC Schottky diode is not fully utilized as it only works during the dead time. In this paper, the hard-switching SR is investigated in an SiC three-phase inverter and compared with a conventional inverter using freewheeling diode (FWD). An improved power loss model for the two inverters has been developed. It is found that the inverter using SR has higher efficiency due to the smaller switching loss. A 7-kW prototype of SiC three-phase inverter is built, which achieves a peak efficiency of 98.8% ($\pm$ 0.15%) and 98.5% ($\pm$ 0.15%) at 40 kHz using SR and FWD, respectively. This paper confirms that the SiC MOSFET is an ideal candidate for the SR. [ABSTRACT FROM PUBLISHER]

A high-voltage tapped-inductor buck converter utilizing a novel autonomous high-voltage valve is presented in this paper. Its application as auxiliary power supply for high-power cascaded-converter submodules is discussed, followed by a presentation of the most challenging problems in designing a low-power high-voltage step-down converter. The TI-buck converter topology is analyzed, which together with the novel autonomous high-voltage valve overcomes most of the problems. Analytical expressions describing the operation as well as circuit simulations are presented. Finally, an experimental evaluation of a 3-kV 70-W prototype converter utilizing the proposed autonomous high-voltage valve with series-connected super-junction MOSFETs is presented. [ABSTRACT FROM PUBLISHER]

Modular multilevel converter (MMC) has been one of the most popular candidates in high-voltage applications. However, reliability is a critical issue due to a large number of power switching devices and capacitors applied in the MMC. To improve the reliability of the MMC, a fast and reliable diagnosis strategy for the open-circuit fault is proposed in this paper, where submodule voltage sensors are relocated to the upper switching device. Furthermore, a voltage observer based on the submodule voltage sensor is established to monitor the capacitor and realize the power control of the MMC under normal operation. A Boolean logic operation based fault indicator is put forward based on the relationship of the operation state and binaried output of voltage sensors, which could detect and locate the open-circuit faults of the MMC very fast. The ratio of the increment of the observed and measured capacitor voltage during the period of positive arm current is applied to monitor the capacitor. The effectiveness of the proposed fault diagnosis strategy and the capacitor monitoring strategy is verified by the experiment results. [ABSTRACT FROM AUTHOR]

Partial discharge (PD) detection is a fundamental tool for the design and diagnosis of insulation systems, particularly organic materials that must operate throughout their life without PD. While the methods for PD measurements under sinusoidal supply voltage are well-established, the same does not hold under repetitive-pulse voltage waveforms, such as those provided by inverters. Electromagnetic noise generated by electronic switch commutation in inverters can overlap with PD pulses, making it difficult to measure, separate from noise, and identify PD. This is particularly more cumbersome when fast rise-time switches are employed. To address these issues, this paper investigates methods to detect PD pulses on enameled wires under repetitive impulsive voltages with different rise times of 60, 500, and 1000 ns, proposing techniques which allow separation of PD from noise even when they overlap in time and frequency domains. This paper employs a time-domain approach using standard deviation curve acquired from a set of measurements to discriminate PD from repetitive commutation disturbance. These techniques can be implemented to achieve unsupervised noise rejection, which would be an important goal for both offline and online PD testing. The proposed approach is validated successfully through tests carried out on a low-voltage motor. [ABSTRACT FROM AUTHOR]

Conventional voltage balancers for the bipolar low-voltage dc (LVdc) distribution system have been composed of multiple power stages, which degrade their power density and cost effectiveness. To minimize the power stages, this paper presents a single-stage voltage balancer with high-frequency isolation. This voltage balancer is based on the three-level dual-active-bridge converter. Furthermore, for the proposed voltage balancer, an enhanced switching modulation, using the two switching patterns $\alpha$ and $\beta$ , is proposed to fully balance the bipolar voltage level under unbalanced load condition and even for when one of the dc poles has no load. Besides, a closed-loop control system can be implemented by using output voltage information and proportional-integral controllers. Finally, experimental results using a 3-kW laboratory prototype converter verify the effectiveness of the proposed voltage balancer. [ABSTRACT FROM AUTHOR]

This paper presents an improved rotating restart method for a sensorless permanent magnet synchronous motor (PMSM) drive system using repetitive zero voltage vectors. To restart the sensorless PMSM drive system, a method for estimating initial rotor position and speed is required due to the absence of sensors such as encoders and resolvers. The rotor position and speed can be estimated using the short-circuit current vectors generated by applying zero voltage vectors. However, the estimated rotor position and speed can be inaccurate. The inaccurate rotor position that causes the current is distorted by the back-electromotive force of the PMSM, and it is impossible to precisely control the system. Therefore, an improved rotating restart method for the sensorless PMSM drive system using repetitive zero voltage vectors is proposed. The effectiveness of the proposed method is verified through simulation and experimental results using a 5-kW PMSM drive system. [ABSTRACT FROM AUTHOR]

In this paper, a voltage sensorless controller is developed for a two-switch single-phase rectifier that involves power factor correction and active pulsating power buffering without electrolytic capacitors. While a two-switch rectifier normally requires four sensed signals for control, only one current sensor is required in this proposal, thereby offering advantages such as low cost, high compactness, isolation between control and power circuits, and improved reliability. While the basic operating principle follows that of a conventional voltage sensorless controller for single-switch converters, several critical design considerations are the key to the success of the implementation which is explained in detail. The feasibilities of the controller are experimentally testified with a 100-W rectifier prototype regarding both steady state and dynamic performance. [ABSTRACT FROM AUTHOR]

In this paper, many impedance-source inverters with coupled inductors have been investigated to obtain a high step-up boost ratio. However, the leakage inductors in these topologies induce great voltage spikes at the dc link, which will increase the voltage stress of switches. Thus, the power level of inverters is limited. Furthermore, the efficiency of the inverters can be degraded by the losses associated with leakage inductors. To address abovementioned issues, this paper proposes a family of low-spike high-efficiency Y-source inverters. The proposed inverters have the ability of eliminating voltage spikes at the dc link and recycling the leakage energy via the additional diode and capacitor. In order to show the excellent characteristics of the proposed topologies, this paper compares the performances of the proposed inverters and the improved-Y-source inverter in many aspects. Simulation and experimental results have verified the abilities of the proposed inverters. [ABSTRACT FROM AUTHOR]

Power flow control in multiterminal HVdc (MTdc) grids is essential to restrict operation within permissible limits. A current flow controller (CFC) can achieve this. In this paper, the modeling, control, and simulation of resistive, RC-circuit-based, and capacitive CFCs is carried out. CFC prototypes have been developed and an MTdc grid test-rig has been employed for experimental validation. Results show that all devices achieve an effective power flow management. The impact of CFC deployment in future MTdc grids is assessed on droop-controlled converters. A voltage compensation-based method is proposed to minimize power deviations during unscheduled line current control. A protection scheme has been assessed under faults. [ABSTRACT FROM AUTHOR]

In this paper, a novel transformerless interleaved high step-down conversion ratio dc–dc converter with low switch voltage stress is proposed. In the proposed converter, two input capacitors are series-charged by the input voltage and parallel-discharged by a new two-phase interleaved buck converter for providing a much higher step-down conversion ratio without adopting an extreme short duty cycle. Based on the capacitive voltage division, the main objectives of the new voltage-divider circuit in the converter are for both storing energy in the blocking capacitors for increasing the step-down conversion ratio and reducing voltage stresses of active switches. As a result, the proposed converter topology possesses the low switch voltage stress characteristic. This will allow one to choose lower voltage rating MOSFETs to reduce both switching and conduction losses, and the overall efficiency is consequently improved. Moreover, due to the charge balance of the blocking capacitor, the converter features automatic uniform current sharing characteristic of the interleaved phases without adding extra circuitry or complex control methods. The operation principles and relevant analysis of the proposed converter are presented in this paper. Finally, a 400-V input voltage, 25-V output voltage, and 400-W output power prototype circuit is implemented in the laboratory to verify the performance. [ABSTRACT FROM PUBLISHER]

In this paper, a design method is proposed for finding the equivalent inductance and capacitance of the single-ended primary-inductor converter (SEPIC). The relations of the output voltage ripple (OVR) of the SEPIC converter are obtained in complete inductor supply mode–continuous conduction mode (CISM-CCM), incomplete inductor supply mode-CCM (IISM-CCM), and IISM-discontinuous conduction mode (IISM-DCM). The maximum of OVR (MOVR) is investigated for a specified range of the input voltage and load resistance. This value of the MOVR is obtained for the minimum values of input voltage and load resistance. In this paper, the minimum values of the equivalent inductance and capacitance are calculated in obtaining the minimum value of the MOVR. One of the other performed studies in this paper is calculation of the switch peak current in CCM and DCM. In addition, the converter is designed based on the minimum values of the MOVR and stress of the switching current. Experimental and simulation results are used to prove the validity of the presented theoretical subjects. [ABSTRACT FROM PUBLISHER]

The Z-source inverter (ZSI) employs an LC impedance network between the main inverter bridge and the power source. The unique feature of the ZSI is that it can operate either in buck or boost mode with a wide range of obtainable output voltages from a given input voltage. This topology also exhibits better electromagnetic-interference noise immunity when compared to a traditional voltage-source inverter (VSI). However, the LC impedance network of ZSI significantly increases the size and cost of the power converter and can make it unsuitable for low-power applications. This paper proposes a novel topology called switched boost inverter (SBI) which exhibits similar advantages of ZSI with lower number of passive components and more active components compared to ZSI. The steady-state and small-signal analyses of SBI, along with its pulsewidth modulation (PWM) control strategies, have been discussed in this paper. This paper also presents a comparison of SBI and ZSI with the same input and output parameters. The theoretical analysis given in this paper has been validated using a laboratory prototype of SBI, and the experimental results are presented for verification. The experimental harmonic spectrum of the inverter's output voltage with the proposed PWM technique is also plotted and compared with that of a traditional VSI. All the experimental results show good correlation between theory and experiments. [ABSTRACT FROM PUBLISHER]

This paper proposes a wide-range zero-voltage-switching (ZVS) active-clamped current-fed push–pull converter for fuel cell application. The presented converter achieves ZVS for all of the primary switches and ZCS for secondary diodes from rated load to 10% full load over the wide input voltage variation, improving the overall efficiency. The ZVS of switches is realized by the energy stored in the transformer leakage inductance aided by the secondary parallel inductor. An additional active clamping circuit suppresses the voltage spike as well as assists in realizing ZVS of switches. Low-voltage-rated switches with low on-state resistance can be used. Moreover, the voltage-doubler rectifier is adopted to release the reverse-recovery problem of rectifier diodes and reduce turns ratio of the high-frequency transformer. Detailed steady-state operation, analysis, design, control, comparative study, and experimental results are discussed in depth in this paper. Finally, a 200-W prototype has been built in the laboratory to verify the effectiveness of the proposed converter. [ABSTRACT FROM PUBLISHER]

In this paper, a new structure for symmetric and cascade multilevel converter is presented. This structure requires the least power electronic components, gate driver circuits, power diode, and dc voltage source. The number of output levels is high. Reduction of the number of power electronic switches against voltage levels is an important factor in multilevel converters due to safety in switches, circuit size, cost, installation area, and complexity in control. To maximize the number of output level in the proposed optimized structure in order to attain different goals, such as reduction of stress on switches, the result of comparing the proposed structure and other structures present. The proposed method is robust against the switching faults in multilevel converter for dc source and the equipment. The simulation and experimental results presented in this paper show the performance of the proposed method. [ABSTRACT FROM AUTHOR]

The large number of semiconductors typically implemented in multilevel converters generates large stray inductances in their commutation loops. As a consequence, high-voltage overshoots appear in the semiconductors during commutation which may limit the operation of the converter. The paper analyzes these overvoltages in the five-level active neutral-point-clamped (5L­ANPC) converter, one of the most popular five level converters and employed by ABB in its ACS­2000 drive. Experimental results show overvoltages almost three times higher than those corresponding to a two-level converter. In order to overcome this problem, the paper presents a new 5L­ANPC with the same characteristics (number of semiconductors, output waveform, switching frequency, efficiency, etc.), but with smaller overvoltages. This is achieved by adding some small capacitors to the busbar that behave like lossless snubbers but with a much simpler implementation. The experimental results illustrate the working principle of these capacitors and demonstrate the reduction of the overvoltages. As a result, the new converter can reach a higher output current or speed-up the commutations reducing, therefore, the losses and increasing the efficiency compared with the previous 5L­ANPC. [ABSTRACT FROM AUTHOR]

Thanks to the favorable advantage of low cost, integrated three-port dc–dc converters with reduced switches have attracted extensive attention. In order to provide more new topologies, this paper aims to propose a programmable topology derivation method, which effectively simplifies the cumbersome process of the conventional combination method. Instead of the manual connection and examination, the proposed alternative can quickly and rigorously derive multiple viable integrated three-port dc–dc topologies from a great number of possible connections with the aid of computer program. Besides, generalized analysis is also accomplished, with which performance characteristics of all derived converters are simultaneously obtained and then a comprehensive comparison can be easily conducted to select a preferred one for the practical application. Finally, an example-specific application with one input and two outputs is given, with topology selection, design, and experimental results demonstrated in detail. [ABSTRACT FROM AUTHOR]

This paper proposes a capacitor voltage regulation method for the dual converter with a floating bridge for aerospace applications. This topology has previously been reported, but with a constrained voltage utilization factor due to the need for capacitor voltage regulations. In this paper, the effect of switching states on the voltage variation of capacitor is quantitatively modeled and an enhanced space vector modulation scheme with current feedback is proposed to achieve an active control of the floating capacitor voltages. This proposed method also allows further exploitation and utilization of converter voltage. The relationship between the allowed modulation index of dual converter and load power factor is obtained and expressed using a fitted polynomial equation. The advantages of the proposed method include boosted voltage utilization and superior performance in term of capacitor voltage balance. These advantages have been proven through simulation and experimental results on RL loads as well as with an open-end winding induction motor. The proposed modulation scheme can boost the converter voltage utilization by at least 10% while achieving full four-level operation. More importantly, the higher available voltage allows extending the constant torque region of the motor, the further beginning of field weakening operation could be postponed. [ABSTRACT FROM AUTHOR]

This paper proposes a dual-function dynamic voltage restorer (DFDVR) with fault current-limiting capability. The new topology can operate under different modes: the short-circuit fault current-limiting mode and the compensation mode for voltage fluctuation. Different functions of the DFDVR are achieved by controlling a brake chopper circuit and antiparallel thyristors. During fault conditions, the antiparallel thyristors are deactivated to protect the dc-side capacitor, and the duration of the on- and off-periods of the semiconductor switch in the brake chopper circuit is controlled to adjust fault current amplitudes. During voltage sags, the antiparallel thyristors are activated, and the brake chopper circuit is turned off by controlling the gate turn-off thyristor in the brake chopper circuit, thus making the DFDVR similar to a conventional DVR. The control scheme and optimal parameter selection of the DFDVR are provided. The design methodology of the DFDVR was verified through simulations performed using the PSCAD/EMTDC software. The experimental results prove the capability and effectiveness of the DFDVR topology. [ABSTRACT FROM AUTHOR]

When fast voltage control is used in a power factor control, the ripple of the dc link causes current harmonics. This paper proposes a method to reduce the harmonic content of a fast voltage loop in a power factor correction, which can both produce low distortion during steady-state operation and fast recovery from a load transient. The performance is achieved by using a Takagi–Sugeno-type nonlinear controller for dc-link voltage control. The proposed nonlinear control is compared with linear proportional–integral (PI) control, which is tuned to meet the standardized regulations for the harmonic content in a 3-kW single phase power supply. The results show that the presented nonlinear voltage controller can maintain the dynamic performance of the linear control with reduced current harmonics. It is also shown that the used nonlinear control method requires only marginally more complex control algorithm compared to commonly used linear PI control. [ABSTRACT FROM AUTHOR]

The extra-LC auxiliary-resonant-snubber-based converter (ELCARSC), as a soft-switching converter, has the advantages of low switching loss, low electromagnetic interference noise, and low-output distortion caused by the dead-time effect. However, the dead-time effect is still the main problem in a high-precision application. Besides, the traditional control and compensation methods rely on the accuracy of the circuit parameters, especially the junction capacitance, thus resulting in compensation error. Therefore, this paper proposed a novel high-precision control method through modulating the initial resonant current to eliminate the dead-time effect of ELCARSC. The method does not need complicated online calculation and reduces the dependence on the accuracy of the circuit parameters, especially the influence of the junction capacitances of the switches. In this paper, the dead-time effect of the ELCARSC is analyzed. The output voltage error with the conventional variable-timing control method is analyzed. Subsequently, the proposed modulated initial resonant current control is introduced. Finally, a prototype was developed that verified the effectiveness of the control method. The quality of the output current and voltage is improved by utilizing the proposed control method. However, the peak current of the auxiliary switch is increased. [ABSTRACT FROM AUTHOR]

This paper presents a sinusoidal pulsewidth modulation (SPWM) based direct digital control with average-voltage model (AVM) and division–summation process for paralleled three-phase three-wire (3φ3W) grid-connected converters to reduce circulating currents. With the direct digital control, plant of each single-phase converter can be derived directly, and a controller is then designed to cover the variation effects of filter inductance and grid voltage. Based on SPWM and AVM over a switching cycle, each 3φ3W converter can be decomposed into three single-phase converters and each converter is controlled individually to track its sinusoidal reference current tightly, reducing circulating currents significantly. Equal current sharing is therefore also achieved. The control laws for achieving grid connection are derived in detail. In the design and implementation, the inductances corresponding to various inductor currents are measured offline and stored in the controller for scheduling loop gain cycle by cycle. Experimental and simulated results from a three-converter system confirm the analysis and discussion of the proposed control approaches. [ABSTRACT FROM AUTHOR]

A trinary multilevel converter uses a few heterogeneous H-bridge submodules (SMs) to synthesize an output voltage with multiple levels. Two major limitations of this converter are that it needs multiple dc sources and it cannot operate under pulsewidth modulation (PWM). This paper addresses these limitations by adding a low-voltage H-bridge SM to this converter and proposing a new switching algorithm. The resulting PWM-based asymmetric cascaded H-bridge converter uses only one dc source and synthesizes a high-quality output voltage. This improved converter can be a potential choice for real and reactive power support in power system applications. This paper also proposes methods for stability analysis and design of this converter. Experimental case studies evaluate the performance of the proposed converter for both standalone and grid-connected modes of operation. [ABSTRACT FROM AUTHOR]

In this paper, performances on two kinds of aggregated flyback microinverters are compared in aspect of harmonic resonances, which are controlled by current feedback control and peak current control. Based on the Norton models of flyback microinverters obtained by a small-signal modeling approach, potential harmonic resonances with the grid are analyzed. Following that, an impedance-based stability criterion is proposed, where the resonance frequency can be calculated and predicted based on the derived Norton models and the system admittance matrix of aggregated microinverters. After comprehensive analysis and comparisons, it is found that the peak-current-control-based flyback microinverters has better performance on damping the harmonic resonances than the current feedback controlled one. Simulations and experiments are carried out for verifying the effectiveness of the presented models and the correctness of the analysis results. [ABSTRACT FROM AUTHOR]

In this paper, a new nonisolated high step-up dc–dc converter is proposed. Active–passive inductor cells (APICs) are used to extend the topology. The ability to achieve high gains is the main merit of the proposed topology. The proposed converter operates based on parallel charging and series discharging of the inductors. The converter also achieves high step-up voltage gain with appropriate duty cycle and low voltage and current stress on the power switches and diodes. The proposed converter is analyzed in operation modes. The main parameters of the converter such as voltage gain, voltage stress of semiconductor devices are calculated to compare with other structures. Considering the output voltage ripple and filter size, the proposed converter is designed. Moreover, the losses and efficiency of the converter are calculated. The performance of the proposed converter is validated by experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a model predictive control technique applied to a dual-active bridge inverter where one of the bridges is floating. The proposed floating bridge topology eliminates the need for isolation transformer in a dual inverter system and therefore reduces the size, weight, and losses in the system. To achieve multilevel output voltage waveforms, the floating inverter dc-link capacitor is charged to the half of the main dc-link voltage. A finite-set model predictive control technique is used to control the load current of the converter as well as the floating capacitor voltage. Model predictive control does not require any switching sequence design or complex switching time calculations as used for space vector modulation; thus, the technique has some advantages in this application. A detailed analysis of the converter as well as the predictive control strategy is given in this paper. Simulation and experimental results to validate the approach are also presented. [ABSTRACT FROM PUBLISHER]

In this paper, a nonisolated bidirectional dc–dc converter is presented. The proposed converter consists of two boost converters to enhance the voltage gain. Four power switches with their body diodes are employed in the proposed converter. Also, two inductors and a capacitor are used as passive components. The input current is divided to the inductors which causes the efficiency to be high. The voltage gain of the proposed converter is higher than the conventional cascaded bidirectional buck/boost converter (CCBC) in step-up mode. Besides, the voltage gain in step-down mode is lower than CCBC. Besides, the efficiency of the proposed converter more than CCBC while the total stress on active switches are same. The simple structure of the proposed converter causes its control to be easy. The steady-state analysis of the proposed converter is discussed in this paper thoroughly. The stress on converters’ devices and the efficiency of the proposed converter and CCBC are compared in this paper. Finally, the proposed converter prototype circuit is implemented to justify the validity of the analysis. [ABSTRACT FROM PUBLISHER]

Phase-shifted carrier modulation is an industry standard in its application to multilevel H-bridge converters. The major advantage of this scheme over level-shifted and space vector modulation schemes is its inherent ability to evenly distribute losses between semiconductor devices. However, phase-shifted schemes suffer from harmonic degradation when operated at the low carrier frequencies required in high-power high-level number applications. This paper develops a model predictive modulation (MPM) scheme that achieves superior harmonic performance, compared to phase-shifted modulation, while ensuring equal semiconductor loss distribution. With respect to complete-enumeration-based predictive techniques, the proposed modulation significantly reduces the number of times the system cost function is evaluated. Reducing the number of calculations by several orders of magnitude ensures computational feasibility. Simulation and experimental results are presented, which confirm correct operation of the modulation strategy. [ABSTRACT FROM PUBLISHER]

Two three-level inverters driving an open-end winding induction motor can generate equivalent voltage waveforms as a single five-level inverter-based drive. In addition, it can bring in benefits such as reduced dc-link voltage, less number of devices, and fault-tolerant capability, which is favored in high-power motor drive applications. The main challenge with this type of configuration is the appearance of large zero-sequence current circulating between the two inverters, which generates extra losses in the switching devices and the motor as well as affects the normal operation of the machine. Another challenge is to balance the dc-link neutral point voltage of the two three-level inverters. This paper has proposed a simplified decoupled space-vector pulsewidth-modulation (PWM) strategy to eliminate the averaged zero-sequence voltage in each switching cycle by the placement of redundant vectors of each individual inverter using a time shift. Neutral point voltage balance is further achieved by adjusting the time duration of the redundant vectors. In this paper, it is shown that it is possible to operate this kind of drive configuration with a single dc power supply and achieve averaged zero-sequence voltage elimination and neutral-point voltage balancing at the same time. Experimental results of a 5.5-kW dual three-level inverter drive using the proposed PWM strategy are presented, which validates the control method and drive configuration. [ABSTRACT FROM PUBLISHER]

This paper presents a comprehensive analysis of the current-stress optimization and soft-switching operation of the isolated bidirectional dual active bridge (DAB) dc–dc converter with the unified triple-phase-shift (UTPS) control. On this basis, the current-stress-optimized modulation scheme is proposed for DAB, which leads to the minimum current stress with the required transmission power and voltage conversion ratio in the whole load range. Moreover, the full soft-switching operation is achieved for the converter simultaneously. Distinct from the previous modulation schemes, the proposed optimized modulation scheme is deduced from a unified analysis of TPS where all effective switching modes are investigated. A novel algorithm based on the Karush–Kuhn–Tucker (KKT) conditions is originally proposed to derive closed-form solutions for the global optimal control parameters. This paper also presents a typical closed-loop control strategy for DAB with TPS control and detailed descriptions about the closed-loop operation. A laboratory prototype is applied, and the experimental results validate that the current-stress optimization and efficiency improvement are realized by applying the optimized modulation scheme. The experimental results also verify the effectiveness of the closed-loop control strategy for DAB with TPS control. [ABSTRACT FROM PUBLISHER]

Proper use of phase-controlled switching technology by controlling the making or breaking of the circuit breaker (CB) at predetermined phase angles of current or voltage can improve the service life of the CB, avoid relay protection device from mal-operation, and reduce the impact on the power grid when power equipment or load is energized or taken out. This paper proposes a novel phase-controlled switching method to address the influence of residual flux for three-phase wye winding unloaded transformers with three limbs, such as large capacitor variable frequency transformer or mine explosion-proof transformer. The optimal operation phase angle for CBs is firstly obtained via theoretical analysis. A model based on the alternative transients program/the electromagnetic transients program (ATP/EMTP) is then built to simulate the transient procedure of a power transformer during breaking and making. The simulated results confirm that the proposed switching strategy can reduce the excitation inrush current effectively when the unloaded transformers are energized. The experimental results reported in this paper are used to validate the accuracy and effectiveness of the phase-controlled switching strategy. [ABSTRACT FROM PUBLISHER]

A new pulsewidth modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is proposed in this paper. A three-level NPC inverter is completely mature and very well-established topology in high-power applications. However, the three-level NPC inverter has an inheritance problem of the neutral-point voltage unbalancing due to the split dc-link capacitors. This structure can cause large neutral-point voltage ripple. Furthermore, output currents of the three-level NPC inverter are distorted by the neutral-point voltage ripple. Therefore, the neutral-point voltage must be controlled. In this paper, a new DPWM method using two different offsets for the neutral-point ripple reduction is proposed and the effectiveness of the proposed DPWM method is verified by using the simulation and the experimental results. [ABSTRACT FROM PUBLISHER]

The traditional space-vector pulsewidth modulation (SVPWM) maximum voltage transfer ratio (VTR, i.e., the ratio of the output voltage fundamental amplitude to the input voltage fundamental amplitude) is 0.866 in a linear modulation region. In this paper, the output voltage fundamental amplitude and total harmonic distortion (THD) affected by a basic vector and a hexagon vector in traditional indirect SVPWM overmodulation are analyzed. The traditional indirect SVPWM overmodulation usually focuses on the inverter stage to improve the VTR, and there are few methods considering both of the inverter and rectifier stages to improve the overmodulation performance of a matrix converter (MC), including output voltage error, and output and input current THDs. In this paper, a new overmodulation method based on indirect SVPWM is presented. Both the output performance and input performance of the MC with the proposed and traditional overmodulation methods are emulated and tested. Simulation results indicate that the output voltage error and the input current THD are smaller and lower, respectively, with the proposed method. Experimental results verify that theoretical analysis is right, and the proposed overmodulation method is feasible. [ABSTRACT FROM PUBLISHER]

A four-level five-phase open-end winding (OeW) drive topology is introduced in this paper. The drive comprises a five-phase induction machine with open-end stator windings, supplied using two two-level voltage-source inverters with isolated and unequal dc-link voltages, in the ratio 2 : 1. The topology offers the advantages of a modular structure with fewer semiconductor components and has a greater potential for fault tolerance, as compared with an equivalent single-sided four-level drive. Due to the large number of switching states, development of a suitable space vector pulsewidth-modulation (PWM) method can be challenging. Hence, this paper examines the implementation of two-level-shifted carrier-based PWM methods. The effect of dead time on the drive performance is discussed, and it is shown that simultaneous PWM switching of both inverters can lead to degraded output phase voltage waveforms. Detailed analysis of this phenomenon is presented, a solution is proposed, and the modified modulation techniques are incorporated in an experimental setup, at first in conjunction with $V/f$ control. Once the proof of concept has been provided, full field-oriented control is implemented in this OeW drive topology for the first time; detailed experimental testing is conducted, and results are reported. [ABSTRACT FROM AUTHOR]

In this paper, a new cascaded multilevel inverter is proposed. For the proposed inverter, two different algorithms to determine the magnitude of the dc voltage sources are proposed. Then, in order to generate maximum numbers of output voltage levels by using a constant number of power switches and/or dc voltage sources, several optimum structures of the proposed inverter are obtained. In comparison with the conventional cascaded multilevel inverters, the proposed inverter is able to generate a high number of output voltage levels by using a lower number of power electronic devices such as power switches, driver circuits, power diodes, and dc voltage sources. In addition, the low amount of blocked voltage by switches is another advantage of the proposed inverter. The accuracy performance of the proposed inverter in generating the positive and negative voltage levels is verified through the experimental results on a 61-level inverter. [ABSTRACT FROM PUBLISHER]

This paper presents a capacitor voltage balancing control applicable to any multilevel dc–ac converter formed by a single set of series-connected capacitors implementing the dc link and semiconductor devices, such as the diode-clamped topology. The control is defined for any number of dc-link voltage levels and converter legs (for single-phase and multiphase systems), guaranteeing the capacitor voltage control for any modulation index value and load (from idle mode to full power). The associated control loop small-signal transfer function is presented, from which optimum compensator design guidelines are derived. The improvement in control performance is verified through simulation and experiments comparing with a previous balancing control strategy in a four-level three-phase dc–ac conversion system. The satisfactory control performance is also verified through simulation in a four-level five-phase dc–ac conversion system. [ABSTRACT FROM PUBLISHER]