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A novel single-phase transformerless dual-mode interleaved multilevel inverter (DMIMI) is proposed in this paper, which can inject a highly sinusoidal ac current to the grid even with the input dc voltage less than the peak grid voltage. Furthermore, dead-beat controllers are developed to directly calculate the optimal duty cycles in a digital control platform. As compared to the traditional dual-mode multilevel approaches, the DMIMI offers high efficiency, less number of components conducting simultaneously in each operation mode, and the capability of reactive power exchange. This paper presents the theoretical analysis and the experimental results obtained from a 1-kW prototype. The experimental results reveal that the proposed DMIMI can achieve high conversion efficiency and low leakage current as well as high quality grid current. [ABSTRACT FROM AUTHOR]

This paper analyzes the combination in a cascaded H-bridge multilevel inverter (CHBI) based on transformers with the different turn ratios for increasing the voltage level and proposes the switching method for achieving the output voltage distribution among H-bridge cells (HBCs). The transformers used in this paper are connected to the output of the respective HBCs, and the secondary sides of all the transformers are connected in series for generating the final output voltage. Only one of the transformers, in particular, has a different turn ratio for increasing the output voltage level. In this paper, the possible turn ratio of the special transformer with a different turn ratio is discussed in detail, and a switching method based on the level-shifted switching method for the topology used in this paper is proposed. To verify the effectiveness of the proposed method, a three-phase 21-level CHBI is experimentally tested. [ABSTRACT FROM PUBLISHER]

This paper presents the current control design procedure of a single-phase grid-tied five-level packed U-cell inverter (PUC5) with an LCL output filter. The PUC5 inverter is used as an interface of renewable energy sources, such as solar applications. The LCL filter is calculated according to the grid-tied operation and converter ratings. An optimal controller, based on a linear quadratic regulator with integral action, is designed to inject a sinusoidal current with low harmonic distortion at unity power factor. For that design, the PUC5 inverter is modelled in the D–Q frame. The sensorless voltage control is incorporated into the switching technique to balance the PUC5 capacitor voltage and generate a five-level waveform at the output. Experimental tests are performed on a laboratory benchmark to confirm the theoretical design. The results prove the efficiency and accuracy of the adopted control strategy in a steady state and under transients of grid current, grid inductance, ac and dc voltage amplitudes. [ABSTRACT FROM AUTHOR]

Zero-common-mode-voltage (CMV) operation of multilevel inverters results in reduced dc-bus utilization and reduced linear modulation range. In this paper, a method to increase the linear modulation range for zero-CMV operation without increasing the dc-bus voltage using a cascaded multilevel inverter with a single dc supply is presented. Using this method, the peak fundamental output voltage can be increased from 0.499 to 0.637  \textV\text{dc} with zero CMV inside the linear modulation range. Also, various pulse width modulation (PWM) switching sequences are analyzed in this paper, and the PWM sequence that gives minimum current ripple is used for the zero-CMV operation of the inverter. The inverter topology with single dc supply is realized by cascading a two-level inverter with two floating-capacitor-fed full-bridge modules. Simulation and experimental results for steady-state and dynamic operating conditions are presented to validate the proposed method. [ABSTRACT FROM AUTHOR]

Soft-switching inverters can achieve high efficiencies and low switchdv/dtanddi/dt, but often impose additional stress on the switches due to their resonant behavior. Multicell converters, on the other hand, can process high voltages by arranging the switches to share the stress. This paper proposes a buck–boost multicell soft-switching inverter with inherent cell voltage balancing. Both the current and voltage stresses are shared by the cells. Soft-switching conditions are achieved for all switching transitions without any need for auxiliary circuitry or clamps. A multiple-winding transformer transfers energy between the terminals and provides galvanic isolation. An analytical study and experimental results on a 1200-W prototype verify the operation of the inverter. [ABSTRACT FROM AUTHOR]

Different modulation methods have been proposed to control the multilevel inverters. This paper focuses on the staircase modulation that is very popular for multilevel inverters with low switching frequencies. Nonreal-time algorithms for the staircase modulation cannot be applied practically in multilevel inverters with varying voltage steps, since the sizes of lookup tables would be huge. We propose a real-time algorithm for multilevel inverters with unequal or varying voltage steps under the staircase modulation. The algorithm results in the minimal total harmonic distortion (THD) of the output voltage of the inverter, which is proved by rigorous mathematical derivations in this paper. A new expression of THD is presented to simplify the derivation significantly. Computational complexity of the algorithm is analyzed to estimate the time cost of the calculation. We implemented the algorithm on a digital signal processor and provide experimental results that verify the performance of the proposed algorithm. [ABSTRACT FROM AUTHOR]

The open-loop control scheme presented in part I of this paper for a dual five-level-inverter-fed induction motor (IM) drive with two dc power supplies maintains dc-link capacitor voltage balancing and common-mode voltage (CMV) elimination throughout the operating range of the drive. The operating limitation of the proposed open-loop control scheme to take corrective action toward the existing unbalance in the dc-link-capacitor voltages is also pointed out in part I of this paper. As a solution to this, a simple closed-loop control scheme, which is based only on the switching-state redundancy, is proposed in this part of the paper. The proposed closed-loop control scheme not only prevents further unbalancing of capacitor voltages but also takes corrective actions to bring back the capacitor voltages in the balanced state. The proposed closed-loop scheme achieves dc-link capacitor voltage balancing and elimination of CMV together in the complete modulation range, including overmodulation of up to the 24-step operation. The proposed control scheme does not affect the output fundamental voltage generated by the inverter, as it effectively utilizes only the availability of redundant switching states of the inverter, and does not call for additional power circuit hardware. The scheme is presented with the simulation studies and experimentally verified with a 1.5-kW open-end winding IM drive. [ABSTRACT FROM AUTHOR]

In this paper, two new topologies are proposed for multilevel inverters. The proposed topologies consist of a combination of the conventional series and the switched capacitor inverter units. The proposed topologies reduce the number of switches and isolated dc voltage sources, the variety of the dc voltage source values, and the size and cost of the system in comparison with the conventional topologies. In addition, the proposed topologies can double the input voltage without a transformer. There is no need for complicated methods to balance the capacitor voltage. The simulation and experimental results of single-phase 25- and 17-level inverters are given to prove the correct operation of the proposed topologies. [ABSTRACT FROM PUBLISHER]

In this paper, a new general cascaded multilevel inverter using developed H-bridges is proposed. The proposed topology requires a lesser number of dc voltage sources and power switches and consists of lower blocking voltage on switches, which results in decreased complexity and total cost of the inverter. These abilities obtained within comparing the proposed topology with the conventional topologies from aforementioned points of view. Moreover, a new algorithm to determine the magnitude of dc voltage sources is proposed. The performance and functional accuracy of the proposed topology using the new algorithm in generating all voltage levels for a 31-level inverter are confirmed by simulation and experimental results. [ABSTRACT FROM PUBLISHER]

For large-scale photovoltaic (PV) systems, the multistring configuration is becoming more and more attractive compared with the classical central inverter, since it results in better energy yield by realizing distributed maximum power point tracking. Among the existing solutions, an attractive topology consists in a single dc bus bar collector cascaded H-bridge (CHB) inverter. Through the use of a single dc bus bar collector, the CHB inverter presents inherent balanced operation while the multistring PV-system is fully decoupled from the grid-tie inverter. This paper proposes the experimental validation of this structure on a reduced-size single-phase laboratory prototype. Results confirm the interest of the proposed PV multistring architecture. [ABSTRACT FROM AUTHOR]

Several pulsewidth modulation (PWM) strategies have been proposed for three-phase multilevel converters. Typically, these PWM methods can be either space-vector or carrier-based implemented, where the carrier-based implementation usually presents a lower computation complexity. In this paper, a novel approach for the carrier-based implementation of different existing PWM methods is proposed for three- (3L) and four-level (4L) dc–ac converters, which can be easily extended to any number of levels. The main features of the proposed approach are its reduced computation complexity and computation time. On the other hand, the proposed approach suggests the derivation of novel PWM strategies which can potentially present improved performance features. As an example, two new discontinuous PWM (DPWM) strategies are proposed for the 4L converter. One of these DPWM strategies presents lower weighted total harmonic distortion than other previously proposed strategies. Simulation and experimental results verify the effectiveness of the proposed approach and novel DPWM strategies. [ABSTRACT FROM AUTHOR]

A new single-phase \uppi-\texttype 5-level inverter using 3-terminal switch-network (3TSN) is proposed in this paper. The topology is considered as a variant of T-type 3-level structure or dual-buck inverter with coupled inductors. This new inverter is suitable for multilevel power inversion with low dc-bus voltage. The merit of the proposed topology is to apply only four active power switches to achieve 5-level operation. Other benefits include double frequency operation of output inductor and equal division of the current that flows through power switches and filter inductor. Hence, it leads to high efficiency and low harmonics. These characteristics allow improvement of losses distribution and volume reduction of output filter inductor. The operation scenario with sinusoidal pulsewidth modulation (SPWM) is described in details. Meanwhile, the magnetic analysis and design are studied and discussed. Finally, a prototype is built to verify the theoretical analysis and demonstrate the benefits of the proposed topology. [ABSTRACT FROM AUTHOR]

A new approach for modulation of an 11-level cascade multilevel inverter using selective harmonic elimination is presented in this paper. The dc sources feeding the multilevel inverter are considered to be varying in time, and the switching angles are adapted to the dc source variation. This method uses genetic algorithms to obtain switching angles offline for different dc source values. Then, artificial neural networks are used to determine the switching angles that correspond to the real-time values of the dc sources for each phase. This implies that each one of the dc sources of this topology can have different values at any time, but the output fundamental voltage will stay constant and the harmonic content will still meet the specifications. The modulating switching angles are updated at each cycle of the output fundamental voltage. This paper gives details on the method in addition to simulation and experimental results. [ABSTRACT FROM PUBLISHER]

This paper proposes a high step-up dc-dc converter based on the Cockcroft-Walton (CW) voltage multiplier without a step-up transformer. Providing continuous input current with low ripple, high voltage ratio, and low voltage stress on the switches, diodes, and capacitors, the proposed converter is quite suitable for applying to low-input-level dc generation systems. Moreover, based on the n -stage CW voltage multiplier, the proposed converter can provide a suitable dc source for an n + 1-level multilevel inverter. In this paper, the proposed control strategy employs two independent frequencies, one of which operates at high frequency to minimize the size of the inductor while the other one operates at relatively low frequency according to the desired output voltage ripple. A 200-W laboratory prototype is built for test, and both simulation and experimental results demonstrate the validity of the proposed converter. [ABSTRACT FROM PUBLISHER]

In this paper, total harmonic distortion (THD) minimization of the output voltage of multilevel inverters is discussed. An efficient approach in reducing the harmonic contents of the inverter's output voltage is THD minimization. In multilevel inverters with a fundamental frequency switching strategy (each switch turning on and off once per output cycle), the switching angles can be selected so that the output THD is minimized (such as the so-called optimal-minimization-of-THD strategy). To obtain the optimum switching angles, an optimization algorithm is applied to the output-voltage THD. In three-phase multilevel inverters, the optimization algorithm is commonly applied to the phase voltage of the inverter. This results in the minimum THD in phase voltage but not necessarily in the line-to-line minimum THD, whereas in three-phase applications, the line-voltage harmonics are of the main concern from the load point of view. In this paper, using the genetic algorithm, a THD minimization process is directly applied to the line-to-line voltage of the inverter. This paper is based on a seven-level inverter. To verify the simulation results, a seven-level-cascaded-H-bridge-inverter-based hardware prototype, including an ATMEGA32 AVR microcontroller, has been implemented. Both simulation and experimental results indicate superiority of this approach over the commonly used phase-voltage THD minimization approach. [ABSTRACT FROM AUTHOR]

This paper proposes a new space-vector pulsewidth modulation (SV-PWM) strategy for a three-level neutral point clamped inverter. The presented SV-PWM strategy makes it possible to control the neutral point voltage by optimum choice of switch sequence for any position and length of output voltage vector. The proposed solution takes into consideration the unbalance of the dc-link voltages. It also analyzes the influence of vector sequences on the predicted unbalance of the dc-link voltage. The solution allows selecting optimum vectors and their on-time durations in order to reduce quickly the dc-link voltage unbalance. The calculation of the space vector area proposed in this paper takes into consideration voltage unbalance and its influence on the length and position of vectors. The proposed approach assures properly generating the voltage output vectors, even in the case of the existing large voltage unbalance in the dc-link. The results of the experimental investigation of the proposed modulation strategy are presented in this paper. [ABSTRACT FROM PUBLISHER]

In this paper, the application of a cascaded multilevel inverter as a dynamic voltage restorer (DVR) is investigated. Two discontinuous multilevel space vector modulation (SVM) techniques are implemented for DVR control and are shown to reduce inverter switching losses while maintaining virtually the same harmonic performance as the conventional multilevel SVM at a high number of levels. This paper also presents a mathematical relationship for computing the distortion at the point of common coupling (PCC) as a function of the distortion of the DVR. This enables the selection of the number of levels required for a certain application. An extended sag duration support compared to the two-level DVR is another advantage of the DVR with a cascaded multilevel inverter. The common-mode voltage (CMV) at the PCC has been evaluated for the three SVM techniques (the conventional multilevel SVM and the two discontinuous SVM), presenting a lower CMV for the second discontinuous SVM. A design example is presented for an 11-kV 5-MVA DVR multilevel cascaded inverter for up to 17 levels, employing the conventional multilevel SVM and the two discontinuous SVM techniques. [ABSTRACT FROM AUTHOR]

In this paper, the authors propose a mathematical model for a new topology called "stacked multicell converter" (SMC). Each phase of the SMC n x m multilevel inverter is formed by a stack of m flying-capacitor multilevel inverters, and each stack or stage is realized by connecting in series n controllable commutation cells. An original multicarrier subharmonic pulsewidth modulation (PWM), called disposition band carrier and phase-shifted carrier PWM (DBC-PSC-PWM), method is developed to produce (n x m + 1) output voltage levels and to improve the output voltage harmonic spectrum with a wide output frequency range. A diagram state machine is then used to decode the DBC-PSC-PWM modulator and distribute the commutations evenly to each inverter cell in a cyclical fashion. To carry out, in practice, the SMC n x m modulation technique, the implementation of the modulation control strategy has been done in a field-programmable gate array circuit XC4010E+ of XILINX to control a three-phase SMC 3 x 2 seven-level inverter, and the experimental results are carried out to confirm the high performance of this inverter. [ABSTRACT FROM AUTHOR]

This paper proposes a multilevel inverter configuration which produces a hexagonal voltage space vector structure in the lower modulation region and a 12-sided polygonal space vector structure in the overmodulation region. A conventional multilevel inverter produces 6n ± 1 (n = odd) harmonics in the phase voltage during overmodulation and in the extreme square-wave mode of operation. However, this inverter produces a 12-sided polygonal space vector location, leading to the elimination of 6n ± 1 (n = odd) harmonics in the overmodulation region extending to a final 12-step mode of operation with a smooth transition. the benefits of this arrangement are lower losses and reduced torque pulsation in an induction motor drive fed from this converter at higher modulation indexes. The inverter is fabricated by using three conventional cascaded two-level inverters with asymmetric dc-bus voltages. A comparative simulation study of the harmonic distortion in the phase voltage and associated losses in conventional multilevel inverters and that of the proposed inverter is presented in this paper. Experimental validation on a prototype shows that the proposed converter is suitable for high-power applications because of low harmonic distortion and low losses. [ABSTRACT FROM AUTHOR]

This paper deals with the analysis of the input dc-link voltage ripple in multilevel inverter based on H-bridge and level doubling network (LDN). The LDN is basically a half-bridge fed by a floating capacitor, with voltage self-balancing capability, recalling the concept of a flying capacitor configuration. The amplitude of the LDN voltage ripple is analytically determined considering both the low-order and the switching harmonic components. In particular, peak-to-peak distributions of voltage ripples over the fundamental period are analytically determined, making possible the design of dc-link capacitor relying only on the dc-voltage ripple requirements. The case study makes reference to negligible switching ripple in the output current. It well represents either grid connection or passive load having almost sinusoidal currents. Numerical simulations carried out by MATLAB/Simulink and a complete set of experimental verifications are given to confirm the theoretical developments. [ABSTRACT FROM AUTHOR]

This paper proposes a new modulation strategy for multilevel inverters, which selects voltage vectors that generate zero common-mode voltage in the load, working at low switching frequency. Experimental results confirm that the method is highly effective and simple to implement in a modern microprocessor. The voltage distortion (total harmonic distortion), the number of commutations, and the linearity are also studied. Finally, it is concluded that the proposed strategy is highly suited for inverters with a high number of levels. [ABSTRACT FROM AUTHOR]

For cascaded multilevel inverter topologies with a single dc supply, closed-loop capacitor voltage control is necessary for proper operation. This paper presents zero and reduced common-mode voltage (CMV) operation of a hybrid cascaded multilevel inverter with predictive capacitor voltage control. Each phase of the inverter is realized by cascading two- three-level flying capacitor inverters with a half-bridge module in between. For the presented inverter topology, there are redundant switching states for each inverter voltage levels. By using these switching state redundancies, for every sampling instant, a cost function is evaluated based on the predicted capacitor voltages for each phase. The switching state that minimizes cost function is treated as the best and is switched for that sampling instant. The inverter operates with zero CMV for a modulation index upto 86%. For modulation indices from 86% to 96%, the inverter can operate with reduced CMV magnitude (Vdc/18) and reduced CMV switching frequency using the new space-vector pulsewidth modulation (SVPWM) presented herein. As a result, the linear modulation range is increased to 96% as compared to 86% for zero CMV operation. Simulation and experimental results are presented for the inverter topology for various steady state and transient operating conditions by running an induction motor drive with open loop $V/f$ control scheme. [ABSTRACT FROM PUBLISHER]

The flying capacitor multilevel inverter (FCMLI) is one of the well-known structures of multilevel inverters having attracted considerable attention because of its merits. In spite of its many advantages, it has some limitations such as high volume and complicated control method because of its bulky capacitors and their voltage balancing requirement. Moreover, the high number of power semiconductors required makes this structure susceptible to failure. To increase the ratio of the number of levels to the number of components, an uneven distribution of capacitor voltages has been suggested in previous reports; however, this approach complicates the control method. Up to now, almost all presented methods suffer from high computational load and/or structure-dependent algorithm. In this paper, a simple state-based and structure-independent method is proposed for capacitor voltage regulation. The proposed method is straightforward and can perform online computation of switching sequences in a computationally efficient manner without any need for stored information or look-up tables. The method is conveniently extendible to any number of cells and levels in an FCMLI structure with arbitrary dc link voltage distribution schemes. Simulation and experimental results show the effectiveness and simplicity of this method. [ABSTRACT FROM PUBLISHER]

This paper presents a new reconfiguration module for asymmetrical multilevel inverters in which the capacitors are used as the dc links to create the levels for staircase waveforms. This configuration of the multilevel converter makes a reduction in dc sources. On the other hand, it is possible to generate 13 levels with lower dc sources. The proposed module of the multilevel inverter generates 13 levels with two unequal dc sources (2VDC and 1VDC). It also involves two chargeable capacitors and 14 semiconductor switches. The capacitors are self-charging without any extra circuit. The lower number of components makes it desirable to be used in wide range of applications. The module is schematized as two back-to-back T-type inverters and some other switches around it. Also, it can be connected as a cascade modular which leads to a modular topology with more voltage levels at higher voltages. The proposed module makes the inherent creation of the negative voltage levels without any additional circuit (such as H-bridge circuit). Nearest level control switching modulation scheme is applied to achieve high-quality sinusoidal output voltage. Simulations are executed in MATLAB/Simulink and a prototype is implemented in the power electronics laboratory in which the simulation and experimental results show a good performance. [ABSTRACT FROM AUTHOR]

Analytical closed-form expressions for harmonic distortion factors corresponding to various pulsewidth modulation (PWM) techniques for a two-level inverter have been reported in the literature. This paper derives such analytical closed-form expressions, pertaining to centered space-vector PWM (CSVPWM) and eight different advanced bus-clamping PWM (ABCPWM) schemes, for a three-level neutral-point-clamped (NPC) inverter. These ABCPWM schemes switch each phase at twice the nominal switching frequency in certain intervals of the line cycle while clamping each phase to one of the dc terminals over certain other intervals. The harmonic spectra of the output voltages, corresponding to the eight ABCPWM schemes, are studied and compared experimentally with that of CSVPWM over the entire modulation range. The measured values of weighted total harmonic distortion (WTHD) of the line voltage \bf V\bf WTHD are used to validate the analytical closed-form expressions derived. The analytical expressions, pertaining to two of the ABCPWM methods, are also validated by measuring the total harmonic distortion (THD) in the line current \bf I\bf THD on a 2.2-kW constant volts-per-hertz induction motor drive. [ABSTRACT FROM PUBLISHER]

This paper presents the design and implementation of a simple neutral point potential (NPP) regulator for a three-level diode-clamped inverter employing a sine-triangle regulator in conjunction with a closed-loop controller with reduced switching losses. The regulator principle is based on adding a continuous variable offset voltage which regulates the midpoint potential of the dc bus. The novelty of the proposed NPP regulator is in the determination of the magnitude of variable offset voltage based upon the average value, peak-to-peak amplitude, total harmonic distortions, and third harmonic content in NPP. Aside from maintaining dc-bus voltage balance, the proposed regulator leads to a significant reduction in the voltage distortion at the NP, resulting in the reduction of the required dc-bus capacitance. It also reduces the switching losses of the inverter by inserting the “no-switching” zone within each half cycle of the fundamental voltage wave. Analytical, computer simulation, and experimental results verifying the approach are presented in this paper for various load power factor angles. [ABSTRACT FROM AUTHOR]

Microinverters operating into the single-phase grid from new energy source with low-voltage output face the challenges of efficiency bottleneck and twice-line-frequency variation. This paper proposed a multilevel inverter based on bridge modular switched-capacitor (BMSC) circuits with its superiority in conversion efficiency and power density. The topology is composed of dc–dc and dc–ac stages with independent control for each stage, aiming to improve system stability and simplify the control method. The BMSC dc–dc stage, which can be expanded to synthesize more levels, not only features multilevel voltage gain but also partially replaces the original bulk input capacitor and functions as an active energy buffer to enhance power-decoupling ability between dc and ac sides. In dc–ac stage, the control strategy of optimized unipolar frequency doubling sine-wave pulse width modulation is proposed to improve the quality of output waveform. Meanwhile, the multilevel voltage phase has been optimized to further reduce the power loss. Finally, a prototype has been built and tested. Associated with the simulation, the experimental results validate the practicability of these analyses. [ABSTRACT FROM PUBLISHER]

Compared with multilevel space vector modulation, level-shifted multicarrier sinusoidal pulsewidth modulation (SPWM) for nested neutral point-clamped (NNPC) inverters requires much less calculations and implementation efforts, but the existing conventional SPWM cannot suppress the severe flying-capacitor (FC) voltage ripples under low output-frequency conditions. In order to solve this problem, a multicarrier-based PWM strategy with complete voltage balance control (VBC) capacity is proposed in this paper. For NNPC inverters operating under low output-frequency conditions, two preprocessing steps, the zero-sequence injection and the modulation-signal rearrangement, are proposed before the comparisons between level-shifted carriers and modulating signals. These preprocessing steps make the average currents flowing through FCs zero, which is beneficial to greatly reduce the FC voltage ripples under low output-frequency conditions. Together with additional VBC, the proposed modulation can assure the FC voltages balanced under the entire output-frequency conditions. Principles and implementation processes of proposed modulation techniques and VBC methodsare elaborated in detail and compared with conventional modulation methods. Both simulation results from a 5-MVA system and experimental results based on a 5-kVA platform are presented to verify the effectiveness. [ABSTRACT FROM AUTHOR]

This paper presents a three-phase cascaded multilevel inverter that uses five-level transistor-clamped H-bridge power cells. Multicarrier phase-shifted pulse-width modulation method is used to achieve balanced power distribution among the power cells. A new method to balance the midpoint capacitor voltage in each cell is developed and tested. The analysis of the output voltage harmonics and the total power losses covering the conduction and the switching power losses are carried out and compared with the cascaded neutral-point-clamped and the conventional cascaded H-bridge inverters. For verifications, the proposed inverter is experimentally tested on an induction motor. From the results, the proposed inverter provides higher output quality with relatively lower power loss as compared to the other conventional inverters with the same output quality. [ABSTRACT FROM PUBLISHER]

A generalized space-vector-based spread spectrum modulation scheme for multilevel inverters is proposed in this paper. The proposed scheme uses the principle of sigma–delta modulation as applied to analog-to-digital converters (ADCs), based on the view that a multilevel converter could be interpreted as an oversampling ADC. The principle of vector quantization is utilized for quantizing the instantaneous reference voltage space vector in the proposed space-vector-based sigma–delta converter. The switching vectors of the inverter are naturally selected without sector identification, ensuring optimum switching sequence under all conditions including the overmodulation region. As the sigma–delta converter results in a randomly varying switching frequency, the proposed scheme has spread spectrum characteristics. To avoid fractional arithmetic, a 60 ^\circ coordinate system is used to represent the space vector in this paper. The proposed scheme can be used for any general n-level inverter, and experimental results are presented for four-, five-, and six-level inverters, driving a 2-hp three-phase induction motor in an open-end winding configuration. The experimental results of the proposed scheme are compared with the space-vector pulsewidth modulation (PWM) scheme and random PWM scheme. [ABSTRACT FROM PUBLISHER]

Multilevel inverters have been widely accepted for high-power high-voltage applications. Their performance is highly superior to that of conventional two-level inverters due to reduced harmonic distortion, lower electromagnetic interference, and higher dc link voltages. However, it has some disadvantages such as increased number of components, complex pulsewidth modulation control method, and voltage-balancing problem. In this paper, a new topology with a reversing-voltage component is proposed to improve the multilevel performance by compensating the disadvantages mentioned. This topology requires fewer components compared to existing inverters (particularly in higher levels) and requires fewer carrier signals and gate drives. Therefore, the overall cost and complexity are greatly reduced particularly for higher output voltage levels. Finally, a prototype of the seven-level proposed topology is built and tested to show the performance of the inverter by experimental results. [ABSTRACT FROM PUBLISHER]

With regard to a five-level inverter comprising flying-capacitor asymmetric H-bridge, the impact on the capacitor voltage under conventional modulation approach is analyzed. Since it is sensitive to the fundamental period and the load current, it may introduce undesired low-order harmonics into the output voltage and may even break down the power switches due to the considerable fluctuation of the flying-capacitor voltage. Thus, this paper proposes a novel pulsewidth-modulation scheme with the positive and negative cross carriers, which controls the flying-capacitor voltage by utilizing the redundant switching states of the output voltages. Three modes of precharging the flying capacitor without extra equipments are presented. Moreover, the capacitance of the flying capacitor and the switching frequency of the power switches can be chosen according to the allowable fluctuation of the flying-capacitor voltage and the load current. In order to remove the overlapping of the level layers, the optimization of the line-to-line voltage waveform is proposed to synthesize the reference vector with the “nearest three-vector” approach. The theory is supported by the experimental results from the prototype. [ABSTRACT FROM AUTHOR]

In this paper, the elimination of harmonics in a cascade multilevel inverter by considering the nonequality of separated dc sources by using particle swarm optimization is presented. Solving a nonlinear transcendental equation set describing the harmonic-elimination problem with nonequal dc sources reaches the limitation of contemporary computer algebra software tools using the resultant method. The proposed approach in this paper can be applied to solve the problem in a simpler manner, even when the number of switching angles is increased and the determination of these angles using the resultant theory approach is not possible. Theoretical results are verified by experiments and simulations for an 11-level H-bridge inverter. Results show that the proposed method does effectively eliminate a great number of specific harmonics, and the output voltage is resulted in low total harmonic distortion. [ABSTRACT FROM PUBLISHER]

Half-cycle symmetry selective-harmonic-elimination pulsewidth-modulation (SHE-PWM) problems may have a large number of valid solutions, which are beneficial to the optimization design. This paper proposes a novel generalized formulation of half-cycle symmetry SHE-PWM problems for multilevel inverters. The advantages of the proposed formulation include simplicity in format, flexibility in PWMwaveforms, and a broad solution space. A method to obtain initial values for the SHE-PWM equations according to the reference modulation index M and the initial phase angle of output fundamental voltage is proposed and investigated thoroughly. Take a five-level inverter with M = 0.75 as an example; six sets of solutions for two typical initial phase angles of 0°? and 90°? are presented. Simulations and experiments are carried out. It is demonstrated that the experimental results agree well with simulated ones, which proves the validity and practicability of the new method proposed. [ABSTRACT FROM AUTHOR]

This paper presents new five-level current-source inverters (CSIs) with voltage/current buck-boost capability, unlike existing five-level CSIs where only voltage-boost operation is supported. The proposed inverters attain self-inductive-current-balancing per switching cycle at their dc front ends without having to include additional balancing hardware or complex control manipulation. The inverters can conveniently be controlled by using the well-established phase-shifted carrier modulation scheme with only two additional linear references and a mapping logic table needed. Existing modulators can therefore be conveniently retrofitted for controlling the presented inverters. By appropriately coordinating the inverter gating signals, their implementations can be realized by using the least number of components without degrading performance. These enhanced features of the inverters have already been verified in simulation and experimentally using a scaled-down laboratory platform. [ABSTRACT FROM AUTHOR]

In this paper, an approach to reduce common-mode voltage (CMV) at the output of multilevel inverter using 3-D space-vector modulation (SVM) is proposed. The 3-D SVM is superset of the traditional 2-D SVM, and thus, it inherits all the merits of traditional 2-D. A simple technique for the selection of switching states to constitute the reference vector is proposed here. The computational cost of the proposed technique is independent of voltage levels of inverter. This technique is easy to implement online in digital controller. The tradeoff between quality of output voltage and CMV is achieved in this paper. This paper realizes the implementation of 3-D SVM to reduce the CMV using a five-level diode-clamped inverter for a three-phase induction motor. Experimental and simulation results demonstrate the feasibility of the proposed technique. [ABSTRACT FROM AUTHOR]

This paper presents a single-phase multistring five-level photovoltaic (PV) inverter topology for grid-connected PV systems with a novel pulsewidth-modulated (PWM) control scheme. Three PV strings are cascaded together in parallel configuration and connected to a five-level inverter to produce output voltage in five levels: zero, +1/2Vdc, Vdc, - 1/2Vdc, and -Vdc. Two reference signals that were identical to each other with an offset that was equivalent to the amplitude of the triangular carrier signal were used to generate PWM signals for the switches. DSP TMS320F2812 is used to implement this PWM switching scheme together with a digital proportional-integral current control algorithm. The inverter offers much less total harmonic distortion and can operate at near-unity power factor. The validity of the proposed inverter is verified through simulation and implemented in a prototype. The experimental results are compared with a conventional single-phase multistring three-level grid-connected PWM inverter. [ABSTRACT FROM AUTHOR]

This paper presents a fundamental-frequency-modulated diode-clamped multilevel inverter (DCMLI) scheme for a three-phase stand-alone photovoltaic (PV) system. The system consists of five series-connected PV modules, a six-level DCMLI generating fundamental-modulation staircase three-phase output voltages, and a three-phase induction motor as the load. In order to validate the proposed concept, simulation studies and experimental measurements using a small-scale laboratory prototype are also presented. The results show the feasibility of the fundamental frequency switching application in three-phase stand-alone PV power systems. [ABSTRACT FROM AUTHOR]

The paper presents a five-level inverter scheme with reduced power circuit complexity for an induction motor drive. The scheme is realized by cascading conventional two-level and three-level neutral point clamped inverters in conjunction with an open-end winding three-phase induction motor drive. An inverter control scheme with common-mode voltage (CMV) elimination, along with a simple dc link voltage control, is developed by using only switching states with zero CMV for the entire modulation range. Theoretical considerations are experimentally verified for a variety of operating conditions. [ABSTRACT FROM AUTHOR]

The concept of hybrid clamped is proposed in multilevel-inverter topologies, and a hybrid-clamped multilevel-inverter topology comprising active and passive clamping devices is presented in this paper. In this topology, the dc-link capacitor voltages can be balanced without additional circuitry or separated dc voltage sources, regardless of load characteristics. It can be used in real and reactive power conversion applications. The topology structure, operating principle, and self-voltage balancing ability are analyzed. In addition, the validity is confirmed by simulations and experiments based on a five-level inverter. Finally, the functions of different clamping devices are compared. [ABSTRACT FROM AUTHOR]

Multilevel diode-clamped converters with more than three levels cannot maintain voltage balance in the dc-link capacitors for some operating conditions due to the existence of dc currents in the middle points. Since capacitors are either completely charged or discharged for those conditions, this circumstance severely limits practical application of these converters. The limit explored in this paper is that the four-level converter cannot achieve voltage balance. Proper redundant vectors are selected in the space-vector diagram so that a quadratic parameter related to the currents in the middle points is minimized. [ABSTRACT FROM AUTHOR]

In this paper, a new cascade switch-ladder multilevel inverter topology is presented which can generate a large number of output voltage levels. First, a fundamental switch-ladder multilevel inverter structure is described. Then, the structure of recommended cascade topology based on series connection of fundamental switch-ladder topologies is presented. To generate maximum number of levels with minimum number of switching elements, dc sources, and voltage on switches, the proposed cascade topology is optimized. Comparison results prove that the presented cascade topology requires fewer numbers of components. Also, the value of voltage rating on switches is less than other structures. Experimental results for two topologies are analyzed to verify the performance of the proposed topology. [ABSTRACT FROM PUBLISHER]

This paper presents a nine-level inverter topology for an open-end induction motor drive requiring only eight switches per phase, using two three-level inverters with two isolated dc links in a 3:1 ratio. A space-vector-based formulation is used to determine pole voltages such that both inverters supply power to the load over the full modulation range, eliminating the possibility of dc bus overcharging. Proper selection of switching states ensures that all floating capacitor voltages are kept tightly balanced. A digital state machine is used to select sequences of switching states in order to eliminate deadtime-induced pole voltage transients, further improving the output-voltage quality. A level-shifted carrier-based pulse width modulation scheme is used. The steady-state and transient performance of this topology were verified and the experimental results are included. [ABSTRACT FROM AUTHOR]

A novel flying-capacitor-clamped five-level inverter based on bridge modular switched-capacitor topology is proposed in this paper. The inverter features the switched-capacitor circuit with dc–dc boosting conversion ability and the multilevel inverter circuit with flying-capacitor-clamped performance. With the special composite structure, the number of components is cut down compared to the topology of the conventional cascaded multilevel inverter. Meanwhile, part of switches can be operated under line voltage frequency, resulting in switching loss reduction. Hence, the potential of system efficiency and power density is released due to embed switched-capacitor circuit. More importantly, the optimized carrier-based phase disposition pulse width modulation method is employed as a control strategy. Under this control strategy, the capacitor voltage self-balance can be realized and quality of output waveforms can be improved significantly. After simulation, the prototype is built to validate the correctness and practicability of the analysis. [ABSTRACT FROM AUTHOR]

This paper presents a closed-loop space vector modulation (SVM)-based sliding mode controller (SMC) for a three-level grid-connected neutral point clamped (3L-NPC) inverter. The nonlinear SMC based on Gao's reaching law has been designed to control the grid current and inject desired amount of active and reactive power into the network. Due to using single dc source at the NPC inverter dc bus, neutral point voltage is controlled through redundant switching states and instantaneous dc voltage feedback integrated into SVM technique. Meanwhile, there is no external voltage controller involved, thus no associated fine tuning issues are existed. The performance of the proposed hybrid controller to inject a desired active/reactive power to the grid is investigated through external perturbations such as change in the line current amplitude/phase shift, ac voltage fluctuation, as well as dc voltage variation. Full converter state-space model was developed and simulated. Experimental results are provided to verify the fast dynamic performance, low content of line current THD%, and good voltage balancing of dc bus capacitors of the NPC inverter. [ABSTRACT FROM AUTHOR]

In this paper, a novel topology of six-level inverters for a medium-voltage high-power applications is proposed, which consists of inner flying-capacitor inverter (FCI) units and outer two-level inverter units. The proposed topology can reduce the number of devices, components, and isolated sources compared with the existing ones in the case of the same number of output voltage steps, which result in a reduction of the size and weight of the inverters. Also, the total power loss of the proposed topology is lower than that of the diode-clamped inverter (DCI) and FCI. Besides, the estimated cost of the proposed topology is about 60.5% and 81.3% compared with the DCI and FCI, respectively. In addition, the modulation technique and the control strategy for the dc-link capacitor and flying-capacitor voltages are developed for the proposed topology. The effectiveness of the proposed six-level inverter for the medium-voltage applications has been verified by simulation results. Also, the feasibility of the proposed inverter has been proved by experimental results for the prototype at the laboratory. [ABSTRACT FROM AUTHOR]

In this paper, a model-predictive control (MPC) has been designed and implemented on the packed U-cell (PUC) inverter, which has one isolated dc source and one capacitor as an auxiliary dc link. The MPC is designed to regulate the capacitor voltage at the desired magnitude to have seven voltage levels at the output of the inverter. Since grid-connected application is targeted by this application, the inverter should be capable of supplying requested amount of active and reactive power at the point of common coupling (PCC) as well. Therefore, MPC should also consider the line-current control to monitor the exchange of reactive power with the grid while injecting appropriate active power at low total harmonic distortion (THD). Various experimental tests including change in dc-source voltage, active power variation, and operation at different power factor (PF) have been performed on a laboratory prototype to validate the good performance obtained by the proposed MPC. The dynamic performance of the controller during sudden changes in dc capacitor voltage, supply current, and PF demonstrates the fast and accurate response and the superior operation of the proposed controller. [ABSTRACT FROM PUBLISHER]

In this paper, a current error space vector (CESV)-based hysteresis current controller for a multilevel 12-sided voltage space vector-based inverter-fed induction motor (IM) drive is proposed. The proposed controller gives a nearly constant switching frequency operation throughout different speeds in the linear modulation region. It achieves the elimination of 6n \pm 1, n = odd harmonics from the phase voltages and currents in the entire modulation range, with an increase in the linear modulation range. It also exhibits fast dynamic behavior under different transient conditions and has a simple controller implementation. Nearly constant switching frequency is obtained by matching the steady-state CESV boundaries of the proposed controller with that of a constant switching frequency SVPWM-based drive. In the proposed controller, the CESV reference boundaries are computed online, using the switching dwell time and voltage error vector of each applied vector. These quantities are calculated from estimated sampled reference phase voltages. Vector change is decided by projecting the actual current error along the computed hysteresis space vector boundary of the presently applied vector. The estimated reference phase voltages are found from the stator current error ripple and the parameters of the IM. [ABSTRACT FROM PUBLISHER]

This paper considers achieving the minimum total harmonic distortion (THD) or frequency-weighted THD (WTHD) of the staircase-modulated output voltage of single-phase multilevel inverters, with or without elimination of the lowest order harmonics. The minimal THD values, together with the corresponding step angles and dc voltage source ratios, have been obtained for the 5-, 7-, 9-, 11-, and 13-level cases; accounting for the device voltage drops when the load is resistive or is moderately inductive is described. Similarly, the minimal WTHD values, together with the corresponding step angles and dc source voltage ratios, have been obtained for the five-, seven-, and nine-level waveform cases. The results show that requiring harmonic elimination leads to larger W/THD than the minimum W/THD that can be achieved without this requirement. Furthermore, a 13-level waveform is needed to attain a voltage THD less than 5%, and a nine-level waveform is needed to attain a WTHD less than 0.5%. Experimental measurements are presented as verification of the analytical results. [ABSTRACT FROM PUBLISHER]

A neutral-point-clamped three-level inverter with small dc-link capacitors is presented in this paper. The inverter requires zero average neutral-point current for stable neutral-point voltage. The small dc-link capacitors may not maintain capacitor voltage balance, even with zero neutral-point current. This may happen due to nonlinearities present in the circuit. This requires a fast control of the neutral-point voltage. A simple carrier-based modulation strategy which allows modeling of the neutral-point voltage dynamics as a continuous function of power drawn from the inverter is proposed. This continuous model shows that the neutral-point current is proportional to the power drawn from the inverter, and it enables the use of a well-established classical control theory for the neutral-point voltage controller design. A simple proportional integral controller is designed for the neutral-point voltage control on the basis of the continuous model. The design method for optimum performance is discussed. The implementation of the proposed modulation strategy and the controller is very simple. The controller is implemented in a 7.5-kW induction machine-based drive with only 14 \mu \F dc-link capacitors. Also, the experimental results show that fast and stable performance of the neutral-point voltage controller are achieved and thus verify the validity of the proposed control approach. [ABSTRACT FROM PUBLISHER]