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A normally-off SiC-JFET/GaN-HEMT cascode device is recently proposed, featuring a cascode configuration that incorporates a high-voltage (HV, e.g., 1200 V) silicon-carbide (SiC) junction field effect transistor (JFET) delivering the HV blocking capability and a low-voltage (LV) enhanced-mode (E-mode) gallium-nitride (GaN) high electron mobility transistor (HEMT) providing the normally-off gate control. This all-wide-bandgap device exhibits superior thermal stability and high switching speed compared to its counterparts, e.g., the SiC/Si cascode device. In this article, we study short-circuit (SC) characteristics of a 1200-V/80-mΩ SiC/GaN cascode device by considering the interactions between the SiC and GaN devices. The single-event SC withstand time (SCWT) of the demonstrated SiC/GaN cascode device is tested to be ∼3 μs under a dc-bus voltage (Vdc) of 600 V when the turn-on gate voltage (VG-on) is set to 5 V. The SC failure occurs due to the formation of hot spots induced by thermal-runaway leakage currents inside the SiC JFET. The SCWT of the cascode device could be improved by applying a moderate VG-on (e.g., SCWT = ∼6.5 μs at VG-on = 3.5 V under v dc = 600 V) without affecting the on-state resistance (r on). However, it is identified that current oscillations tend to be triggered during the SC period when VG-on is too low (e.g., lower than 3 V). The oscillation behavior is attributed to the energy stored in the interconnection parts between the SiC and GaN devices. The harmful oscillations could be suppressed by applying higher VG-on, which drives the SiC JFET into low-transconductance mode by modulating the drain-to-source voltage (VDS-G) of the LV GaN HEMT. [ABSTRACT FROM AUTHOR]

A 650-V/84-mΩ normally-off GaN/SiC cascode device is demonstrated with systematic static and dynamic characterizations. The cascode device features a low-voltage enhancement-mode (E-mode) gallium nitride (GaN) high electron mobility transistor (HEMT) to enable normally-off gate control, and a 650-V normally-on silicon carbide (SiC) JFET provides the high-voltage blocking capability. The GaN/SiC cascode device exhibits many application-desired behaviors, including reverse conduction capability, avalanche breakdown capability, thermally stable threshold voltage, low input/output capacitances, no dynamic RON degradation, and negligible dynamic VTH shift. In addition, a customized double-pulse test board is built to evaluate the switching performance of this cascode device and other 650-V SiC-based power devices. This cascode device adopting low-voltage GaN HEMT has low QG×RON and exhibits excellent switching performance. The switching losses (EON and EOFF) are much smaller than that of the 650-V Si/SiC cascode device and comparable to that of the state-of-the-art 650-V SiC MOSFETs. [ABSTRACT FROM AUTHOR]

Although the gallium nitride (GaN) high-electron-mobility transistor/silicon carbide (SiC) junction field-effect transistor (JFET) cascode device exhibits certain performance advantages over the SiC metal–oxide–semiconductor field-effect transistor (MOSFET), its robustness in harsh operating conditions is unknown. In this work, the short-circuit (SC) robustness of 650-V GaN/SiC cascode devices is characterized, analyzed, and compared with that of several mainstream SiC MOSFETs. GaN/SiC cascode devices exhibit competitive SC capability. Different failure modes are observed: thermal runaway in the SiC JFET of the cascode device and gate-to-source breakdown in the SiC MOSFET. The difference is associated with the configuration of the dielectric above SiC in the JFET and the source pad layout. According to the waveforms in SC events, failure spots, and thermal simulation results, a thermal runaway in the SiC JFET is attributed to the positive feedback between the drain leakage current and the junction temperature in the local area (hotspot) without the source pad on the top. The SC withstand time of the cascode device can be extended by reduction of the active area without the source pad. [ABSTRACT FROM AUTHOR]

Short circuit (SC) capability of 650-V Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) under single and repetitive tests is characterized in this article. The investigated devices exhibit strong capability under a single SC test, but weak capability under repetitive SC tests with a bus voltage of 400 V and a gate drive voltage of 6 V. The failure mechanism under repetitive SC tests is revealed through electrothermal simulation and microscale failure spot analysis. Thermal fatigue cracks are formed due to the high temperature spike and local temperature fluctuations in the narrow GaN channel and buffer layers, leading to weak repetitive SC capability. The unique heat confinement effect in the GaN layer plays an important role in the formation of high temperature spike and fatigue cracks. The withstand time in a single SC test is several hundred microseconds due to fast drain current drop that results from high temperature and, to a lesser degree, the dynamic threshold voltage shift during the SC transient. The device failure in a single-event SC test is related to heat diffusion to a wider region. Some guidelines are proposed for handling and improving the repetitive SC capability. [ABSTRACT FROM AUTHOR]

Systematic characterizations of a cascode device with a low-voltage enhance-mode (E-mode) p-GaN gate high-electron mobility transistor as the control device and a high-voltage (HV) depletion-mode (D-mode) silicon carbide junction field effect transistor (JFET) as the voltage blocking device are presented in this article. The demonstrated device with a breakdown voltage rating of 1200 V and a static on-resistance (RON) of 100 mΩ features small device capacitances with fast switching speed, avalanche breakdown capability, thermally stable threshold voltage (VTH), and no dynamic RON degradation. To identify its safe operation in the off-state with a high drain bias, the off-state middle point voltage (VM) between the E-mode device drain and D-mode device source is investigated. A relatively low off-state VM is achieved under both static and dynamic modes. In addition to the device-level characterization, a custom-designed double-pulse test circuit is built to evaluate the transient switching performance of the cascode device. Optimal gate drive conditions are proposed to 1) overcome the drain bias induced positive dynamic VTH shift; and 2) suppress the increased dynamic off-state leakage current (IOFF) induced by on-state hole injection. Under 800 V/16 A testing conditions, high switching speed with the drain voltage peak slew rates of 72 V/ns during turn-on and 121 V/ns during turn-off is achieved. [ABSTRACT FROM AUTHOR]