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Wide bandgap semiconductors show superior material properties enabling silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) present good features on its switching speed and withstand voltage. However, the high voltage and fast switching characteristics of SiC MOSFETs also put forward new requirements for voltage measurement, that is, high bandwidth under high voltage conditions. This article proposes a new voltage divider structure and a proactive parameter design compensation network to build high voltage and high bandwidth voltage sensing circuit. This structure utilizes the characteristics that the same resistor has the same parasitic capacitance to meet the high frequency constraints of the voltage sensing circuit. The influence of parasitic parameters and load parameters on circuit performance is analyzed in detail, which provides a basis for the compensation network design. By combining the proposed voltage sensing circuit with an appropriate proactive parameter design load effect compensation network (PDCN), the withstand voltage rating of the low-voltage and high-bandwidth voltage probes can be extended to required levels. Different from other existing methods, PDCN can actively design the compensation circuit parameters and provide the optimal parameters of the compensation circuit. This lead to a smaller input capacitance than the state of the art commercial voltage probes, which will help to obtain better performance when measuring high-speed switching voltage. The performance of the voltage measurement is experimentally verified and compared by SiC-based double pulse test (DPT) circuits. [ABSTRACT FROM AUTHOR]

The silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) has a more serious voltage overshoot than the silicon insulated gate bipolar transistor (IGBT) due to the fundamental differences of the devices’ parasitic parameters. In this paper, a novel low-inductance packaging structure for a wire-bond-based multichip phase-leg SiC MOSFET module to suppress the voltage overshoot is proposed. This packaging structure is based on the adjacent decoupling concept achieved by several decoupling capacitors to reduce the size of the commutation loop. The improvement in the packaging parasitics has been verified through an Ansys Q3D extractor. Furthermore, the influence of adjacent decoupling capacitors is analyzed in detail by frequency-domain analysis and verified with LTspice simulation analysis. Thereafter, the selection and thermal reliability of adjacent decoupling capacitors are expounded. The experimental results demonstrate the effectiveness and superiority of the proposed packaging structure. [ABSTRACT FROM PUBLISHER]

This paper presents a novel compact circuit combining function of gate control and voltage balancing for series-connected silicon carbide (SiC) metal–oxide–semiconductor field-effect transistor (MOSFET). Two series-connected SiC MOSFETs with the proposed circuit only require a single standard gate driver to achieve the gate control and voltage balancing during both steady-state and switching transition. Moreover, the proposed circuit is only composed of ten passive components. Therefore, the proposed circuit provides a low-cost and highly reliable method to increase the blocking voltage of the SiC MOSFET. The operation principles of the proposed circuit are theoretically analyzed. In addition, the high-blocking-voltage device is not only required in switching-mode power supply (SMPS) but also in dc-breaker applications. The proposed circuit is then modified to make it suitable to the dc-breaker applications. The simulation and experimental results validate the effectiveness and superiority of the proposed circuit in both SMPS and dc-breaker applications. [ABSTRACT FROM PUBLISHER]