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In this work, a multilevel 42-sided polygonal space vector structure for suppression of lower order harmonics for open-end induction motor (OEIM) drive applications is proposed. The proposed power circuit topology consists of two inverters feeding an OEIM from either side. The main inverter fed with a single dc-link providing active power for motoring operation is switched at low switching frequency. The secondary inverter fed with a capacitive supply is switched at high frequency to suppress lower order harmonics upto 39th order, up to the base speed of operation allowing maximum utilization of the dc-link. The advantages of lower order harmonic suppression in motor phase voltage, for polygonal space vector structures, are combined with multilevel inverter topology. This offers various advantages like multilevel operation with low inverter switching for the main power delivery inverter and harmonic suppression throughout the modulation range. The low switching frequency primary inverter generates harmonics of the order $6*k \pm 1$ , where $k = 1, 2, 3,{\ldots }$. The harmonics are suppressed by the capacitor-fed secondary inverter, which supplies only reactive power for suppression of lower order harmonics in motor phase voltage. Use of a single dc-link facilitates four-quadrant operation of the inverter. The proposed scheme is validated for steady-state and dynamic performance by experimental results. [ABSTRACT FROM AUTHOR]

This article proposes an inverter topology for the first time for suppression of all lower order harmonics (5th, 7th, 11th, 13th, etc.) up to 39th harmonic. The lower order harmonic suppression is achieved by switching the 42-sided polygonal vectors, which eliminates harmonics in phase voltage without using a passive LC filtering technique. The power circuit topology uses a single dc-link supply for the primary inverter. The secondary inverter is fed with a capacitive supply. A novel topology is proposed for the dense six-level secondary inverter. The lower order harmonics in phase voltage are suppressed using the secondary inverter, which acts like a switched-capacitive filter. This article also proposes a novel capacitor voltage-balancing scheme for the first time, which achieves voltage balancing for secondary inverter capacitors. The voltages of secondary inverter capacitors are balanced using the power balance relationship between the primary inverter and the motor load. An experimental study of the topology and the capacitor-balancing scheme is presented for the validation of proposed scheme. [ABSTRACT FROM AUTHOR]

Multilevel cascaded H-bridge (CHB) converters are an attractive solution for multiple applications like flexible ac transmission systems and solid-state smart transformers, among others. This article is focused on a CHB working with unbalanced conditions per cell (different cell dc voltages and/or cell voltage references). In this scenario, the phase-shifted pulsewidth modulation (PS-PWM) technique produces a harmonic distortion around twice the carrier frequency and its multiples in the CHB output voltage. In this article, a generalized variable-angle PS-PWM method is presented in order to mitigate this drawback improving the CHB output voltage harmonic spectrum. The proposed method is based on applying a mathematical search algorithm to determine the phase displacement angles to be applied to the PS-PWM technique. Experimental results show how this objective is achieved without introducing any disadvantage in the CHB operation. The method can be applied to CHB with any number of cells. [ABSTRACT FROM AUTHOR]

In this article, a model predictive control (MPC) strategy based on the optimal switching sequence (OSS) concept for a single-phase grid-connected H-bridge neutral-point-clamped (H-NPC) power converter is presented. The proposed OSS-MPC algorithm considers both the grid current tracking error and the dc-link capacitor voltage balance. Special emphasis is placed on the power converter control region in order to design suitable switching sequence candidates for this multiobjective control problem. Additionally, based on an analysis of the weighting factor effect over closed-loop performance, it is possible to demonstrate that this controller parameter is relatively easy to adjust. In fact, the weighting factor only affects the peak current during transients, with no effect over the steady-state performance. As a result, the proposed OSS-MPC provides a fast closed-loop dynamic to the H-NPC converter, which operates with a fixed switching frequency at all times. This predictive control strategy is experimentally validated in a 3.5-kVA laboratory setup. [ABSTRACT FROM AUTHOR]

This paper proposes a novel 49-level stacked inverter topology for drives. The 49 levels are achieved by stacking three 17-level inverters. Each of the 17-level inverter is developed by cascading a flying capacitor (FC) inverter with three capacitor-fed H-bridges. The device count can be reduced by making the FC and the three cascaded H-bridges common to the dc link in each phase using selector switches in between them. The selector switches need to operate at fundamental frequency only. Also, the devices need to block very low voltages. Hence, MOSFETs can be used. This topology requires three dc sources, each of V\text{dc} /6 only, which can be replaced with stacked batteries for electric vehicle applications. The reduction in the dc voltage requirement is achieved by using a normal symmetric six-phase induction motor with parallel connection of the opposite phase windings. All the floating capacitors in the topology can be balanced irrespective of any modulation index or load power factor. Due to the high number of voltage levels, nearest level control can be used instead of pulse width modulation, which reduces the switching losses. The $dv/dt$ during the inverter operation is also less. Detailed experimental results at different speeds of operation and during transients ensure that the novel topology can be a viable option for high-power adjustable speed drives. [ABSTRACT FROM PUBLISHER]

Multilevel cascaded H-bridge converters have become a mature technology for applications where high-power medium ac voltages are required. Normal operation of multilevel cascaded H-bridge converters assumes that all power cells have the same dc voltage, and each power cell generates the same voltage averaged over a sampling period using a conventional phase-shifted pulse width modulation (PWM) technique. However, this modulation method does not achieve good results under unbalanced operation per H-bridge in the power converter, which may happen in grid-connected applications such as photovoltaic or battery energy storage systems. In the paper, a simplified mathematical analysis of the phase-shifted PWM technique is presented. In addition, a modification of this conventional modulation method using variable shift angles between the power cells is introduced. This modification leads to the elimination of harmonic distortion of low-order harmonics due to the switching (triangular carrier frequency and its multiples) even under unbalanced operational conditions. The analysis is particularized for a three-cell cascaded H-bridge converter, and experimental results are presented to demonstrate the good performance of the proposed modulation method. [ABSTRACT FROM PUBLISHER]

In this paper, a model predictive control (MPC) based on optimal switching sequences (OSSs) for a single-phase grid-connected full-bridge neutral-point-clampled (NPC) power converter is presented. The predictive control algorithm is formulated in terms of OSSs, which was originally proposed to govern three-phase power converters. In this paper, the OSS concept is extended to control single-phase power converters. The proposed MPC algorithm belongs to the continuous control set MPC and is able to provide fixed switching frequency while handling system constraints. The proposed algorithm has been experimentally tested in an NPC power converter prototype. Experimental results show the desired fixed switching behavior in the steady-state condition and the intrinsic fast dynamic provided by MPC during transients. Furthermore, the test outcomes demonstrate the robustness of the proposed controller under large system parameter deviations. [ABSTRACT FROM AUTHOR]

Zero-common-mode-voltage (CMV) operation of multilevel inverters results in reduced dc-bus utilization and reduced linear modulation range. In this paper, a method to increase the linear modulation range for zero-CMV operation without increasing the dc-bus voltage using a cascaded multilevel inverter with a single dc supply is presented. Using this method, the peak fundamental output voltage can be increased from 0.499 to 0.637  \textV\text{dc} with zero CMV inside the linear modulation range. Also, various pulse width modulation (PWM) switching sequences are analyzed in this paper, and the PWM sequence that gives minimum current ripple is used for the zero-CMV operation of the inverter. The inverter topology with single dc supply is realized by cascading a two-level inverter with two floating-capacitor-fed full-bridge modules. Simulation and experimental results for steady-state and dynamic operating conditions are presented to validate the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a hybrid selective harmonic mitigation (SHM)-selective harmonic elimination (SHE) switching technique based on pulse-amplitude modulation (PAM) concept. It has been applied on a four-leg neutral-point-clamped (NPC) inverter to eliminate and mitigate more harmonic orders than recently proposed hybrid SHM-SHE-pulse width modulation (PWM) method while generating switching pulses at the same frequency. In conventional SHE and SHM techniques, equations are solved to attain the switching angles. Regarding the PAM, value of inverter dc voltage can be considered as an additional degree of freedom by which the flexibility of such techniques would be increased maintaining the switching frequency. In the proposed SHM-SHE-PAM, the conventional equations are reformulated to obtain constant switching angles for a vast range of modulation index (ma) applied on a four-leg NPC inverter. Switching pulses of the three-phase legs and the fourth leg are calculated to mitigate the nontriplen harmonics and eliminate the triplen ones, respectively. Due to the unique switching angles valid in the whole range for ma, the calculation time and volume (storage capacity) are significantly reduced leading to a simpler controller implementable on a low-risk and cheap AVR chip. Experimental tests’ results of a four-leg NPC inverter as UPS application prove the good dynamic performance and accuracy of the proposed implemented switching technique in producing associated pulses for the inverter switches at very low frequency to mitigate/eliminate undesired harmonic orders from the output phase/line voltage waveforms without using bulky filters. [ABSTRACT FROM AUTHOR]

For cascaded multilevel inverter topologies with a single dc supply, closed-loop capacitor voltage control is necessary for proper operation. This paper presents zero and reduced common-mode voltage (CMV) operation of a hybrid cascaded multilevel inverter with predictive capacitor voltage control. Each phase of the inverter is realized by cascading two- three-level flying capacitor inverters with a half-bridge module in between. For the presented inverter topology, there are redundant switching states for each inverter voltage levels. By using these switching state redundancies, for every sampling instant, a cost function is evaluated based on the predicted capacitor voltages for each phase. The switching state that minimizes cost function is treated as the best and is switched for that sampling instant. The inverter operates with zero CMV for a modulation index upto 86%. For modulation indices from 86% to 96%, the inverter can operate with reduced CMV magnitude (Vdc/18) and reduced CMV switching frequency using the new space-vector pulsewidth modulation (SVPWM) presented herein. As a result, the linear modulation range is increased to 96% as compared to 86% for zero CMV operation. Simulation and experimental results are presented for the inverter topology for various steady state and transient operating conditions by running an induction motor drive with open loop $V/f$ control scheme. [ABSTRACT FROM PUBLISHER]

The cost reduction of power-electronic devices, the increase in their reliability, efficiency, and power capability, and lower development times, together with more demanding application requirements, has driven the development of several new inverter topologies recently introduced in the industry, particularly medium-voltage converters. New more complex inverter topologies and new application fields come along with additional control challenges, such as voltage imbalances, power-quality issues, higher efficiency needs, and fault-tolerant operation, which necessarily requires the parallel development of modulation schemes. Therefore, recently, there have been significant advances in the field of modulation of dc/ac converters, which conceptually has been dominated during the last several decades almost exclusively by classic pulse-width modulation (PWM) methods. This paper aims to concentrate and discuss the latest developments on this exciting technology, to provide insight on where the state-of-the-art stands today, and analyze the trends and challenges driving its future. [ABSTRACT FROM PUBLISHER]

Grid-connected power converters play a key role in several applications such as the integration of renewable energy sources and motor drives. For this reason, the development of high performance control strategies for this particular class of power converters has increasingly attracted the interest of both academic and industry researchers. This paper presents the predictive optimal switching sequence (OSS) direct power control (DPC) (OSS-DPC) algorithm for grid-connected converters. The OSS-DPC method belongs to the predictive-DPC family and provides the desired power references by calculating globally OSSs. To address computational and implementation issues, an efficient control algorithm, named reduced OSS-DPC, is introduced. The implementation of the proposed control strategy in a standard DSP is evaluated on a two-level power converter prototype working as a STATCOM. Experimental results show the algorithm's potential to provide high performance during both transient and steady states. [ABSTRACT FROM PUBLISHER]

Multilevel converters have received increased interest recently as a result of their ability to generate high quality output waveforms with a low switching frequency. This makes them very attractive for high-power applications. A cascaded H-bridge converter (CHB) is a multilevel topology which is formed from the series connection of H-bridge cells. Optimized pulse width modulation techniques such as selective harmonic elimination or selective harmonic mitigation (SHM-PWM) are capable of preprogramming the harmonic profile of the output waveform over a range of modulation indices. Such modulation methods may, however, not perform optimally if the dc links of the CHB are not balanced. This paper presents a new SHM-PWM control strategy which is capable of meeting grid codes even under nonequal dc link voltages. The method is based on the interpolation of different sets of angles obtained for specific situations of imbalance. Both simulation and experimental results are presented to validate the proposed control method. [ABSTRACT FROM PUBLISHER]