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Accurately estimating the capacity of lithium-ion batteries in electric vehicles (EVs) is critical for making correct management decisions. However, the randomness of the charging voltage range of EVs can lead to missing observations or reduced accuracy of capacity estimation methods. This paper proposes an adaptive battery capacity estimation method suitable for arbitrary charging voltage range based on incremental capacity (IC) analysis and data-driven techniques. All charging conditions of EVs are divided into three categories according to the charging voltage range. Three data-driven estimation sub-methods with sequential application priority are designed for the three charging conditions separately, including back-propagation neural network with IC peak coordinates as input, ensemble learning with local high IC curve as input, and linear regression with ampere-hour coordinate transformation. The method is based on a priori knowledge to select a suitable estimation sub-method under different charging conditions, so as to improve the adaptability. Experimental data is collected from eight commercial lithium-ion battery modules for model establishment and verification. Over 250,000 experimental samples at different states of health and random charging ranges show that the method can accurately estimate battery capacity under arbitrary charging conditions, with a maximum error of 2%.

Three-level inverter has been widely used in electric drives and renewable power generation system. However, the common mode voltage (CMV) and output current ripple reduction of three-level inverter should be carefully regulated for the appropriate operation. As these two targets are mutually interrelated, the conventional space vector modulation (SVM) scheme cannot cope with them decently. To overcome this drawback, this paper proposes a novel modified SVM scheme to realize CMV and current ripple reduction simultaneously. The generating mechanism of output current ripple is analyzed, and the relationship between current ripple and utilized vectors is quantitatively described. Based on the analyses, the proposed optimal current ripple and CMV reduction pulse width modulation (OCR-CMVRPWM) method adopts four voltage vectors (large, medium, small and zero vectors) to reduce root mean square (RMS) value of current ripple by allocating the sequence and dwell times of utilized vectors. Compared to the existing PWM methods, the proposed OCR-CMVRPWM scheme can reduce the peak of CMV to half of value using the conventional SVM, and obtain a significant reduction of output current total harmonic distortion (THD). The effectiveness of the proposed method is validated by both simulation and experimental results.

The conventional model predictive control (MPC) suffers from high common-mode voltage (CMV) magnitude and large current ripples. In this article, the reduced CMV MPC strategy with double vector (RCMV-MPCDV) is proposed for three-level inverters, which adopts double vector to reduce the CMV and current ripples simultaneously in per-sampling period. First, based on geometric relationship of median, a novel cost function that evaluates median line distance is proposed to reduce the computational complexity, rather than evaluating the closest distance. Second, in order to reduce the computational burden, the double vector preselection algorithm is presented with fewer evaluation times. Third, the candidate vectors are reclassified and regrouped from partial basic vectors, which restricts CMV magnitude within one-sixth of dc-link voltage. In addition, to select more satisfactory double vectors for RCMV-MPCDV scheme, two improved methods are proposed to compensate the losing candidate vectors. The simulation and experimental results with steady-state performance and dynamic response validate the effectiveness of the proposed method.

The conventional three-level inverter only has voltage buck capability. The quasi-Z-source three-level T-type inverter (QZS 3LT $^2$ I) has been proposed to realize voltage buck–boost operation. In this paper, we further propose a novel modulation scheme for the QZS 3LT $^2$ I to realize voltage boosting, reduce the common-mode voltage (CMV), and control the neutral-point voltage balance simultaneously. The proposed scheme adopts a large vector, a medium vector, a small vector with low CMV magnitude, a zero vector, and a shoot-through vector to generate the output voltage. According to sector number and neutral-point voltage difference, a p-type or n-type small vector with low CMV magnitude is properly selected to balance the neutral-point voltage. Shoot-through states are inserted within zero vector to boost the dc input voltage without affecting the ac output voltage. Dwell times of basic vectors are calculated through the revised volt–second balance equation. Furthermore, a coordinate control strategy between neutral-point voltage balance and voltage boosting is proposed. Doing so, the CMV magnitude can be restricted within one-sixth of dc-link voltage and neutral-point voltage imbalance can be effectively mitigated. The effectiveness of the proposed scheme is verified by simulations and experiments.

The improved LCL filter is used in transformerless three-level photovoltaic inverter system for leakage current suppression. However, the common-mode (CM) resonance circulating current (CMRCC) is generated, which causes inverter-side current oscillation, leakage current increment, and system instability. To overcome these issues, an improved CM circulating current model with detailed analyses of CMRCC is proposed in this paper. Based on above theories, the CMRCC is influenced by filter parameters, zero-sequence duty ratio, and number of switching transitions. To suppress CMRCC, a hybrid control strategy composed of proportional integral (PI) and feedforward control is presented. It is realized by real-time adjusting zero-sequence duty ratio in space vector modulation technique. Compared with the conventional damping resistor techniques, the CMRCC and leakage current are effectively suppressed with the proposed method. Thus, the performance of inverter-side currents and leakage current suppression is greatly improved. Besides, the capacitor-voltage-feedforward control is adopted to eliminate resonance peak in the differential-mode circuit. Simulation and experimental results are given to demonstrate the effectiveness of theoretical analyses and the proposed method.

Recently, a few fault-tolerant control strategies have been proposed for T-type three-level inverters to improve the reliability of the inverter system. However, the neutral-point (NP) voltage oscillations suppression is never considered in the previous fault-tolerant control strategies. In order to suppress the NP voltage oscillations when open-circuit fault occurs to NP switches, this paper proposes two novel fault-tolerant control strategies named as improved two-level switching tolerant control and hybrid switching tolerant control (HS-TC). Both methods are implemented by adding an optimal time-offset to the three-phase turn- on times. The corresponding time-offset value of each method is simply calculated considering the phase current and dwell time of [O] state. Moreover, an NP voltage balancing algorithm to eliminate the dc deviation and a dc bias to further reduce the NP voltage oscillations are used in the HS-TC. The performance and comparison of the tolerant controls with respect to the NP voltage oscillations, current total harmonic distortion, and dynamic response are illustrated and analyzed through the simulation and experimental results.

The conventional three-level inverter suffers the limitation of voltage buck operation. In order to give both voltage buck and boost operation capability, the quasi-Z-source three-level T-type inverter (3LT $^2$ I) has been proposed. This paper further proposes a space vector modulation (SVM) scheme for the quasi-Z-source 3LT $^2$ I to reduce the magnitude and slew rate of common-mode voltage (CMV). By properly selecting the shoot-through phase, the shoot-through states are inserted within zero vector in order not to affect the active states and output voltage. Doing so, the CMV generated by the quasi-Z-source 3LT $^2$ I is restricted within one-sixth of dc-link voltage, and voltage boosting and CMV reduction can be simultaneously realized. In addition, high dc-link voltage utilization can be maintained. The proposed scheme has been verified in both simulations and experiments. Comparisons are conducted with the conventional SVM method and the phase-shifted sinusoidal PWM method.

This paper proposes a zero-sequence circulating current (ZSCC) control scheme for the multiparalleled three-level T-type inverters (3LT2Is). Based on the analysis with the proposed generalized model of multiparalleled 3LT2Is, it is seen that the ZSCC is influenced by the circuit parameters, duty cycles, and the circulating currents of the l th and first 3LT2I. To mitigate the circulating currents, a deadbeat control strategy for n-paralleled (n≥3) inverters is proposed, which is realized by adjusting the duty cycle of the small vectors in each PWM sampling period. Compared with the conventional PI control method, the ZSCC spike is mitigated with the proposed scheme, thus improving the quality of the output currents. Also, the reliability of the 3LT2Is system is improved because such a scheme only needs the information about the ZSCC and zero-sequence duty ratio in the l th and the first inverter. The proposed method can also be applied to the neutral-point-clamped converters. Simulation and experimental results verify the effectiveness of the theoretical analysis and the proposed method.

Parallel three-level T-type inverters (3LT2Is) can effectively increase the power rating. However, when multiple 3LT2Is are connected to a single dc bus, the zero-sequence circulating current (ZSCC) will occur. The ZSCC will distort the output currents and increase the system loss. To overcome this drawback, this paper proposes a novel deadbeat control scheme for the ZSCC suppression. A generalized model for analyzing ZSCC in parallel 3LT2 Is is developed for designing the deadbeat control method. The proposed deadbeat control scheme is realized by real time adjusting the dwell time of small vectors in each space vector modulation. Compared to the conventional PI control method, the influence of different sector is eliminated, thus, improving the output current waveform and reducing the ZSCC. The effectiveness of the proposed method is verified by simulation and experiments.

The concept of hybrid clamped is proposed in multilevel-inverter topologies, and a hybrid-clamped multilevel-inverter topology comprising active and passive clamping devices is presented in this paper. In this topology, the dc-link capacitor voltages can be balanced without additional circuitry or separated dc voltage sources, regardless of load characteristics. It can be used in real and reactive power conversion applications. The topology structure, operating principle, and self-voltage balancing ability are analyzed. In addition, the validity is confirmed by simulations and experiments based on a five-level inverter. Finally, the functions of different clamping devices are compared

A passive lossless snubber circuit for multilevel inverters is proposed in this paper. The topology is simple and requires no extra control circuit. In order to reduce the high-voltage stress on power switches with this snubber circuit, an improved snubber circuit is presented by adding separate low-power direct current voltage sources into the original one. The operating principles and design considerations are described in detail in this paper. A prototype of a three-phase three-level diode-clamped inverter with the improved passive lossless snubber is built and tested. The simulation and experimental results indicate that not only can it realize the soft switching operation of the three-level inverter with low-voltage stress but also the topology and the control are simple.