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This article presents an improved optimum damping current-mode buck converter with fast-transient response and small-transient voltage using new current sensing circuits. The improved optimum-damping circuit, consisting of the dynamic slope generator and the proposed rail-to-rail current sensor, can stabilize the converter during the output current change and can accelerate the transient response to achieve better figure of merit performance. The dynamic slope generator can compensate the slope to prevent subharmonic oscillation issue and lower undershoot/overshoot without an extra slope compensator. The proposed rail-to-rail current sensor increases the input voltage range, accurately captures the inductor current information, and accelerates the transient response as the load current changes, because it eliminates spikes without the need for a sample-and-hold circuit in a conventional current-sensing circuit. The contributions of the proposed converter are listed in the following: 1) we have proposed a new current-sensing circuit without voltage divider, which can be operated rail-to-rail and improve the dynamic response; 2) the new current-sensing circuit consisted of no switches and therefore, without switching noises; 3) the new current-sensing circuit without voltage divider has a smaller chip area and a smaller path delay; 4) the proposed current-sensing circuit needs no sample-and-hold circuits to reduce current spikes; 5) the transient response and transient voltage of the proposed converter are better than others' works; and 6) we have designed and implemented a new optimum-damping current-mode buck converter with better performances compared with previous publications. more...

This article proposes a low spurious noise and fast-transient-response buck converter with second-order continuous-time delta-sigma modulator (CT-DSM). The DSM technique has the superiority of oversampling and the characteristics of noise shaping to reduce spurious noise and speed up transient response. Moreover, the transient response eruption technique uses a dynamic current compensator to accelerate the transient response. Therefore, the proposed CT-DSM buck converter reduces spurious noise, reduces the output harmonic tones, and accelerates transient response, but it keeps high efficiency, low noise, and low ripple of the traditional switching converter. The proposed DSM buck converter is fabricated in TSMC $\text{0.35}\ \mu\text{m}$ 2P4M CMOS process with a chip area of 1.32 ×1.38 mm. The measurement results show that the peak noise power is −70 dBm across output spectrum, which is −10 dBm lower than a traditional CT-DSM buck converter. When the load current changes from 50 to 500 mA and from 500 to 50 mA, the transient responses are both 4 μs, which are 7 μs faster than the traditional CT-DSM buck converter. The maximum output overshoot voltage is 20 mV, the output voltage ripple is 10 mV, and the conversion peak efficiency is 90.4% at the output voltage of 2.4 V. These characteristics keep the same performances as or even better than the traditional CT-DSM buck converter. more...

This paper presents a high-efficient low-noise buck converter with continuous-time delta-sigma-modulation and burst-mode techniques. The proposed buck converter uses the techniques of over-sampling, noise shaping, burst mode, and continuous-time second-order delta-sigma modulator to achieve low output noise, low overshoot and undershoot voltage, and improve the recovery time. First, the second-order DSM can lower the switching frequency noise, overshoot, and undershoot of the converter. Second, the noise shaping technique can move the noise to high frequency and filter out the noise within bandwidth. Third, the burst-mode technique can accelerate the transient response. The proposed chip is fabricated with a 0.35 μ m Taiwan Semiconductor Manufacturing Company (TSMC) CMOS process and the chip area is 1.5 × 1.5 mm. The transient recovery time is 6 and 16 μ s, when the load current changes from 600 to 50 mA and from 50 to 600 mA, respectively. The output noise spectrum is –67.5 dbm, when output voltage is 2 V. The maximum efficiency is 91.6%, when the output voltage is 2 V. The supply voltage is 3.3 V. The output voltage range of the proposed converter is 1–2.5 V. more...

A sub-1-μs ultrafast-response buck converter utilizing improved analog-voltage-dynamic-estimation (AVDE) techniques is proposed in this letter to improve previous works. First, the improved AVDE controller uses a new pseudocurrent circuit and a new ramp generator to get low gain, wide bandwidth, wide dynamic range, and low equivalent series resistor $(R_{{\text{ESR}}})$ . Second, the proposed converter has high performance, fast transient response, and low output voltage ripple. Third, the circuit does not need slope compensation so that it is very simple to implement. The switching frequency of the proposed buck converter is 1 MHz for nominal 3.3-V input and 0.8–2.5-V output range application. The experimental results prove that the proposed scheme improves the transient response within 1.2 μs and its maximum power efficiency can be up to 91.9%. The fastest transient time of the proposed converter is only 0.8 μs as the switching frequency is equal to 1 MHz. The settling time of the proposed converter is only within 0.8 cycle of the switching frequency. The maximum load current is 300 mA. The proposed buck converter has been fabricated with a commercial 0.35-μm CMOS 2P4M process, and the total chip area is about ${1.46 \;\text{mm}\times 1.5}$ mm, including PADs. more...

A switched capacitor (SC)-based converter with an integrated switch is proposed to improve the efficiency of the traditional SC converter. The proposed converter has the properties of fast transient responses and nonpulsating output current, which can reduce both the output voltage ripple and current stress requirement of the output capacitor. The proposed converter has been implemented using the Taiwan Semiconductor Manufacturing Company Technology Corporation 0.35-μm 3.3/5 V 2P4M CMOS process. The switching frequency is 1 MHz with a 150-mA maximum load current for 3.3-V input and 1.0-4.5-V output range application. The experimental results prove that the power efficiency of the proposed scheme can be up to 90%. more...

This paper proposes a new phase-locked-loop (PLL)-based inductive coupled contactless energy transfer (CET) analog frequency-shift keying (FSK) demodulator using a high-efficiency RF-to-dc rectifier for biomedical implanted devices. The analog FSK demodulator is composed of a modified CMOS three-stage rectifier, a voltage regulator, an FSK signal generator, and a PLL. The proposed modified single-stage rectifier with both positive and negative output voltages using a PMOS and an NMOS pass transistor, an inverter, and two capacitors has a small active area and can enhance the power conversion efficiency. The proposed RF-to-dc rectifier achieves an efficiency of 64% at 8.4 dBm. The power consumption of the demodulator is as low as 0.76 mW, and the active area is 0.084 mm2. The analog FSK demodulator supports a data rate of 100 kb/s to 1 Mb/s. The chip was implemented in a Taiwan Semiconductor Manufacturing Company (TSMC) 0.35- μm double-poly quadruple-metal CMOS technology to verify the proposed CET circuit. Two figures of merit are provided to illustrate the advantages of the proposed architecture. more...

An integrated class-D amplifier with active current sensing suitable for AC switches is presented in this paper. The proposed current-sensing technique is used to sense and control the inductor current at the output stage and allows the current-sensing element to be integrated into class-D amplifiers. To verify the performance of the proposed circuits, a class-D amplifier was designed and fabricated with 3.3-V 0.35- mum double-polyquadruple-metal CMOS technology on a chip area of 1.79 times 1.45 mm. The maximum power efficiency of the class-D amplifier can be up to 94% for an 8-Omega load. These active current-sensing circuits can be applied to other power converters with AC switches. more...

A new monolithic fast-response buck converter using spike-reduction current-sensing circuits is proposed in this paper. The proposed converters are designed and implemented with TSMC 0.35-mum DPQM CMOS processes. The operation frequency can be up to 1.887 MHz. The response time is only 2 mus and compared with other references. The maximum output current is 750 mA, and the maximum power efficiency can be up to 89.1% at 2.442-W output power. The chip area is only 2.157 mm2. more...