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This article proposes an optimized asymmetric pulsewidth modulation (OAPWM) for saliency-based sensorless control of permanent magnet synchronous machines (PMSMs). Compared with the conventional symmetric space vector PWM, OAPWM has merits of longer active vectors and more accurate current slope measurements, which are beneficial to the low-speed sensorless drives. In OAPWM, a distributed zero vector is inserted between two adjacent active vectors. Thus, the current ripple and the power loss can be reduced. Moreover, the length of zero vector is optimized considering the current ripple and modulation index. Then, a current oversampling method and the least square algorithm are adopted to improve the calculation accuracy of the current slope. And the average phase current in one PWM period is calculated using six sampling points. The effectiveness of OAPWM for sensorless control is verified on both 500- and 1500-W PMSMs based on a single field programmable gate array. In comparison with the conventional methods, more accurate position estimation can be achieved during both the transient and steady-state processes.

The overmodulation canimprove the utilization of dc-link voltage in the induction motor (IM) field-weakening (FW) control, thereby extending the maximum output torque. Nevertheless, the high modulation index (MI) will cause severe torque ripple. To figure out the relation between the torque ripple and MI, the amplitude of torque ripple with different MI is calculated quantitatively. Then, a torque quality evaluation function (TQEF) is designed to evaluate the torque quality in overmodulation-FW region by considering both fundamental torque extension and torque ripple suppression. On this basis, a modulation index optimization module is proposed for the maximum TQEF value realization. The analysis shows that the studied method could achieve the optimal trade-off between the fundamental torque extension and the torque ripple suppression. The TQEF value of the studied method is higher than that of the conventional six-step voltage method and the inscribed circle voltage method, meaning that the torque quality is optimized. Finally, the effectiveness of the studied method is verified experimentally on an advanced RISC machines (ARM)-based 3.7 kW IM platform.

In this article, we present a new type of Z -source inverter (ZSI) that replaces two inductors in the original quasi-ZSI with two transformers. It can produce a very high output voltage with the high value of the modulation index. Moreover, it enables both to provide a better power quality of output and to reduce the switching loss. In particular, the proposed quasi-clamped ZSI with two transformers give a unique solution to obtain high gain by reducing the turns ratio, rather than increasing it. Also, the leakage inductance of the transformer might cause huge voltage spikes across the inverter bridge. To deal with this problem, an effective clamping technique is proposed. As a result, this increases the overall efficiency of the system by utilizing the low-power switching devices. The characteristics of the proposed quasi-clamped ZSI with two transformers are comprehensively discussed with the detailed theoretical analysis. Thereafter, its performances are evaluated by both simulation and experimental tests.

This article proposes a novel floating capacitor (FC) and dc-link capacitor voltage balancing scheme for a single-source three-phase nine-level inverter with reduced part count. Although nine levels are generated by keeping the dc-link capacitor voltage to FC voltage ratio as 3:1, it comes with complete absence of any useful pole voltage redundancies. Therefore, the conventionally adopted redundant-state-switching-based pulsewidth modulation technique cannot be applied for FC voltage balancing. Hence, a novel carrier-based modulation scheme is proposed here, which addresses the issue of FC voltage balancing by safely clamping the modulating reference to pole voltage levels that aid in FC voltage balancing. The dc-link capacitor voltages are also balanced using a unique way suitable for this inverter having nonredundant characteristics. Simulation and experimental results verify the capability of the proposed balancing scheme for the optimized nine-level inverter under different modulation and load conditions. It is found that a maximum fundamental phase peak voltage of 0.607 times dc-link voltage (at 0.91 modulation index) can be achieved at unity power factor and, thus, utilizing the dc bus of the inverter effectively.

This article proposes a common-mode voltage (CMV) attenuation method for the three-phase current source inverter (CSI)-fed permanent-magnet synchronous machine drive. The key of this method is to introduce an auxiliary circuit branch connected in parallel with the dc link. Based on the dedicated switching strategy, the zero-voltage-switching conditions are provided for the main switches in the CSI. In particular, the zero current vector is newly constructed without utilizing shoot-through operation in the CSI. Thus, the CMV in the traditional CSI drives is attenuated significantly. Compared with the existing research on CMV suppression, the proposed method will not compromise the modulation index range or increase output current harmonics. Meanwhile, the overshoot voltage can be clamped by the auxiliary power circuit in the dc link under open-circuit fault in the power switches. The system configuration, operating principle, analysis of operation modes, as well as the control scheme are described in detail. Both simulation and experimental results are presented to verify the performance of the proposed method.

It is necessary to suppress the emission level of conducted electromagnetic interference (EMI) for the power electronics converters, and the variable switching frequency pulsewidth modulation (VSFPWM) is an alternative approach to reduce conducted EMI without adding bulky passive components. However, the experimental results indicate that many obvious EMI spikes in spectrum remain so that the conducted EMI reduction for VSFPWM is limited. In order to eliminate the EMI spikes in spectrum, this article first investigates the cause of the EMI spikes for VSFPWM, and the analysis results show that the nonuniform distribution of switching frequency is the primary reason. Then, a novel PWM strategy called uniform distribution PWM (UDPWM) is proposed to eliminate the EMI spikes and to further reduce conducted EMI. The design of a UDPWM is based on the uniform distribution of switching frequency and the principle of less switching loss. Moreover, the analytical formula of switching frequency is also deduced in detail, which adopts fixed variation range of switching frequency whatever the modulation index is. Finally, the experiments are carried out to validate the effectiveness of the UDPWM in reducing conducted EMI and switching loss. The UDPWM can approximately reduce conducted EMI by 20 dB compared with the conventional constant switching frequency PWM, and all obvious spikes in the spectrum are eliminated compared with VSFPWM.

This paper presents a 5-level inverter topology for open-end induction motor drives by using a single dc source. The open stator windings of the drive are supplied with a 3-level flying capacitor inverter from one end and capacitor-fed 2-level inverter from another end. The voltage ratio of the dc link to the capacitor in 2-level inverter is maintained at 4:1 ratio to generate five-level voltage output. The capacitor in 2-level inverter is balanced by the switching redundant vector combinations from both the inverters while the floating capacitors in the 3-level inverter are balanced by using redundant switching states. The proposed topology gives 5-level operation with less number of floating capacitors and power semiconductor switches compared to other existing topologies. Also, the balancing of the capacitors is independent of load power factor and modulation index. Further, the generalization of the proposed dual inverter scheme for any n -level inverter is also included in this paper. The experimental results and required analysis are also presented to validate the inverter scheme.

According to different clamping methods, nine modes (C_MODE1-9) of the traditional discontinuous pulsewidth modulation (DPWM) for neutral-point-clamped three-level converter have been revealed. Since traditional DPWM cannot balance neutral point (NP) voltage under the full range of modulation index (MI) and power factor (PF), two extended modes (E _MODEs) are proposed in this paper, which can balance NP voltage. The proposed extended discontinuous pulsewidth modulation (EDPWM) is characterized by using C_MODEs and E_MODEs alternately.Therefore, EDPWM can balance NP voltage under the full range of MI and PF. Since the switching numbers under C_MODE and E_MODE in one switching cycle are two and three, respectively, the switching loss under EDPWM is lower than that under other pulsewidth modulation (PWM) strategies. The performance of EDPWM is analyzed and compared with traditional DPWM, space vector PWM (SVPWM) and virtual SVPWM (VSVPWM) in terms of switching loss, waveform quality, and the ability of NP voltage control. Finally, the feasibility and superiority of the proposed method are verified by experiments.

High penetration of renewable energies through fast-response power converters results in a considerable displacement of conventional synchronous generators and losing of system inertia for frequency control. Modular multilevel converters (MMCs) can be employed serving as an interface between the large-scale renewable generation and power grids. In a microgrid with high shares of renewables integrating through MMCs, submodule (SM) capacitors can be used as energy storage to provide a degree of synthetic inertia for system frequency support. This paper quantitatively exploits the MMC synthetic inertia in a microgrid with flexible renewable penetration levels. An MMC inertia coefficient concept is proposed. It is mainly affected by the penetration ratio, the SM capacitance, and the modulation index of an MMC, with the system operation constraints. According to the analysis, a substantial portion of system inertia can be provided by properly designed MMCs. Detailed MMC frequency control loops are presented. The capacitor average voltage is proportionally linked to the frequency deviation, in order to flexibly adjust the capacitor energy during frequency events. The MMC output active power is deliberately and simultaneously regulated according to the capacitor energy change rate. By controlling the MMC capacitor voltage, dc side power, and output active power, an amount of energy can be released or absorbed by SM capacitors to improve the system frequency response during the frequency event transients, while the renewable generation is scarcely influenced. The proposed concept is experimentally verified and the results show that, with proper system parameters and control loops, the line frequency deviation and the rate of change of frequency can be significantly reduced. Good agreements of the system frequency characteristics have been achieved between the theoretical calculation and experimental results.

In this paper, space opposite vectors modulation (SOVM) is proposed to decrease common-mode voltage (CMV), and also improve inverter switching losses compared to pulsewidth modulation 7 (PWM7) for dual two-level inverters (DTLI). Employing the control simplicity of DTLI to achieve multilevel winding voltages, the two conventional two-level inverters of DTLI are independently controlled; consequently, the capability of adjusting phase difference between the carriers (PDC) of two inverters is established. To mathematically evaluate and compare the performance of DTLI driven by SOVM and PWM7, CMV and losses for different PWMs are formulated. Moreover, contour, three- and two-dimensional analyses are conducted to investigate the effects of PDC and modulation index on CMV, voltage total harmonic distortion (THD), voltage weighted THD and switching losses. All theoretical bases, simulation results from MATLAB/Simulink and experimental results conducted by a DTLI prototype validate the superiority of SOVM over PWM7.

In this paper, an overmodulation (OVM) technique is proposed based on Fourier analysis. The OVM trajectory is a mixture of six arc segments of the inscribed circle and six vertices of the voltage hexagon. By adjusting the holding angle at each vertex, the modulation index is determined. The fundamental component is expressed as a function of the holding angle, and the linearity with the modulation index is obtained by the inverse relation. This algorithm guarantees seamless transitions from the space vector pulsewidth modulation to OVM and finally to the six-step. Apart from the variable voltage variable frequency control, the proposed algorithm works well with the interior permanent magnet synchronous motor current controller. By computer simulation and experimental evidence, the effectiveness is demonstrated.

This paper presents an improved pulsewidth modulation strategy in conjunction with an optimal compensator for fast capacitor voltage balancing in three-level neutral-point-clamped (NPC) inverter. The voltage balancing compensator is designed in such a way that it produces optimal unbalance compensation coefficient according to the inherent limitations related to the variability range of modulating signals. It generates maximum compensating neutral current for the full modulation depth extending into overmodulation region and throughout the entire range of load power factor angles, and thus improves the unbalance compensation ability for all the operating conditions of the inverter. The optimal compensation offset signal corresponding to each operating point is determined from the boundary limit of the auxiliary modulating signals. Particle swarm optimization is applied for such purpose. The performance of the proposed optimal compensator for different combinations of modulation index and load power factors are evaluated through extensive simulation study using Matlab/Simulink and validated in experimentation using a three-level NPC inverter prototype with induction motor load. Finally, the voltage balancing performances of the proposed compensator are compared with that available in literature to confirm the usefulness of the proposed concept.

Zero-sequence current (ZSC) is inevitable in the structure of an open-end winding permanent-magnet synchronous machine (OW-PMSM) system with a common dc bus due to the simultaneous existence of the ZSC loop and the zero-sequence voltage (ZSV) caused by the inverters and third electromotive force. To suppress the ZSC, a novel strategy with a reduced switching frequency is proposed in this paper. The main contribution of the proposed method is that the ZSC is suppressed totally with a reduced switching frequency. The duration time of the active voltage vectors is redistributed to generate the reference voltage in a zero-sequence loop, which leads to the suppression of the ZSC. Different from the conventional method, only the active voltage vectors instead of the zero voltage vectors are employed to suppress the ZSC. Consequently, the switching frequency in the modulation process can be reduced. In addition, the effective modulation range of the ZSV is analyzed, which further reveals the relationship among the effective modulation of the ZSV, the modulation index, and the ratio of the third flux linkage component to the fundamental flux linkage component. Finally, the effectiveness of the proposed method is validated by an OW-PMSM experimental setup with a common dc bus. Moreover, the proposed method is experimentally compared with the existing methods.

This paper analyzes the characteristics of the submodule (SM) voltage fundamental frequency and second-order harmonic ripples with the consideration of negative voltage state of the full-bridge SM. The optimal operation point, which minimizes the fundamental frequency ripples, is derived. Both the design principle and analytical expressions for SM capacitance dimensioning are presented, and the comparison between energy storage requirements with and without negative voltage states in the arm reference voltages are also carried out under the same constraints on the transmission power, modulation index, and SM voltage fluctuations. However, the SM voltage fundamental frequency ripples increase significantly with reactive power increasing. Therefore, a circulating current injection (CCI) method is proposed in order to suppress the ripples caused by reactive power. Comparative simulations on a ±200 kV hybrid modular multilevel converter (MMC) and experimental results on a laboratory prototype verified the correctness of the presented design principle and the effectiveness of the proposed CCI method. It is shown that the energy storage requirements of the hybrid MMC with negative voltage in arm reference voltages can be reduced about 15%, and it achieves a significant reduction about 45% with the proposed CCI method.

This paper proposes a capacitor voltage regulation method for the dual converter with a floating bridge for aerospace applications. This topology has previously been reported, but with a constrained voltage utilization factor due to the need for capacitor voltage regulations. In this paper, the effect of switching states on the voltage variation of capacitor is quantitatively modeled and an enhanced space vector modulation scheme with current feedback is proposed to achieve an active control of the floating capacitor voltages. This proposed method also allows further exploitation and utilization of converter voltage. The relationship between the allowed modulation index of dual converter and load power factor is obtained and expressed using a fitted polynomial equation. The advantages of the proposed method include boosted voltage utilization and superior performance in term of capacitor voltage balance. These advantages have been proven through simulation and experimental results on RL loads as well as with an open-end winding induction motor. The proposed modulation scheme can boost the converter voltage utilization by at least 10% while achieving full four-level operation. More importantly, the higher available voltage allows extending the constant torque region of the motor, the further beginning of field weakening operation could be postponed.

The carrier-based pulsewidth modulation (CBPWM) and virtual space vector pulsewidth modulation (VSVPWM) for neutral point clamped three-level converter are reviewed briefly in this paper. A novel modulation strategy is proposed to maintain unconditional neutral point voltage balance under the full range of power factor and modulation index. The proposed PWM strategy is featured with three switching actions in one switching cycle, which is named 3SNPBPWM hereafter. In 3SNPBPWM, one phase is clamped to a certain level without switching action, and the other two phases have one and two switching actions in one switching cycle (SC), respectively. Moreover, a neutral point voltage recovery algorithm for 3SNPBPWM is also proposed. The performance of 3SNPBPWM is analyzed and compared with CBPWM and VSVPWM in terms of switching loss, waveform quality, and ability of neutral point voltage recovery. Finally, the feasibility and superiority of 3SNPBPWM are verified by experiment.

This paper presents a fully integrated high-frequency (HF) radio-frequency identification (RFID) tag chip based on the ISO/IEC 15693 and discusses a series of design techniques, including analog and digital control circuits. In order to get a more coupled power supply, an amplitude shift keying demodulator with very low modulation index is proposed. Moreover, modulator, limiter, and electrostatic discharge circuit are mentioned to make the tag IC work effectively and reliably. Besides, digital control circuit with 2-kbit EEPROM memory is designed to help the tag operate correctly under a very low magnetic field. The proposed RFID tag IC was fabricated using a 0.18-μm 2P6M CMOS technology with an area of 926 μm by 855 μm and a power consumption of less than 120 μA. Data rates of 6.62–52.97 kb/s are supported. The tag can operate under a minimum magnetic field of 0.12 A/m and a minimum modulation index of 2.33% which is far less than 10% required by the RFID standard. Compared with the prior references, the proposed tag IC has better performances especially in the aspect of low modulation index.

In this paper, a space-vector-modulation method for indirect matrix converters is proposed to improve the output voltage quality in high modulation index ratios and to reduce the peak common-mode voltage (CMV). A novel approach in the rectifier stage modulation generates a variable dc-link voltage that is controlled to drive the inverter stage on the limit of the linear modulation during each switching period. This allows inherent formation of the output voltage using only two active vectors per sector, which reduces the peak CMV and enhances the output voltage quality. Analytical and experimental studies are carried out to validate the feasibility and the benefits of the proposed modulation technique.

A discrete-time average model-based predictive control (DTA-MPC) is proposed for a quasi-Z-source inverter (qZSI). As a single-stage inverter topology, the qZSI regulates the dc-link voltage and the ac output voltage through the shoot-through (ST) duty cycle and the modulation index. Several feedback strategies have been dedicated to produce these two control variables, among which the most popular are the proportional–integral (PI)-based control and the conventional model-predictive control (MPC). However, in the former, there are tradeoffs between fast response and stability; the latter is robust, but at the cost of high calculation burden and variable switching frequency. Moreover, they require an elaborated design or fine tuning of controller parameters. The proposed DTA-MPC predicts future behaviors of the ST duty cycle and modulation signals, based on the established discrete-time average model of the quasi-Z-source (qZS) inductor current, the qZS capacitor voltage, and load currents. The prediction actions are applied to the qZSI modulator in the next sampling instant, without the need of other controller parameters’ design. A constant switching frequency and significantly reduced computations are achieved with high performance. Transient responses and steady-state accuracy of the qZSI system under the proposed DTA-MPC are investigated and compared with the PI-based control and the conventional MPC. Simulation and experimental results verify the effectiveness of the proposed approach for the qZSI.

Impedance network inverters are the best alternatives for voltage-source and current-source inverters. The boosting capability and the shoot-through solution of such converters make them excellent solutions for various applications. Nevertheless, hard switching forces the converter to operate in low switching frequency, which results in a bulky impedance network. Moreover, the coupling between the shoot-through duty cycle and the inverter modulation index makes a tradeoff between the voltage gain and the modulation index (output voltage harmonics). This paper presents a novel dual switching frequency modulation to mitigate the switching losses of the converter, which results in a more compact impedance network. The proposed method combines a high-frequency pulse width modulation with a low-frequency sinusoidal pulse width modulation (SPWM). Therefore, the switching losses decrease considerably with respect to the conventional simple boost modulation. In addition, the impedance network design frequency remains high, and the network size decreases obviously. The proposed approach removes the interdependence between the shoot-through duty cycle and the inverter modulation index. A comparison between the proposed method and the conventional simple boost method is performed to show its advantages over the conventional method. Finally, experimental results are presented to validate the performance of the proposed method.

This paper proposes a novel 49-level stacked inverter topology for drives. The 49 levels are achieved by stacking three 17-level inverters. Each of the 17-level inverter is developed by cascading a flying capacitor (FC) inverter with three capacitor-fed H-bridges. The device count can be reduced by making the FC and the three cascaded H-bridges common to the dc link in each phase using selector switches in between them. The selector switches need to operate at fundamental frequency only. Also, the devices need to block very low voltages. Hence, MOSFETs can be used. This topology requires three dc sources, each of $V_{\text{dc}}$ /6 only, which can be replaced with stacked batteries for electric vehicle applications. The reduction in the dc voltage requirement is achieved by using a normal symmetric six-phase induction motor with parallel connection of the opposite phase windings. All the floating capacitors in the topology can be balanced irrespective of any modulation index or load power factor. Due to the high number of voltage levels, nearest level control can be used instead of pulse width modulation, which reduces the switching losses. The $dv/dt$ during the inverter operation is also less. Detailed experimental results at different speeds of operation and during transients ensure that the novel topology can be a viable option for high-power adjustable speed drives.

This letter presents a novel middle-level selective harmonic elimination-pulse-amplitude modulation (SHE-PAM) method to calculate switching angles and to synthesize reference voltage for variable dc voltage sources connected to multilevel inverter. Instead of conventional multivariable nonlinear transcendental SHE-pulse-width modulation (SHE-PWM) equations or polynomial equations derived from them, the proposed method works on univariate linear equations. Due to reduced computational complexities, it can be implemented in real-time for the inverter having a large number of levels. Without amplifying the magnitude of higher order harmonics, proposed method eliminates a significant number of harmonics as compared to SHE-PWM and conventional SHE-PAM methods. The total harmonic distortion (THD) of the output voltage is a function of only number of voltage levels and remains constant for a whole range of modulation index. The theoretical analysis and working characteristics of suggested method are validated by simulation and experimental studies.

For three-phase dual-output dc–ac conversion systems, the nine-switch inverter is one of the most versatile available topologies. Despite some disadvantages, recent studies show that the nine-switch inverter achieves efficiency values equivalent to or higher than its 12-switch counterpart, when operating in certain ranges of the modulation index and displacement angles. The use of proper pulse width modulation techniques is able to increase the efficiency even more, as well as to equalize the loss distribution among the switches, favoring an effective and low-cost thermal design. The available pulse width modulation techniques are complex and do not explore the full capacity of the nine-switch inverter to reduce its losses. For this reason, this paper proposes an unrestricted generalized scalar pulse width modulation for nine-switch inverters. Based on this new generalization, a current peak tracking technique is also proposed, achieving small average number of switchings and the highest overall efficiency when compared with other techniques, likewise a more balanced loss distribution among the switches. Experimental results are carried out to demonstrate the validity of the new generalization and the effectiveness of the proposed technique in reducing the switching losses.

This paper proposes a unique carrier-based pulse width modulation strategy for a three-level neutral-point-clamped inverter that works satisfactorily and with uniform convergence time over the full power factor (PF) range of the load variation. It has excellent control over capacitor voltages and mitigates low-frequency oscillations in the neutral point for the full PF range. First, an investigation is made to see how the load currents get modulated to generate compensating neutral current causing charging and discharging of dc-link capacitors. It is observed that when an additional modulating voltage signal that is in phase with the corresponding phase current is added in each phase, a neutral current is produced in the right direction which can be used to compensate for any prior unbalance in capacitor voltages. It is demonstrated that the performance of this scheme is insensitive to the load PF variation (full range from zero to unity). It performs satisfactorily throughout the entire linear modulation range and eliminates any undesirable low-frequency harmonic component in the compensating neutral current. The effectiveness of the proposed scheme is verified through simulation and experimental results by varying load PF as well as modulation index with both passive and motor loads.

This paper presents a new high-frequency modulation method for multilevel converters. The proposed method provides a broad linear operating range and can be digitally implemented with minimal computational effort. This modulation method creates a phase voltage composed of a rectangular component superimposed on the top of a quasi-square-shaped reference function. The reference functions are defined such that the utilization of the dc-link voltage is maximized in any modulation index, while the dv/dt of the switches is always the minimum possible value. In order to implement the proposed method, an update time that is much shorter than the fundamental period is defined in the algorithm for updating the rectangular components of the reference voltage. The high-frequency rectangular component can then be imposed on the reference function to generate the final switching function by switching between two voltage levels during the time between two update instances. Several experimental results are provided to evaluate the performance of the proposed method and to compare its operation to conventional methods.

In this paper, a control method based on the derivative of power is introduced for single-stage single-phase grid-connected cascaded H-bridge (CHB) photovoltaic inverters. The proposed scheme uses solar arrays derivative of power with respect to current to track maximum power point of each array individually. Using this method along with hybrid modulation technique allows utilization of CHB cells up to their full potential. The control system has a simple structure, and is inherently able to stabilize the system under heavy mismatching conditions where the modulation index goes higher than unity. The effectiveness of the proposed technique is verified by simulation and experimental results.

Considering the advantage of the modified stacked multicell converter over flying capacitor and stacked multicell converters, and noting that investigation of the conduction and switching power losses can be advantageous in the design of multilevel converters, an analytical approach to calculate and analyze conduction and switching power losses in modified stacked multicell converter is presented in this paper. First, rms and average currents flowing through the insulated-gate bipolar transistors (IGBTs) and antiparallel diodes are analytically calculated by considering the duty cycle of each IGBT and diode in terms of converter modulation index, load current, and power factor. For validation, numerical results of the derived closed-form equations for computation of the rms and average currents are compared with simulation results and experimental measurements. Numeric computations of the closed-form equations match the simulation results and experimental measurements very well, which verifies the analytic equations. Next, derived equations for rms and average currents computation are utilized to calculate the conduction power losses. Finally, switching power loss analysis is performed by numeric approach and curve fitting method.

This paper presents a hybrid selective harmonic mitigation (SHM)-selective harmonic elimination (SHE) switching technique based on pulse-amplitude modulation (PAM) concept. It has been applied on a four-leg neutral-point-clamped (NPC) inverter to eliminate and mitigate more harmonic orders than recently proposed hybrid SHM-SHE-pulse width modulation (PWM) method while generating switching pulses at the same frequency. In conventional SHE and SHM techniques, equations are solved to attain the switching angles. Regarding the PAM, value of inverter dc voltage can be considered as an additional degree of freedom by which the flexibility of such techniques would be increased maintaining the switching frequency. In the proposed SHM-SHE-PAM, the conventional equations are reformulated to obtain constant switching angles for a vast range of modulation index $(m_{a})$ applied on a four-leg NPC inverter. Switching pulses of the three-phase legs and the fourth leg are calculated to mitigate the nontriplen harmonics and eliminate the triplen ones, respectively. Due to the unique switching angles valid in the whole range for $m_{a}$ , the calculation time and volume (storage capacity) are significantly reduced leading to a simpler controller implementable on a low-risk and cheap AVR chip. Experimental tests’ results of a four-leg NPC inverter as UPS application prove the good dynamic performance and accuracy of the proposed implemented switching technique in producing associated pulses for the inverter switches at very low frequency to mitigate/eliminate undesired harmonic orders from the output phase/line voltage waveforms without using bulky filters.

This paper assesses the feasibility of three-phase pulse-width modulated (PWM) three-level voltage-source converters (VSC), namely neutral-point-clamped (3L-NPC) and T-type (3L-T) as alternatives to two-level converter (2L-VSC) for low-voltage multimegawatt renewable energy grid-connected converter applications. For this purpose, a novel design algorithm that takes switching frequency, capacity factor, modulation index, PWM scheme(s), and converter topology(ies) as input is unveiled to provide the design steps and performance benchmark for the specified topologies and modulation methods. Design of the LCL filter is also addressed, and equivalent output ripple performance criteria is used to benchmark the converter performances for a set of selected filter parameters. Main contribution of this algorithm is that it covers cost and operating factors of the design during the hardware design phase by introducing/modifying the terms of total cost of ownership (TCO) and return on investment (ROI) time considering the major energy markets. The design is detailed for 1-MVA system, and the results are summarized for 0.5 and 2-MVA systems. The study shows that 3L topologies perform more efficiently than 2L-VSC (T-type being the most prominent—with the shortest ROI), whereas the difference becomes much more prominent at the multimegawatt range, provided that all three yield equivalent outputs fulfilling the stringent grid codes.

For cascaded multilevel inverter topologies with a single dc supply, closed-loop capacitor voltage control is necessary for proper operation. This paper presents zero and reduced common-mode voltage (CMV) operation of a hybrid cascaded multilevel inverter with predictive capacitor voltage control. Each phase of the inverter is realized by cascading two- three-level flying capacitor inverters with a half-bridge module in between. For the presented inverter topology, there are redundant switching states for each inverter voltage levels. By using these switching state redundancies, for every sampling instant, a cost function is evaluated based on the predicted capacitor voltages for each phase. The switching state that minimizes cost function is treated as the best and is switched for that sampling instant. The inverter operates with zero CMV for a modulation index upto 86%. For modulation indices from 86% to 96%, the inverter can operate with reduced CMV magnitude ( $V_{\rm dc}/18$ ) and reduced CMV switching frequency using the new space-vector pulsewidth modulation (SVPWM) presented herein. As a result, the linear modulation range is increased to 96% as compared to 86% for zero CMV operation. Simulation and experimental results are presented for the inverter topology for various steady state and transient operating conditions by running an induction motor drive with open loop $V/f$ control scheme.

This paper proposes a new topology for an enhanced-boost Z-source inverter (ZSI) with combined two Z-impedance networks. By two Z-impedance networks and low shoot-through duty cycle, the proposed inverter produces high output voltage gain. In traditional ZSIs for high boosting voltage, a low modulation index is required; hence, under these conditions, the output voltage will have low quality with high total harmonic distortion. Compared with the conventional high-boost ZSI topologies, the proposed inverter uses shorter shoot-through duration and a larger modulation index to improve the output waveform quality. Comparison between the proposed topology and previously proposed schemes, in terms of inductor numbers, voltage and current stresses on elements, sizes of inductors and capacitors, efficiency, and switching device product (SDP) factors of diodes, is made, and the results verify the priority of the proposed topology. The operating principle of the proposed topology is analyzed in detail. Both simulation and experimental results verify the high performance of the proposed inverter.

In this paper, three overmodulation techniques for the three-to-five-phase indirect matrix converter (IMC) are proposed. The first technique utilizes only the adjacent large vectors in the sector in which the reference output voltage vector lies. The second technique improves on that by continuously adapting vector elimination in the $d_2{-}q_2$ vector space based on the output voltage requirements. The third technique utilizes the ripple in the dc link to further reduce the modulation index of the inverter stage during overmodulation. All three techniques increase the voltage transfer ratio of the three-to-five-phase IMC from 0.788 to 0.923, but with the addition of harmonics generated by a vector in the $d_2{-}q_2$ vector space of the inverter stage. Simulation and experimental results from a prototype three-to-five-phase IMC validate the three proposed overmodulation techniques.

This paper investigates time-domain analysis of sampling effect in digital pulsewidth modulation (DPWM) of dc–dc converters. The relation between the sampling delay, duty ratio, and multisampling factor (sampling to carrier frequency ratio) has been characterized. The sampling delay of the digital controller used for DPWM of the dc–dc converter has close relation with the actual pulsewidth-modulation output. An increase in the multisampling factor can reduce the delay effect of the DPWM. The output voltage varies as a stepped function of the duty ratio instead of the linear function as observed in ideal modulation. It is shown in this paper that this delay is a periodic function of the duty ratio. The effect of variations in the sampling frequency, switching frequency, and modulation index has been analyzed. The proposed sampling effect has been verified analytically for the buck, boost, and buck–boost dc–dc converters. The experimental results for the buck and boost converters have been obtained with the control circuit realized through a field-programmable gate array-based digital controller.

Common-mode voltage (CMV) is one of the most important issues for the power electronics inverters. An interesting space vector modulation of the three-leg current-source inverter has been reported for the CMV reduction recently. However, it has the disadvantages of the bipolar current pulses and modulation index range limitation. In order to solve these problems, a four-leg current-source inverter with a new space vector modulation is proposed in this paper. With the proposed method, the system CMV can be significantly reduced without bipolar current pulses and modulation index range limitation. Finally, the experimental tests are carried out on a four-leg current-source inverter, and the experimental results verify the effectiveness of the proposed method.

A low device switching frequency operation is essential in medium-voltage (MV) high-power drives to increase semiconductor device utilization as well as to achieve higher overall system efficiency. However, there exists a tradeoff between device switching frequency and harmonic distortion of machine currents. Synchronous optimal pulsewidth modulation (SOP) is an evolving technique for controlling multilevel inverters of MV ac drives at low device switching frequency without compromising the quality of machine currents. The state-of-the-art generalized SOP algorithm for five or higher level inverters leads to unequal device switching frequency, and also, transients in machine currents are possible due to the change in the number of switching instants at higher modulation index values. The goal of our study is to propose a new SOP technique that ensures equal device switching frequency and further reduces device switching frequency compared to the generalized SOP method. Also, it is expected that machine current transients at higher modulation index values will be reduced. The proposed SOP technique has been verified experimentally on a cascade nine-level inverter-fed 1.5-kW induction motor drive.

Power converters using deterministic switching frequency schemes have switching noise concentrated at harmonic frequencies, resulting in enhanced electromagnetic emission. To suppress the harmonic spikes in three-phase multilevel voltage source converters, a digital control scheme based on dithered sigma–delta modulation (SDM) is proposed in this paper. Introducing a dithered sequence in an SDM varies the switching frequency randomly, resulting in the suppression of the spurious harmonic spikes in the output spectrum even with a regular control input. Although the switching frequency varies randomly, the minimum pulsewidth of the proposed scheme is the sampling time period, avoiding the minimum pulsewidth problem. Instead of a conventional scalar quantizer, the quantizer in the proposed dithered sigma–delta converter uses the principle of space vector quantization. The proposed scheme is experimentally verified on a constant $v/f$ open-loop induction motor drive for a three-level inverter realized by cascading two two-level inverters. The performance of the proposed scheme is compared with different pulsewidth modulation schemes in the entire modulation index, including the overmodulation region.

This paper proposes a pulsewidth-modulation strategy to achieve balanced line-to-line output voltages and to maximize the modulation index in the linear modulation range where the output voltage can be linearly adjusted in the multilevel cascaded inverter (MLCI) operating under unbalanced dc-link conditions. In these conditions, the linear modulation range is reduced, and a significant output voltage imbalance may occur as voltage references increase. In order to analyze these effects, the voltage vector space for MLCI is evaluated in detail. From this analysis, the theory behind the output voltage imbalance is explained, and the maximum linear modulation range considering an unbalanced dc-link condition is evaluated. After that, a neutral voltage modulation strategy is proposed to achieve output voltage balancing as well as to extend the linear modulation range up to the maximum reachable point in theory. In the proposed method, too large of a dc-link imbalance precludes the balancing of the output voltages. This limitation is also discussed. Both the simulations and the experiments for a seven-level phase-shifted modulated MLCI for electric vehicle traction motor drive show that the proposed method is able to balance line-to-line output voltages as well as to maximize the linear modulation range under the unbalanced dc-link conditions.

In this paper, the analysis of space vector modulation of a three-phase/wire/level Vienna rectifier is conducted, according to which the implementation of the equivalent carrier-based pulsewidth modulation is deduced theoretically within each separated sector in the diagram of vectors. The voltage balancing ability of dc-link neutral point, which depends on the uneven distribution of short vectors, is analyzed as well. An adaptive and robust controller to balance the output voltage under the unbalanced load limit for different modulation indices is proposed. The proposed controller can work at wide range of unbalanced load condition as well. Furthermore, the maximum unbalanced load is deduced versus the modulation index m when the converter works in unity power factor. An experimental prototype of 2.5 kW was built to verify the effectiveness of the theoretical analysis. Finally, the tested unbalanced limit of outputs for the experimental platform was given under different modulation indices. The output voltages for dual bus are balanced, and the theoretical analysis is verified.

Cascaded multilevel (CM) converter is a series connection of several inverters that together generate multiple voltage levels with controllable frequency, phase, and amplitude. Its main advantages are high power, reliability, and power quality. However, it has considerable drawbacks such as high number of components, many isolated power sources, decreasing voltage quality with the modulation index, and regeneration in some series inverters at specific modulation indexes, even when the machine is motoring. The authors propose to improve any CM topology through two solutions: use optimal voltage asymmetries (ratios), higher than conventional ones; replace the voltage sources by floating capacitors balanced with a new control (PI controller) and/or a high-frequency link. This paper presents theoretical analysis and experimental results of CM converters with increased voltage-quality (levels), some of them keeping this high quality and avoiding regeneration in motor mode at any motor operation point, using the proposed voltage asymmetries and simplifying or eliminating some voltage sources. Experimental results show a reduction of components, an improved voltage quality, and a satisfactory behavior in stationary and dynamic operation.

In this paper, a sensorless method for low- and zero-speed operations is proposed for a high-power medium-voltage pulsewidth-modulated current-source-converter-fed interior-permanent-magnet motor drive system. The proposed method is based on the injection of a high frequency (HF) pulsating sinusoidal signal in the estimated synchronous reference frame of the drive's field-oriented control (FOC) scheme. The conventional FOC control scheme, low switching frequency, dc-link inductor, and the inverter output three-phase filter capacitor of the medium-voltage high-power current-source drive present some challenges in the generation and design of the HF-injection signal. To overcome these challenges, the FOC scheme is modified by introducing a modulation index control with suitable dc-link current compensation to enhance the dynamic response of the injected signal and prevent any clamp in the injected signal. In addition, a multisampling-space-vector-modulation method is proposed to prevent the distortion in the HF signal due to a low switching frequency to injected signal ratio. A detailed study and analysis regarding the influence of low switching frequency, output filter capacitor, and magnetic saturation in the injection method is carried out to determine the visible HF range of the injected signal. It is found that, by using the proposed FOC scheme and multisampling modulation scheme and by the proper design of the HF signal, an accurate rotor flux angle can be estimated for sensorless zero-/low-speed operations. Experimental results are provided to verify the proposed control method.

A new pulse width modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is developed and presented in this paper. The proposed PWM scheme not only takes advantage of the special properties available in NPC inverters, but also reduces the switching loss of the inverter along with an inherent neutral point (NP) voltage control. Based on a circuit-level decoupling concept, the NPC inverter can be decoupled into two three-level Buck converters in every defined operating section, and thereby the controller design can be simplified. The salient features of the proposed scheme, as compared with the existing carrier-based DPWM strategies, are: 1) its reduced computational processing time, 2) its capability to balance the dc-link voltage without any additional control, and 3) its reduced complexity, e.g., only one carrier wave needed for pulse width modulating. Same as a space-vector modulation, the maximum modulation index, 1.1547, can be attainable by the proposed scheme. Moreover, compared to conventional continuous sinusoidal PWM, using this technique proposed here, the switching losses of the devices can be reduced by one third. In order to explain the operation of this topology properly, the decoupling principle including the driving signal synthesis and the NP potential variation are analyzed in detail in this paper. Finally, the viability and performance of the proposed modulation scheme are shown through simulation and experimental results in a laboratory prototype.

The voltage-fed Z-source inverter/quasi-Z-source inverter (qZSI) has been presented suitable for photovoltaic (PV) applications mainly because of its single-stage buck and boost capability and improved reliability. This paper further addresses detailed modeling and control issues of the qZSI used for distributed generation (DG), such as PV or fuel cell power conditioning. The dynamical characteristics of the qZSI network are first investigated by small-signal analysis. Based on the dynamic model, stand-alone operation and grid-connected operation with closed-loop control methods are carried out, which are the two necessary operation modes of DG in distributed power grids. Due to the mutual limitation between the modulation index and shoot-through duty ratio of qZSI, constant capacitor voltage control method is proposed in a two-stage control manner. Minimum switching stress on devices can be achieved by choosing a proper capacitor voltage reference. Experimental results are presented for validation of the theoretical analysis and controller design.

This paper proposes a three-phase current reconstruction technique with an online current offset compensation function for three-phase inverter applications utilizing only a single current sensor. In the proposed current sensing method, a phase current and a branch current are simultaneously measured twice in a switching period by using a single current sensor. After that, the current reconstruction algorithm is applied to obtain the three-phase current information. Compared to previous single current sensor strategies, in the proposed method, the sensor output is regularly sampled, and the dead zone is located near the boundary of the voltage vector space instead of near the origin and the borders of each sector. This boundary-neighbored dead zone makes the proposed method more attractive in extremely low modulation index cases because it avoids periodical dead zones which have been an issue in the existing methods. Moreover, the online compensation method for a current measurement offset makes it possible to achieve purely balanced three-phase current control without an offset component. The effectiveness of the proposed method has been verified through simulations and experiments by measuring and reconstructing three-phase currents under various conditions.

In this paper, an input power factor compensation method is proposed for a high-power pulse-width-modulated current-source-converter (CSC)-fed permanent magnet synchronous motor (PMSM) drive system. The proposed method is based on controlling the d-axis stator current component in the field-oriented control (FOC) scheme of the drive system. The CSC-fed PMSM drive system and its FOC scheme are first introduced. Then, the relationships between the machine side, dc-link, and the line side are investigated. Based on the analysis, a new d-axis stator current control scheme that can ensure unity input power factor for the operating speed range is proposed. The main feature of the proposed scheme is to compensate the line-side power factor without the need for modulation index control in either the rectifier or the inverter. Therefore, offline Selective Harmonic Elimination (SHE) modulation schemes can be implemented on both line- and machine-side converters to minimize the total harmonic distortion. This results in reduced switching frequency and reduced switching losses. Simulation results for a 2.44 MW medium-voltage system and experimental results from a low-voltage 6.5 kW IPM motor drive are provided to verify the effectiveness of the proposed compensation method.

This paper extends the Z-source concept to matrix converters and explores a family of Z-source matrix converters. Their principles and characteristics are analyzed, and a simplified voltage-fed Z-source matrix converter is used as an example to demonstrate its operation, voltage gain versus modulation index, PWM method, boost control, and implementation of the control. Both simulation and experimental results verify operation of the proposed Z-source matrix converter, analytical results, and control method. The Z-source converters can achieve buck and boost operation with reduced number of switches needed, therefore achieving low cost, high efficiency, and reliability, compared to the traditional matrix converters.

In this paper, a real-time circulating current reduction method for parallel harmonic-elimination pulsewidth modulation (HEPWM) inverters is proposed. HEPWM techniques are often used in high-capacity inverters. For instance, in a hybrid microgrid, the inverters are employed to transfer power between the dc and ac buses. If the inverters are in parallel operation, the zero-sequence path can be established, and the zero-sequence circulating current will circulate among the inverters. The proposed method installs a cascade null-vector control system behind the conventional three-phase HEPWM modulator. The proposed null-vector control system can be disabled to save switching losses when the zero-sequence circulating current is small, whereas it can be enabled when the zero-sequence circulating current becomes large. The proposed method does not affect the line-to-line voltage waveforms of HEPWM inverters, and it can easily enable/disable the null-vector control system to provide bumpless transfer. Compared with the conventional HEPWM with zero-sequence harmonics elimination, the proposed method can provide an extra 15% modulation index range. Results that were obtained from both simulation and experiments confirmed the performance and effectiveness of the proposed method.

The matrix converter is a single-stage ac-ac power conversion device without dc-link energy storage elements. Any disturbance in the input voltages will be immediately reflected to the output voltages. In this paper, a modified space vector modulation strategy for matrix converter has been presented under the abnormal input-voltage conditions, in terms of unbalance, nonsinusoid, and surge (sudden rising or sudden dropping). By using the instantaneous magnitude and phase of input-voltage vector to calculate the voltage modulation index and input-current phase angle, this modified modulation strategy can eliminate the influence of the abnormal input voltages on output side without an additional control circuit, and three-phase sinusoidal symmetrical voltages or currents can be obtained under normal and abnormal input-voltage conditions. The performance of the input currents is analyzed when the matrix converter uses different modulation strategies. Some numerical simulations are presented to confirm the analytical results. Tests are carried out on a 5.5-kW matrix converter prototype. Experimental results verify the validity of the proposed strategy.