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The stability and accuracy of power hardware-in-the-loop (PHIL) setups are sensitive to and deteriorated by the dynamics and nonideal characteristics of their power interfaces, such as time delay, noise perturbation, and signal distortion. In this article, a compensation scheme comprising a Smith predictor compensator is proposed to mitigate the impact of time delay on PHIL stability. Furthermore, an online system impedance identification technique is leveraged to enhance the robustness of the compensator and facilitate the compensation scheme with adaptivity to system impedance variation. Analytical assessment, simulation results, and PHIL experimental results are presented to verify the proposed compensation scheme. This scheme enables robust and stable testing of novel power technologies under varying impedance ratios representative of the complex scenarios emerging within the power sector.