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Multilevel converters have many power devices and drivers. Thus, a direct reliability calculation based only on the first failure occurrence on one of the components clearly leads them to be devalued compared to two-level converters. However, taking into account that symmetrical multilevel converters such as the X-level active neutral point clamped (ANPC) family are based on imbricated and/or stacked switching cells on the one hand, with an additional center tap at the dc bus in three-phase operation on the other hand, several redundancies clearly appear which can be managed to increase the global reliability. For the first time, a general and theoretical methodology used to calculate reliability laws and failure rates and applied to compare two-, three-, and five-level topologies is proposed. Results show that the fault handling of three- and five-level three-phase topologies permits a great increase in reliability over a “relatively” short time duration, in addition to other benefits. [ABSTRACT FROM PUBLISHER]

A five-level power factor correction topology with fault-diagnosis and fault-tolerant capabilities is proposed and analyzed. This structure is derived from the well-known three-level one-pole double-boost including double-stacked redundant and low-storage-energy flying capacitor cells. Two fault-diagnosis strategies are presented. The first one directly operates the monitoring of the voltages across the flying capacitors, detecting and localizing the faulty switch by means of two sensors. The second one is based on indirect voltage vector detection through only one sensor. Both of these strategies are analyzed and simulated with the efficient phase disposition pulsewidth modulation technique. The design and the most important features are highlighted owing to a digital control frame and a single-phase mock-up rated at 115 V/400 V, - 4 kW, and 2 \times 31 kHz. The presented results also offer a dedicated strategy permitting an optimized real-time reconfiguration in postfault operation. [ABSTRACT FROM PUBLISHER]

This paper deals with a hybrid fault-tolerant converter topology. It is performed through the connection of a classical three-phase three-level neutral-point-clamped (3L-NPC) converter with a fourth three-level flying capacitor (3L-FC) leg. The 3L-FC leg actively balances the 3L-NPC neutral-point voltage. For normal operation mode, this paper proposes a mathematical design of the filter needed to connect these two different topologies. Experimentally, and thanks to the already existing decoupling capacitors of the 3L-NPC converter, this filter requires the addition of only one low size inductance. When one fault of the power switch of the 3L-NPC occurs, this paper proposes a hardware reconfiguration technique based on only two fuses and one thyristor per leg allows a safe postfault operation recovery. This is achieved thanks to a simple fault-detection method and a new technique that combines fault leg isolation and corresponding phase postfault connection to the neutral point. Also, a dedicated field-programmable gate array (FPGA)-based control of the reconfigured converter is synthetized to ensure power system availability under fault operation mode. The converter fault-tolerant capabilities are addressed through simulation results and original overall experimental validations of the fault detection and isolation and the postfault operation steps, carried out on a 15-kW prototype converter. [ABSTRACT FROM AUTHOR]

Power-factor-corrector (PFC) converters are now commonly used in low-power supply systems connected to ac net- works. In addition to their basic PFC properties, they constitute the best technical solution to directly obtain the compatibility with a large range of ac voltages provided by different distribution networks around the world (typically, from 85 to 265 V rms). It is the main application of these converters. This function is achieved with an additional cost and volume, and this extra price to pay needs to be minimized. In this context, we first recall the main approaches of the de- sign of conventional PFCs based on the boostconverter topology. We emphasize the different critical points of the sizing that mainly concern the input choke and the silicon devices, in regard with the choice of the switching frequency. Few ways of improvement are then presented for these conventional PFCs. In a second part, always in the context of a large input voltage range, we consider the possibility to introduce the multi-level concept to reduce the input choke and filters. A solution using a multi-level flying Capacitor Two-Cell converter is presented. It is shown that it can lead to a significant increase of the performances, with several options of sizing which can be suited to different requirements of the applications. [ABSTRACT FROM AUTHOR]