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This paper proposes two hybrid asymmetric cascaded multilevel inverters for driving medium-voltage open-end winding motors. Each phase of the proposed systems consist of a three-level (3L) H-bridge cell and a nine-level (9L) H-bridge cell connected in series. An unequal dc-voltage ratio of 1:8 between cells is used, providing 19 phase voltage levels. The topologies of the 9L H-bridge cell are based on modular multilevel cascade converter (MMCC) with double-star chopper cells, while the 3L H-bridge cell is fed by a floating capacitor. Compared to conventional MMCC for open-end stator winding motor drives, the proposed inverters can produce more phase voltage levels. In addition, they require a smaller number of power semiconductor switches, drivers and capacitors. Simulations and experimental results are presented in order to demonstrate the performance and feasibility of the proposed topologies. [ABSTRACT FROM AUTHOR]

Nowadays, a multilevel converter represents a good idea for commercial and industrial applications, where small size and cost, low maintenance, reliability in a wide range of environments, and good efficiency are required. Furthermore, the multilevel converter can provide control for both maximum power tracking and output power factor reducing the filter weight and volume. The proposed power converter topology, called five-level E-type inverter (5L E-Type Inverter), for grid-connected applications is presented and analyzed in this paper. The performance of the three-phase 5L E-Type Inverter has been theoretically investigated. The thermal models of the power semiconductor have been created taking into account the parameters provided by the manufactures and employing multidimensional lookup tables in the Plexim/PLECS environment. The design and selection of passive components have been described in order to obtain amazing performances in terms of weight, volume, and efficiency and power quality. New control strategy, named concurrent control, for 5L E-Type Inverter has been implemented and validated in the LabVIEW development environment. The peak efficiency of the converter above 98.3% and the total harmonic total harmonic distortion current (THDi) less than 3% have been achieved. [ABSTRACT FROM AUTHOR]

This paper is concerned with the use of a three-level inverter for a synchronous reluctance machine (SynRM). The SynRM suffers from a poor power factor due to poor machine saliency. This makes it harder to operate the three-level neutral-point-clamped inverter due to a strict requirement to have the two dc-link capacitor voltages balanced. This paper proposes a new nearest three vector modulation algorithm which can balance the two dc-link capacitors even at poor machine saliency ratio (poor power factor). In this paper, a method of sizing the two dc-link capacitors based on the machine power is also proposed. A comparison between two- and three-level inverters was conducted. The SynRM registered lower $d$-axis current ripple with a three-level inverter, indicating lower core losses in the machine. [ABSTRACT FROM PUBLISHER]

This paper proposes a vector control strategy for independent control of two permanent-magnet synchronous motors (PMSMs) using a single four-leg inverter (4LI). An expanded two-arm modulation to obtain a balanced three-phase output voltage is described. This paper also proposes a method to compensate for the fluctuations in the neutral point voltage of two split capacitors in the dc link. The experimental results show that independent speed and position control of two PMSMs can be achieved using a single 4LI with the proposed vector control method. [ABSTRACT FROM AUTHOR]

Space vector modulation (SVM) is a widely used method for multilevel inverters. Most of the SVM methods are nearest three vector (N3V) based schemes. Therefore, several researchers have proposed advanced implementation algorithms with reduced complexity for N3V methods. However, topologies like neutral point (NP) clamped inverter (NPCI) require some distinctive methods (called as non-N3V methods) to balance NP voltage for high modulation index and low power factor operations. Currently, the existing non-N3V methods exercise highly complex algorithms for duty ratio calculation and subtriangle identification. This paper presents a new approach, suitable for both N3V and non-N3V methods, with reduced implementation complexity. The proposed algorithm is based on an equivalent two-level space vector diagram and does not require any trigonometry, coordinate transformation, or volt-second balance solution. Unlike other carrier-based methods, it can change the switching sequence as well as the duration of redundant vectors. Moreover, the proposed approach does not require extra steps for implementing hybrid modulation and it can also be extended to multilevel topologies. One N3V, two non-N3V, and hybrid methods are developed using the proposed modulation algorithm, and are compared in detail. Simulation and experimentation on a three-level NPCI verify the validity of the proposed algorithm. [ABSTRACT FROM PUBLISHER]

This paper proposes a new nine-level inverter for medium- and high-power applications. The proposed topology comprises of a three-level (3L) active neutral-point-clamped (ANPC) inverter connected in series with a floating capacitor (FC) fed H-bridge. Besides, two additional switches operating at line frequency are appended across the dc link of the 3L ANPC structure. Compared with conventional hybrid cascaded inverters, the primary advantage of this addition is doubling of the resulting root mean square output voltage. This amelioration is achieved while preserving the standard 3L ANPC and H-bridge structures with minimum topological modification. A simple logic-gate-based voltage balancing scheme is developed to regulate the FC voltage. The proposed voltage balancing method is independent of load power factor, inverter modulation index, and can balance the voltage across FC instantaneously. The step-by-step formulation of logical expressions for the generation of gating pulses is deliberated in detail and can be generalized for any $n$-level inverter. Further, simulation results as well as the experimental measurements obtained from the laboratory prototype are presented to validate the effectiveness and practicability of the proposed configuration. Finally, the notable merits of the proposed inverter over the prior art topologies is established through a comprehensive comparative study. [ABSTRACT FROM PUBLISHER]

Three-phase inverters in uninterrupted power supply, electric vehicles, and hybrid electric vehicles use an intermediate dc-link electrolytic capacitor, which has reliability issues and is one prominent cause of inverter failure and limited life. The large volume of an electrolytic capacitor increases the size and cost of the system. Recent research on electrolytic capacitorless inverters using six-pulse modulation technique along with high-frequency power conversion has attempted to address this issue. However, closed-loop operation and control has some issues due to capacitorless dc-link. In this paper, closed-loop operation, design, and implementation of an electrolytic capacitorless inverter is presented. A proof-of-concept 1-kW hardware prototype has been built and tested in a laboratory under different loading conditions. In total, 98% rated efficiency of the inverter is obtained with total harmonic distortion within 2%. Transient results during start-up and load change are smooth, demonstrating safe operation of the inverter. [ABSTRACT FROM AUTHOR]

In this paper, two modulation strategies called Mod-1 and Mod-2 are compared for a three-level diode neutral-point-clamped (NPC) inverter synchronous reluctance machine (SynRM) drive. These modulation strategies do not operate at a fixed switching frequency. A new modulation strategy which operates at a fixed switching frequency is proposed called Mod-3. The SynRM suffers from a poor power factor which makes it harder to archive capacitor voltage balancing for a three-level NPC inverter. These modulation strategies are of the nearest three vector (NTV) family. Mod-1 and Mod-3 choose certain vector states to achieve capacitor voltage balancing, whereas Mod-2 strategy makes use of the inverter vector state’s dwell time. The parameters of interest are the torque ripple, the neutral point (NP) voltage ripple, the inverter efficiency, and the $d$-axis current ripple. Though lower torque ripple and better power quality are registered on Mod-2 strategy. Mod-1 strategy has 14% improvement in inverter efficiency at lower modulation index ($m_i = 0.4$). Mod-2 strategy has 11% more NP voltage ripple at a modulation index of 0.4. One of the disadvantages of Mod-1 strategy is the varying switching frequency. Mod-3 scheme produced higher inverter efficiency, better balancing of the capacitor voltages, and guaranteed fixed inverter switching frequency. The disadvantage with Mod-3 strategy is that it generated higher torque ripple, $d$-axis current ripple, and current total harmonic distortion when compared to Mod-1 and Mod-2 at the same load conditions. [ABSTRACT FROM AUTHOR]