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A gate driving for power devices is a key technology to further improve switching characteristics. With the help of digital gate driver IC, the switching behavior of power devices can be enhanced even under high-speed switching. In this paper, an evaluation platform for determining the optimal switching pattern of an active gate drive control is proposed for an inverter circuit. A high speed optimization system is built up to search for an advantageous switching pattern that reduces total switching loss of two power devices in an inverter circuit and constrains surge voltage simultaneously. The proposed online optimization demonstrates its feasibility for the full-bridge inverter circuit, which is rated at 500 V with digital active gate drive control. Experimental results show that the proposed optimization system is able to obtain optimal switching pattern from $64^{60}$ possible combinations of switching patterns within 15 min, which is 6 times faster than the previous study. Optimizations can also conducted under different load current conditions. Eventually, the obtained optimal pattern yields up to 42% reduction in the total switching loss when it constrains surge voltage to minimum compared with the conventional driving pattern. [ABSTRACT FROM AUTHOR]

One of the main challenges of the solid-state transformer (SST) lies in the implementation of the dc–dc stage. In this paper, a quadruple-active-bridge (QAB) dc–dc converter is investigated to be used as a basic module of a modular three-stage SST. Besides the feature of high power density and soft-switching operation (also found in others converters), the QAB converter provides a solution with reduced number of high-frequency transformers, since more bridges are connected to the same multiwinding transformer. To ensure soft switching for the entire operation range of the QAB converter, the triangular current-mode modulation strategy, previously adopted for the dual-active-bridge converter, is extended to the QAB converter. The theoretical analysis is developed considering balanced (equal power processed by the medium-voltage (MV) cells) and unbalanced (unequal power processed by the MV cells) conditions. In order to validate the theoretical analysis developed in the paper, a 2-kW prototype is built and experimented. [ABSTRACT FROM PUBLISHER]

This paper presents a new least-mean-square (LMS) algorithm based deadtime compensation method to suppress the current distortion in permanent-magnet synchronous motor (PMSM) field-oriented control (FOC) drives. Compared to conventional average value compensations, the proposed method is robust to switching device parameter variations thanks to the online adaptation capability of the LMS algorithm. Similarly, the disturbance observer compensators are also immune to switching device parameter variations; however, varying motor parameters degrade their compensation performance. Without prior knowledge of switching device or motor parameters, the proposed method can directly reduce the deadtime current harmonics by generating compensation voltage references. In addition, the proposed method is easy to implement since it does not require voltage errors estimation or current harmonics extraction, which are necessary for disturbance observer and adaptive filter based methods. The proposed method is tested on a 2.5-kW voltage-source inverter PMSM drive controlled by an FOC algorithm. Its effectiveness is validated by both experimental results and spectrum analysis. [ABSTRACT FROM AUTHOR]

An adaptive control of DPWM implementable in clamped-three-level inverters with two strings of photovoltaic (PV) panels in cascaded connection is proposed in this paper. The proposed modulation is developed based on the so-called circuit-level decoupling concept. It is able to provide balance line voltage even under unbalanced dc links. The unequal dc voltages appeared due to asymmetric maximum point of power trackings (MPPTs) are controlled by proper injection of zero-sequence voltage to the common mode voltage, while the total dc voltage is regulated based on the voltage commands generated by the MPPT of each string. Thus, both PV strings are able to be operated based on their MPPTs while there is almost no low-order harmonic distortion at the inverter output current. Compared with the previous methods, the high capability of the proposed method is evaluated by simulation study and experimental tests. [ABSTRACT FROM AUTHOR]

Inverter dead-time is known to make open-loop induction motor drives oscillatory, while operating at light-loads in particular. While dead-time compensation schemes exist, precise compensation of the same is often challenging as it involves factors such as device and driver delays and switching transition times, which are difficult to be quantified accurately. Hence, the effect of dead-time could be under or overcompensated. This paper presents a comprehensive analysis of the impact of such undercompensation and overcompensation on the stability of a 100-kW induction motor drive, along with experimental investigations of the same. The effects of undercompensation and overcompensation on the inverter output voltage are analyzed on a switching-cycle average basis. Further, small-signal models are proposed for an open-loop drive, when it is undercompensated and overcompensated. Stability analysis of the above motor drive is reported, which predicts oscillatory behavior with both under and overcompensation, over certain fundamental frequency ranges, respectively. Further, two different types of oscillatory behavior, characterized by different oscillating frequencies, are observed for the cases of under and overcompensation. The analyses are supported by simulations. Experimental investigations carried out also support the analyses and simulation results. [ABSTRACT FROM AUTHOR]

This paper investigates a multilevel inverter composed of series/parallel-connected H-bridges. The presented structure can be used for applications in which the use of semiconductor switches with low-voltage and low-current ratings is intended. A comprehensive system model, an overall control strategy to adjust the output voltage with constant magnitude and frequency, and a level-shifted PWM (LS-PWM) strategy based on a voltage vectors unidimensional analysis and a plane analysis are presented. The LS-PWM is capable of mitigating the low-frequency circulating current, thus generating multilevel voltage signals with low harmonic distortion, maximum number of levels, and low dv/dt. In addition, considering a wide range of values of voltages and currents and various power levels, the total converter losses are reduced compared with the conventional multilevel converters. Two multilevel conventional inverters with the same number of semiconductor switches are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

This paper presents a nine-level transformer-based inverter requiring only eight switches. The envisaged structure consists of two standard H-bridges fed from a single dc source. Besides, a single-phase transformer is employed to aid the process of intermediate voltage level generation. An ad-hoc pulsewidth modulation scheme based on boolean logic form equations is developed to derive the gating pulses. An effortless extension of the proposed inverter to a higher number of voltage levels is also achieved by generalizing the switching functions. Furthermore, the superior performance of the proposed topology is demonstrated through a comprehensive cost-based analysis. Finally, the validation of the proposed topology is accomplished through experiments on a down-scale prototype, and the measurement results are included. [ABSTRACT FROM AUTHOR]

The requirements for peripheral circuits of power converters are becoming more restrictive due to the enhancement of Si-based power devices and due to practical use of SiC device. In the design of modern high-speed switching converters, the stray inductances and capacitances both in the device package and in the gate drive circuit in addition to those in the main circuit of the power converter must be considered. In these situations, the gate driving technique represents the key technology for enhancement of high-speed switching ability of power devices, as there are design limitations to reduce the stray inductances and capacitances. So far, several active gate control methods have been proposed. Most conventional active gate drivers are configured using analog circuits such as transistors and diodes. Thus, it is difficult to reconfigure their control parameters to fit the stray inductances and capacitances after the implementation of power converter and gate circuits. As a solution to these problems, the authors have proposed a programmable gate driver IC, which is a digitally controlled circuit. This gate driver IC can control the gate current at 63 separate levels, operated by programmable fully digital 12-bit and clock signals. In this paper, an active gate current control based on the load current in a half-bridge inverter with two programmable gate driver ICs is demonstrated. This developed gate control is different to the general current feedback control followed the reference value. It is verified that the proposed active gate control can effectively improve the tradeoff relationship between the surge voltage and switching loss of the pulsewidth modulation half-bridge inverter circuit. [ABSTRACT FROM AUTHOR]

This paper proposes new angles constraint for selective harmonic elimination-pulsewidth modulation (SHE)-PWM utilized in single-phase inverter applications. The proposed angles constraint naturally eliminates all triplen harmonics, whereas they conventionally appeared in all single-phase output voltages. The harmonic amplitude formula is developed based on the obtained angles constraint, and then modified single-phase SHE equations are defined to eliminate only specified low nontriplen harmonics. Therefore, more harmonics would be eliminated with the same switching frequency in modified SHE-PWM. Five-level voltage waveform has been opted to implement the introduced method, but it can be applied on all multilevel voltage waveforms such as seven-level with even number of angles. Unlike the conventional SHE technique, THD is analyzable in modified SHE to find optimum values for switching angles in order to control noneliminated harmonic amplitudes and minimize THD. Moreover, the cancellation of triplen harmonics empowers a single-phase inverter to supply nonlinear loads beside linear ones. Some experimental tests are accomplished using a single-phase five-level modified packed U-cell (MPUC) inverter. Results are discussed to prove the excellent performance of a single-phase MPUC inverter under both normal and harmonic loads and accurate elimination of determined triplen and nontriplen harmonics by applying the presented angles constraint. [ABSTRACT FROM AUTHOR]

This paper proposes a vector control strategy for independent control of two permanent-magnet synchronous motors (PMSMs) using a single four-leg inverter (4LI). An expanded two-arm modulation to obtain a balanced three-phase output voltage is described. This paper also proposes a method to compensate for the fluctuations in the neutral point voltage of two split capacitors in the dc link. The experimental results show that independent speed and position control of two PMSMs can be achieved using a single 4LI with the proposed vector control method. [ABSTRACT FROM AUTHOR]

Three optimized pulse-width modulated (PWM) techniques for the overmodulation region of two-level inverter-fed ac drives are introduced and investigated from the harmonic loss minimization point of view. The optimization is elaborated for the lowest loss-factor, which is proportional to the square of the root mean square value of current harmonics. The loss-factors are computed for different switching numbers as the function of the motor fundamental voltage. It is shown that, with respect to the motor heating and torque ripples, the acceptable drive condition can be guaranteed by a relatively low value of an inverter switching frequency up to 96%–97% of maximal possible motor voltage. Furthermore, it is shown that the so-called three-vector methods have considerably better performance in the lower part of the overmodulation region than the so-called two-vector method for the same number of switching. The performance of the techniques is compared with other existing PWM techniques. This paper discusses the implementation details of the proposed optimal PWM techniques. The theoretical results are verified by experimental and simulation tests. [ABSTRACT FROM AUTHOR]

This paper presents a new compact three-phase cascaded multilevel inverter (CMLI) topology with reduced device count and high-frequency magnetic link. The proposed topology overcomes the predominant limitation of separate dc power supplies, which CMLI always require. The high-frequency magnetic link also provides a galvanic isolation between the input and output sides of the inverter, which is essential for various grid-connected applications. The proposed topology utilizes an asymmetric inverter configuration that consists of cascaded H-bridge cells and a conventional three-phase two-level inverter. A toroidal core is employed for the high-frequency magnetic link to ensure compact size and high-power density. Compared with counterpart CMLI topologies available in literature, the proposed inverter has the advantage of utilizing the least number of power electronic components without compromising the overall performance, particularly when a high number of output voltage levels is required. The feasibility of the proposed inverter is confirmed through extensive simulation and experimentally validated studies. [ABSTRACT FROM AUTHOR]

A constant switching frequency hysteresis controller based on current error space vector (CESV) for two-level voltage source inverter fed induction motor (IM) drive is proposed in this paper. Here the stator voltages along the α- and β-axes are estimated using current error information and steady-state model of IM. Estimated stator voltages, switching dwell times, and instantaneous voltage error vectors are used in the online hysteresis boundary computations. The steady-state CESV boundaries and the phase voltage normalized harmonic spectrum of the proposed hysteresis controller at different speeds resembles that of a constant switching frequency voltage-controlled bus clamping pulse-width modulation-based drive. The proposed controller exhibits adjacent voltage vector switching, fast dynamic response under transient conditions, and has a simple controller implementation. The superior performance of the proposed controller is simulated using MATLAB/Simulink platform and experimentally verified on a three-phase 2.2 kW IM drive. [ABSTRACT FROM AUTHOR]

The effect of inverter dead time on the inverter output voltage is well studied in the literature. This paper studies the effect of the dead time on the inverter input current. An expression for the switching-cycle-averaged inverter input current including the dead time effect is derived, which shows the dead time effect to primarily result in a reduction in the average value of the inverter dc input current. The effect of dead time on the input current is incorporated into the dc-link dynamic model of a diode-bridge-rectifier (DBR) fed voltage source inverter (VSI). A switching-cycle-average model of a DBR-VSI-fed induction motor is proposed, which considers the effect of dead time on both the ac output voltage and dc input current of the VSI. The proposed average model is used to study the light-load instability phenomenon in a 100-kW open-loop motor drive. The proposed model is shown to predict the region of oscillatory behavior (i.e., region exhibiting light-load instability) with better accuracy than existing average models. The proposed model also accurately predicts the dc-link voltage swing at such oscillatory operating points. While being comparable in accuracy in predicting the system dynamics, the proposed model is much more computationally efficient than the state-of-the-art switching model. The validity of the proposed average model is also confirmed by experimental measurements on a 100-kW induction motor drive. [ABSTRACT FROM AUTHOR]

This paper presents an optimized topology for a \text3-\phi three-level inverter with complete elimination of common-mode voltage (CMV). The proposed multilevel inverter (MLI) configuration is realized by modifying a T-structure \text3-\phi inverter. The proposed configuration is an optimized solution with respect to the pulse-width modulation strategy used for CMV elimination. The given three-level inverter structure uses only 16 power semiconductor switches, which is much lower than the existing configurations. A reduced number of power semiconductor devices results in a diminished number of driver circuits, less installation space, and low cost. Further, due to the complete elimination of CMV, the proposed MLI is free from issues such as electromagnetic interference and leakage current with a reduction in filter requirement. The presented topology is also compared with other existing topologies to prove its advantage. It is an optimized solution with respect to the dc bus voltage requirement and the total voltage rating of the devices or the components used in the system. Simulation and experimental results are presented to confirm the capability of the proposed MLI. [ABSTRACT FROM AUTHOR]

As a result of dead-time, device on-state voltage drop, dc bus voltage measurement error, etc., volt-second errors degrade precise control of torque and flux linkage, particularly at low speeds. This is true for deadbeat-direct torque and flux control, which directly manipulates the volt-second vector sourced by inverters, as well as for indirect field oriented control drives. This paper introduces a real-time sensing scheme to measure the motor terminal volt-second vectors for each switching period with negligible phase lag. Based on the volt-second sensing, a model reference adaptive system-based approach is developed to decouple the volt-second errors from inverter nonlinearity, and dc bus voltage fluctuation and measurement error. By delivering an accurate volt-second vector for each switching period, torque and flux control accuracy, self-sensing performance, and parameter estimation accuracy are significantly enhanced. [ABSTRACT FROM AUTHOR]

A method for the seamless transition of three-phase inverters switched between grid-tied and stand-alone modes of operation is presented in this paper. In this method, only the inverter current and voltage sensors are utilized, and no control over the grid-side static transfer switch is needed. The presented method contains two strategies for grid-tied-to-stand-alone and stand-alone-to-grid-tied transitions. In the stand-alone-to-grid-tied transition strategy, a novel algorithm is presented for estimating the grid angle nearly instantaneously, which allows the three-phase inverter to respond very quickly if the grid and point-of-common-coupling voltages are out of phase. This fast response allows the inverter to effectively eliminate the transient overcurrent that would normally occur if it was connected to the grid without first being synchronized. The fast response also allows the inverter to return to normal operation very quickly after such an event. The strategy for the seamless transition from grid-tied to stand-alone mode is also presented. These strategies have been verified through experiments, and the results are presented in this paper. [ABSTRACT FROM PUBLISHER]

Computational burden is a major hurdle for practical implementation of finite-state predictive torque control (FS-PTC) of motor drive fed by a multilevel inverter. One of the reasons of computational complexity is that all voltage vectors are evaluated for prediction and actuation. This paper proposes a reduced number of voltage vectors for the prediction and actuation, which are called prediction vectors in FS-PTC. The performance is investigated for a three-level neutral-point clamped inverter fed motor drive in terms of torque and flux response, stator current total harmonic distortion, robustness, average switching frequency, and neutral-point voltage variation. The number of prediction vectors is reduced based on the position of stator flux and the deviation in stator flux from its reference. Experimental results confirm that the computational burden could be reduced by 38%, while the dynamic performance is comparable with the conventional all voltage vectors based FS-PTC. [ABSTRACT FROM AUTHOR]

This paper identifies possible topological reconfigurability of a T-type inverter for direct torque controlled (DTC) induction motor drives when an open-switch fault occurs. In open-switch fault, inverter current path is different than normal path. This causes undesirable inverter switching states. Since DTC is based on a voltage vector selection criterion, open-switch fault causes ambiguous torque control. Analysis of DTC drive under two different inverter open-switch fault conditions viz. half-bridge and neutral-point switch fault are presented. The operation of the inverter in DTC mode against faults is achieved by simple topological reconfiguration. [ABSTRACT FROM PUBLISHER]

In this paper, a novel space-vector pulse-width modulation (PWM) scheme for reducing the common-mode voltage (CMV) in the three-phase five-level active neutral-point clamped (5L-ANPC) inverter is proposed, where only the 55 selected voltage vectors among the entire 125 that produce low values of the CMV are utilized. This PWM scheme can significantly reduce the CMV without the increase of switching losses and total harmonic distortion of the output voltages. With the 55 selected voltage vectors, the inverter can still operate up to the maximum modulation index. In addition, the capacitor voltages are controlled by redundant switches of the 5L-ANPC inverters. It has been shown that the peak value of the CMV is decreased to one-twelfth of the dc-link voltage from the simulation and experimental results. [ABSTRACT FROM PUBLISHER]

Common-mode voltage (CMV) in voltage-source inverters (VSIs) has been well defined and is frequently referred to in the literature. While often referred to, there is no real consistency with respect to how the CMV properties of an individual modulation scheme are evaluated, lacking tools to assess the relative merits or disadvantages of a certain topology or modification of a control scheme. The way that it is analyzed is still mostly a matter of the different authors' foci. In this paper, we propose a metric for the analysis of the CMV, aiming to fill the aforementioned gap. Thereby, the CMV in VSIs is quantified by the number of possible levels and the step sizes between different levels, as well as the respective frequencies of occurrence. The first two are given by the number of levels and the number of phases of the inverter. Depending on the modulation (control) schemes, all possibly available levels or a few of these levels are present in the CMV. We illustrate the use of the tool by applying it to thoroughly study the CMV properties intrinsic to the topologies of multilevel multiphase single- as well as double-ended diode-clamped VSI drive systems. As part of this analysis, we uncover new relationships concerning the existence of zero CMV level. Furthermore, we exemplarily apply the developed tool to the assessment of the CMV properties of selected pulse width modulation (PWM) control schemes and translate the findings into an interpretation of the endangerment of a given drive to suffer damage from inverter-induced bearing currents. The theoretical findings are supported by measurements. This paper also reviews the literature on CMV in multilevel multiphase VSI systems. With the proposed metric in mind, the CMV being mostly discussed as an element of different foci becomes even clearer, confirming again the need for the development of such a tool. [ABSTRACT FROM AUTHOR]

The conventional current-source inverter has two major problems: unidirectional power flow and voltage boost operation, which make it impossible to be used in many applications, such as hybrid electric vehicles and general-purpose variable-speed motor drives. Z-source inverters (ZSIs) can solve both problems. Quasi-ZSIs (qZSIs) were recently proposed as an important improvement to traditional ZSIs. Besides the advantages inherited from ZSIs, qZSIs also have several of their own merits. This paper presents a comprehensive study on the new features of current-fed qZSI, including the advantageous buck–boost function, improved reliability, reduced passive component ratings, and unique regeneration capability. The current-fed qZSIs are bidirectional with an additional diode, unlike the voltage-fed ZSI that needs a switch to achieve bidirectional power flow. A modified space vector pulse-width-modulation method is proposed, and the available operating regions for motoring and regeneration operation are analyzed in this paper. Since the current-fed qZSI has the same operation as the current-fed ZSI, many results of this paper are also applicable to the current-fed ZSI. A reverse-blocking insulated-gate bipolar-transistor-based current-fed qZSI prototype was developed in the laboratory. Simulation and experimental results are shown to verify the theoretical analysis. [ABSTRACT FROM PUBLISHER]

In this paper, a novel multilevel dc–ac inverter is proposed. The proposed multilevel inverter generates seven-level ac output voltage with the appropriate gate signals’ design. Also, the low-pass filter is used to reduce the total harmonic distortion of the sinusoidal output voltage. The switching losses and the voltage stress of power devices can be reduced in the proposed multilevel inverter. The operating principles of the proposed inverter and the voltage balancing method of input capacitors are discussed. Finally, a laboratory prototype multilevel inverter with 400-V input voltage and output 220\ \textV\text{rms}/2\,{\text{kW}} is implemented. The multilevel inverter is controlled with sinusoidal pulse-width modulation (SPWM) by TMS320LF2407 digital signal processor (DSP). Experimental results show that the maximum efficiency is 96.9% and the full load efficiency is 94.6%. [ABSTRACT FROM AUTHOR]

This paper proposes an integrated field and armature current control strategy for a variable flux reluctance machine (VFRM) with an open-winding topology. By using an open-winding inverter, the field and armature currents can be injected into a single coil as a sinusoidal current biased by the dc offset rather than the separated field and armature windings. The integrated current control can reduce the copper loss to half and extend the operating speed range owing to the reduction in the winding resistance. In order to utilize the zero-sequence current as a field current, a zero-vector modification technique is proposed, in which the switching-on time of the zero vectors is modified to generate the constant zero-sequence voltage between two inverters. The proposed scheme is implemented in a synchronous $dq0$-axis frame with space vector modulation. For the validation of the proposed method, a machine model of the VFRM is developed and implemented in MATLAB/Simulink. The simulation and experimental results verify that the proposed strategy can effectively reduce the copper loss and extend the operating speed range. [ABSTRACT FROM AUTHOR]

Three-level neutral point clamped (NPC) inverters exhibit a natural balancing property that can self-regulate the intermediate neutral point voltage to half the overall dc-link voltage. However, the underlying mechanisms of this process are not well understood, its performance under various load conditions has not been properly explored, and the requirements and benefits of ( $RLC$) balance booster filters to enhance the natural balancing response are not clear. This paper presents a generalized model of an NPC natural balancing process that allows these issues to be explored for various load structures and balance booster configurations (i.e., isolated wye, wye with a grounded star point, etc.). The model accurately predicts the dominant balancing time constant, identifies the harmonics that drive the balancing process, and can quantify the steady-state balance booster losses for a designed target natural balance response. Extensive simulation and experimental tests have been performed to validate the theoretical model. [ABSTRACT FROM PUBLISHER]

The advancement in power electronics has made the use of any number of phases in ac machines possible since with the inverter, any number of phase voltages can be realized as long as the corresponding inverter exists. To supply multiphase drives requires multiphase voltage source inverters (VSIs) whose output voltages depend very much on the methods of generating the pulses to turn on and turn off the inverter devices appropriately. This paper presents an analytical technique for the determination of the expressions for the modulation signals used in the carrier-based sinusoidal and generalized discontinuous pulse width modulation schemes for two-level, five-phase voltage source converters. These expressions can be used for both balanced and unbalanced phase voltages generated by any two-level multiphase inverter, in generating the required reference signals appropriately. An example of a five-phase VSI is presented to illustrate the strategy. Simulation and experimental results are presented in which a close examination shows that both results are similar for the balanced and unbalanced load voltage cases. [ABSTRACT FROM AUTHOR]

Operating a dual three-level inverter system from a single dc link circuit is an economic solution for generating five-level output voltage waveforms and to double the output power compared to a single three-level inverter. Such an inverter system is used for feeding a drive motor with open stator windings. A mechanism is then required to reduce the common-mode voltage components of the motor voltages. This paper describes an offline optimization method that minimizes both the harmonic distortion of the motor currents and the common-mode voltage components. The optimization permits reduction of the switching frequency to a very low value of 200 Hz without compromising the harmonic distortion. High performance operation of the drive system at low switching frequency is experimentally demonstrated. [ABSTRACT FROM PUBLISHER]

This paper demonstrates improved performance of a three-phase voltage source inverter (VSI) when digital multisampled space vector modulation is used. The modulator and the inverter controller are implemented entirely using a field-programmable gate array platform, thus achieving increased bandwidth with respect to a typical digital signal processor or microprocessor-based controller. Increased controller bandwidth results in lower output voltage harmonic distortion in the frequency range above the fundamental and below the switching frequency. Experimental validation is presented together with the analysis carried out using a state space model of a VSI with an output LC filter. [ABSTRACT FROM AUTHOR]