Search

The number of applicable carrier-based pulsewidth modulation (PWM) patterns increases with the growth of output levels in scalable multilevel topologies, such as active-neutral-point-clamped (ANPC) converters. Therefore, it is hard to optimize PWM for such topology, especially with large output levels. In this paper, a simplified and modular carrier-based PWM design approach for multilevel ANPC converters is proposed. Inspired by the decomposition theory, the topology decomposition is introduced in this paper to decompose an N-level ANPC converter into low-level subtopologies. Then, the complete set of applicable PWM patterns is derived based on ANPC operation principles, which makes it possible to optimize the performance based on the various requirements in applications. Meanwhile, the carrier-based PWM is implemented through the utilization of subtopologies with low-level modulation schemes, such that the design process of carrier-based PWM is greatly simplified and modularly realized. Both the complete PWM patterns and PWM design examples with experimental results of several ANPC converters are provided to show the feasibility and modularity of the proposed method. [ABSTRACT FROM AUTHOR]

This paper proposes a single-phase ac–dc–ac converter composed of a transformer and two three-leg converters connected in series. The proposed converter allows to supply the load with a voltage with constant amplitude and frequency, and to operate with the grid current with low harmonic distortion and high power factor. In addition, the converter can be used to mitigate fundamental overvoltage and voltage harmonics at the grid. The system model, regions of operation, a power flow analysis, and a method to regulate the dc-link voltages using the voltage vector redundancies are given. In the first version of this paper, two pulsewidth modulation (PWM) techniques (including space vector PWM) and a control system were provided. The proposed topology is compared with two conventional systems in terms of operation range, harmonic distortions, and semiconductor losses. Simulation and experimental results are provided to validate the feasibility of the system. [ABSTRACT FROM AUTHOR]

This paper presents a novel control strategy to significantly reduce the high-frequency transformer loss in a modular solid-state transformer (SST) based converter system. The modular SST design is based on an ac–dc power-electronic building block comprised of an H-bridge at the ac input and a bidirectional soft-switching isolated dc–dc converter with a medium-voltage insulated high-frequency transformer. The ac terminals of input H-bridges are connected in series and directly coupled to the medium-voltage ac line, while the output dc terminals are all connected in parallel at a low voltage. The key innovation described in this paper, without sacrificing the output performance, is the control scheme that reduces core and winding losses associated with the dc–dc resonant stage by turning off the selected dc–dc converters in synchronism with the line voltage. The prototype for the test described in this paper is based on a modular SST where each module is rated at 50 kVA, with a 200 kHz transformer using 1.7 kV silicon carbide discrete mosfets, but the described control concepts are more broadly applicable to similar topologies. [ABSTRACT FROM AUTHOR]

This paper provides an experimental discussion on a real-time real-power emulator that plays an important role in achieving a total test of medium-voltage, high-power, high-speed induction motor drives. The use of the emulator brings cost and time savings to the test. The test bench including the emulator is characterized by connecting two modular multilevel double-star chopper-cell (DSCC) converters connected in a front-to-front way. This paper designs, builds, and tests a 400- ${\rm V}_{\rm dc}$ , 10-kW downscaled test bench. It mainly consists of the following two identical DSCC converters: 1) one DSCC converter is used as an inverter under test; and 2) the other as a real-time real-power high-fidelity emulator. Experimental waveforms confirm that the emulator can reproduce electrical and mechanical operating performance of the three-phase 200-V, 10-kW, four-pole, 9000-r/min induction motor loaded with a centrifugal compressor. [ABSTRACT FROM AUTHOR]

This paper presents a neutral-point deviation and ripple compensating control method applied to a three-level neutral-point-clamped (NPC) converter. The neutral-point deviation and its harmonic components are analyzed with a focus on the average current flowing through the neutral-point of the dc link. This paper also proposes a control scheme compensating for the neutral-point deviation and dominant harmonic components under generalized unbalanced grid operating conditions. The positive and negative sequence components of the switching functions and ac input currents are employed to accurately explain the behavior of three-level NPC converter. Simulation and experimental results are presented to verify the validity of the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents the flexible dc capacitor voltages balancing control method for star-connected cascaded H-bridge converters. In this paper, the power flows are analyzed by investigating all the converter's control freedoms. Based on the analyses, users can accomplish the dc capacitor voltage balancing with both negative-sequence current and zero-sequence voltage. These two kinds of control options are further integrated together with the defined weighting factor $K$. The low-voltage ride-through operation of a proposed control method is also discussed in this paper. The control method is verified with a 220-V 1-kVA static synchronous compensators based on the star-connected cascaded H-bridge converters, and the experimental test results show that all the dc voltages are well regulated at the commanded value with different weighting factor $K$. [ABSTRACT FROM AUTHOR]

A drive train system (DTS) powered by an ideal voltage source and driving a permanent-magnet synchronous motor (PMSM) is discussed in this paper. A two-level three-phase voltage source inverter is used as a means of power conditioning. This converter is not equipped with any harmonic filters on neither the ac nor the dc side. The mechanical part of the DTS is modeled as a double oscillator according to a drive train in an electric vehicle (EV). Various inverter modulation schemes are applied, namely, a single-phase hysteresis scheme, two-space vector-based hysteresis control schemes, for one, a stator aligned hysteresis and for another, a rotor aligned hysteresis, a modulation scheme based on pulsewidth modulation (PWM), such as sinusoidal modulation (including zero-sequence components) and space-vector pulsewidth modulation (SVPWM). The hysteresis-based pulsing methods are nondeterministic and build a current controller in their structure by nature. The other pulsing methods are deterministic due to their underlying PWM and require a separate control unit. The influence of these modulation schemes on the performance of the DTS is determined by assessing the level of inverter generated harmonics flowing to the PMSM and to the tires [downforce, (mechanical part)] as well as the resulting switching frequency (electrical part). The simulated results presented in the paper indicate that the pulsing frequency can be reduced by means of the hysteresis controller. In addition, the dispersion of the harmonic energy of the inverter generated spectrum partly compensate the absence of filters. [ABSTRACT FROM PUBLISHER]

This paper investigates a method to increase fuel economy of motors for an electric vehicle (EV) traction system. The low-torque region of an EV motor is frequently used in everyday urban driving and in fuel economy measurement. Pulsewidth modulation (PWM) carrier harmonic iron loss accounts for a high percentage of total loss for EV motors in this region. This paper reveals the relationship between phase current and carrier harmonic iron loss for a permanent-magnet synchronous motor (PMSM) in the low-torque region. Thus, a novel carrier harmonic loss reduction technique is proposed and applied to two sets of three-phase windings for a concentrated winding PMSM. The loss is successfully reduced in a 70-kW EV motor as well as a two-dimensional finite-element method (2-D-FEM) calculation. The efficiency of the developed motor is calculated and compared with that of a conventional motor in the JC08 mode driving cycle. [ABSTRACT FROM PUBLISHER]

This paper presents an improved dc-link voltage balancing algorithm for a three-level neutral-point-clamped inverter by considering phase current direction. Detailed studies on the effects of change in load current direction on the dc-link capacitor voltages are presented. A maximum value of power factor is numerically derived, above which it affects the capacitor voltage balancing capability. Compared with the previously presented research work, the inputs to the space-vector pulsewidth-modulation block are the three phase currents and the difference between the two capacitor voltages. Depending on the states of the two dc-link capacitor voltages and phase current direction, redundant voltage vector sequences are selected. The selected vectors keep the capacitor voltage deviations within 5% of the total dc-link voltage. Two zero switching vectors (i.e., PPP and NNN) are also removed from all subsectors of the earlier proposed strategy, which one used to produce higher common-mode voltages. Detailed simulation and experimental results are presented in this paper for a 6.0-kW surface permanent-magnet synchronous machine. Both the simulation and experimental results show the required performance of the proposed system. [ABSTRACT FROM AUTHOR]

This paper proposes a new carrier-based modulation strategy for symmetrical cascaded multilevel converters denominated phase disposition with sorting (PDS). It deals with the issue of irregular distribution of PWM signals and power for each converter cell that occurs when using the conventional phase disposition (PD) modulation. Although some alternatives have been proposed in the literature for overcoming these problems, most of them do not consider operation of the converter under fault conditions on the power cells. Therefore, one of the contributions of the proposed PDS modulation strategy is the ability to evenly distribute the pulse signals for the converter semiconductor switches, resulting in the same power being processed by all cells, maintaining the good quality of the synthesized output voltages, even with faults in one or more power cells. In addition, it allows implementation in commercial digital signal processors, not requiring additional hardware. The good performance of the proposed modulation strategy is validated through experimental results for a three-phase symmetrical cascaded multilevel converter with three cells per phase, considering normal and faulty conditions on the power cells. [ABSTRACT FROM AUTHOR]

Unipolar-pulsewidth modulation (UP-PWM) inverter takes advantages of high power efficiency and small output chokes which is widely used in the industry. However, UP-PWM inverters cannot be used in parallel operation due to a current unbalance problem. This paper studies the current unbalance problem of paralleled UP-PWM inverters with common dc bus and ac bus. First, the problem of unbalanced inductor current is defined and analyzed. Second, a technique to eliminate unbalanced currents is proposed. The proposed current balancing technique only requires one more current sensor in an inverter module rather than changing converter topology or modulation method, which makes it possible to apply UP-PWM inverters in parallel-operation while keeping the advantages of unipolar switching. The proposed current balancing method is verified by both simulation and hardware experiment. Experimental verification is performed on two 1 kW, 400 V input, and 120 V/60 Hz output prototypes, which shows a good agreement to the analytical study. [ABSTRACT FROM AUTHOR]

The neutral-point voltage-balancing control is a critical issue of a neutral-point-clamped converter. The conventional control strategy is to inject the specific zero-sequence voltage to regulate the redundant vector, but it is unacceptable to the three-phase four-wire system. This paper provides a neutral-point voltage-balancing control by the dipolar modulation, and the control freedom of the zero-sequence voltage is flexible. Therefore, the proposed method is suitable for both three-phase three-wire and three-phase four-wire systems. Besides, the proposed method improves the control dynamic in a reactive power system. The proposed neutral-point voltage-balancing control is verified by the mathematical analysis and experimental results. The control dynamic, power loss estimation, and the output current performance are analyzed in this paper. [ABSTRACT FROM PUBLISHER]

This paper discusses and compares phase-shifted pulse-width modulation (PS-PWM) and level-shifted PWM (LS-PWM) in a modular multilevel single-delta bridge-cell (SDBC) inverter for utility-scale grid-tied photovoltaic applications. This three-phase SDBC inverter provides the capability of operating even under power-distribution imbalances not only among three clusters, but also among cascaded bridge cells in each cluster. The main focus of this research lies in analyzing the capability of operation under severe power-distribution imbalances and presenting power-balancing methods based on zero-sequence current injection, which result in an extended power-balancing capability. This paper highlights that LS-PWM is superior to PS-PWM in both power-balancing capability and harmonic performance at the ac side of the SDBC inverter when operating under power-distribution imbalances. Experimental results obtained from a three-phase 10-kW downscaled system show good agreement with those from the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper introduces a three-phase grid-connected inverter for commercial-scale photovoltaic systems. The circuit topology combines an ac-inductor-less active bridge with a parallel-connected pulsewidth modulation inverter acting as an instantaneous reactive power compensator. The active bridge, called a 120° conduction inverter, operates at a switching frequency equal to the grid frequency and outputs a 120° rectangular current, while the compensator eliminates the harmonic currents included in the rectangular current. The main advantage of this strategy is the reduction in size of the required ac inductor by a factor of 4, as well as the reduction of power losses in the switching devices. The theoretical analysis clearly shows that the compensator can synthesize a sinusoidal output current by controlling only instantaneous reactive power, thus eliminating the need for electrolytic capacitors. A 5-kW experimental setup validates the operating principle and the control method of the proposed inverter and exhibits an inverter efficiency as high as 99.2% with Si superjunction mosfets. [ABSTRACT FROM AUTHOR]

In this paper, the pulsewidth modulation switch method was used to investigate the effect of the transformer leakage inductance on the small-signal model in isolated full-bridge converter. A galvanic isolated hard-switching full-bridge converter that operates in constant-current mode is analyzed, confirming that leakage inductance significantly affects the small-signal model, and the influence of leakage inductance can be equivalent to a resistance in series with the converter's output LC filter just as that in phase-shifted full-bridge converter. However, the same leakage inductance in these both converters will lead to different equivalent resistance due to different operating principles. Results of the modified model, simulations, and the experiments are compared to verify the correctness of the model. Moreover, this paper also shows that the Norton equivalent circuit of the charger operates in constant current mode, which can be used to estimate the dynamic behavior of the system. [ABSTRACT FROM AUTHOR]

This paper introduces a compensation strategy to deal with both current and voltage measurement errors in the three-phase pulsewidth modulated rectifier system. The dc offset and scaling errors in the voltage and current measurements cause the injection of undesired dc and unbalanced currents into the three-phase input current and subsequently lead to voltage ripple at the dc output voltage. This paper proposes a compensation scheme for current measurement error where the dc offset and scaling errors in the current measurement are estimated from the characteristic of the dc output voltage ripple combining with simple band-pass and low-pass filters. Meanwhile, an advanced current controller designed with a proportional integral plus two resonant controllers tuned at the fundamental grid frequency $({{\omega _s}})$ and $2{\omega _s}$ in the synchronous (d–q) reference frame is suggested to reject the impact of the dc offset and scaling errors in the voltage measurement. The proposed compensation method is developed without the need of extra hardware circuit, sensor, or precise information of system parameters so that it can be considered as more cost-effective and robust solution. The effectiveness of the proposed solution is verified by experimental results. [ABSTRACT FROM AUTHOR]

The switching speeds of next-generation power semiconductor devices, such as those made of silicon carbide and gallium nitride are roughly ten times those of conventional devices (e.g., silicon insulated-gate bipolar transistors). This increases the frequency range of the electromagnetic noise accompanying the switching operations of pulsewidth modulated (PWM) converters and worsens the influence of radiated noise. The authors have previously proposed an active common-mode filter (ACF) that reduces the radiated noise from the power cables connected to a PWM converter and evaluated its effect in reducing radiated noise by using a function generator as a common-mode (CM) noise source. In this paper, the ACF is applied to a motor drive system fed by a three-phase PWM inverter, and the attenuation characteristics of the CM voltage are evaluated. To avoid saturating the ACF, the combination of an active common-noise canceller and the ACF is discussed. The experimental results show that the system constructed in this paper can suppress the CM voltage produced by the PWM inverter over a wide frequency range from 100 to 100 MHz. [ABSTRACT FROM AUTHOR]

Induction motor loss segregation and efficiency measurement requires loading dynamometers and other equipment, such as a variable voltage sinusoidal power supply. These are expensive and not often available even when a loading device is accessible. Variable frequency drives are now widely used for operating induction machines and are more widely available and less expensive. However, their use in place of a fixed frequency sinusoidal power supply to directly measure machine efficiency is intriguing, but inherently challenging due to the pulsewidth modulation (PWM) output voltage. This paper presents some investigations for using variable frequency drives to perform IEEE 112B and IEC 60034-2-1 tests. The use of the drive, the measurement criteria, and procedures are reported and discussed. The results presented demonstrate the feasibility of the proposed concept for measuring machine efficiency with a PWM power source. [ABSTRACT FROM AUTHOR]

Grid-interactive inverters allow distributed generation units to provide various ancillary services in microgrids. As the linear modulation region of inverters is restricted by the dc-bus voltage, providing ancillary services may drive the fundamental positive-sequence inverter voltage to the overmodulation region. Therefore, to operate in the linear modulation region the maximum active- and reactive-power of the inverter may have to be reduced unless pulsewidth modulation (PWM) references are adjusted. In this paper, an atypical PWM method is proposed for maximizing dc-bus utilization of grid-interactive two-level voltage source inverters (2L-VSI) providing ancillary services. Two important ancillary services, i.e., negative-sequence compensation and harmonic compensation are considered in this paper. The proposed method increases the maximum active- and reactive-power that a 2L-VSI can deliver when providing ancillary services by injecting a common-mode component in the references computed based on instantaneous reference magnitudes. The validity of the proposed technique is verified through simulation, as well as experimental data obtained using a 208-V three phase grid-connected 2L-VSI. [ABSTRACT FROM AUTHOR]

This paper presents the direct compensation of the switching interval error of the effective voltage vectors by the dead time of a pulsewidth modulation voltage source inverter (PWM-VSI). The output voltages of a three-phase PWM-VSI are distorted and have voltage errors from the dead time to avoid the shoot-through of inverter arms and the time delay of the gate drive. Voltage distortion increases the harmonics of the output voltages and decreases control performance. This paper presents a simple and direct compensation technique to solve this problem in a three-phase VSI. The practical switching output voltages are determined by the dc-link voltage, the switching signals of each phase, the dead time, the time delay, and the current polarities of each phase. For these reasons, output voltage errors are not constant. In order to analyze the dead-time effect in the actual switching voltages of each phase, the practical switching voltages in a sampling period of a space vector PWM (SVPWM) method are calculated according to the current polarity. In the calculation, the dead time, the time delay of devices, and the voltage drops on power devices are included to consider nonlinear voltage distortion. From these practical switching voltages during the switching intervals in a sampling period, the average output voltages of each phase can be derived, and the output voltage errors between the voltage commands and the average output voltages of each phase are obtained. The SVPWM switching intervals of each phase can be derived by the average output voltages that are calculated according to the current polarity and nonlinear voltage distortion to compensate for the output voltage errors. With the simple detection of the current polarity, the practical errors of the switching intervals of each phase can be compensated by the addition of the compensated switching time. Simulation and experimental results validating the proposed compensation method are presented in this paper. [ABSTRACT FROM AUTHOR]

This paper provides an intensive discussion on analysis, simulation, and experiment of a back-to-back (BTB) systemunifying two modular multilevel cascade converters based on double-star chopper cells (MMCCs-DSCCs). Each of the twoDSCCs connected back-to-back consists of multiple cascaded chopper cells and a center-tapped inductor per leg. Lowvoltage steps bring significant reductions in harmonic voltage and current to the BTB system. Neither dc-link capacitornor voltage sensor is required for regulating the dc-link voltage and controlling the dc-link current. A three-phase200-V, 10-kW, 50-Hz downscaled BTB system with phase-shifted PWM is designed, constructed, and tested to verify itsoperating principles and performance. Analytical, simulated, and experimental results agree well with each other insteady and transient states. Experimental waveforms confirm the effectiveness of a self-starting/restartingprocedure. [ABSTRACT FROM AUTHOR]

This paper presents a modular push–pull PWM converter (MPC) for a battery energy storage system, which is intended for grid connections to medium- or high-voltage power systems. The converter per phase consists of a center-tapped transformer and two arms based on a cascade connection of multiple bidirectional PWM chopper-cells with floating dc capacitors. This paper discusses the operating performance and control method of the MPC, focusing on voltage balancing of all the floating dc capacitors. Moreover, a comparison is made between the MPC and a modular multilevel converter (MMC), under an assumption that both are used as the same battery energy storage system. The validity of the operating performance and control method is confirmed by both computer simulation using the “PSCAD/EMTDC” software package and experiment using a three-phase, 200-V, 5-kW downscaled model. [ABSTRACT FROM PUBLISHER]

A modified-virtual-space-vector-based dc-link voltage balancing strategy is proposed in this paper for a three-level inverter. In the proposed strategy, the summation of the three-phase currents for virtual vector needs not to be zero and it also keeps the two capacitor voltages balanced with wider range of load variations. The duty cycles for all the power switches are also derived in this paper using a nearest three-voltage vector scheme. Due to the reduced use of the medium voltage vectors, the proposed control strategy can considerably decrease the neutral-point voltage fluctuation for lower power-factor-based loads as well. Detailed simulation and experimental studies are also carried out to show the effectiveness of the proposed system with a dc-link voltage balancing strategy with permanent magnet synchronous machine. Voltage and current harmonic distortions are also presented with change in modulation index. A Dspace-based real-time operating system is used for real-time implementation with a 6.0-kW surface permanent magnet synchronous motor. [ABSTRACT FROM PUBLISHER]

A low-order harmonic pulsating torque is a major concern in high-power drives, high-speed drives, and motor drives operating in an overmodulation region. This paper attempts to minimize the low-order harmonic torques in induction motor drives, operated at a low pulse number (i.e., a low ratio of switching frequency to fundamental frequency), through a frequency- domain (FD) approach as well as a synchronous reference frame (SRF) based approach. This paper first investigates FD-based approximate elimination of harmonic torque as suggested by classical works. This is then extended into a procedure for minimization of low-order pulsating torque components in the FD, which is independent of machine parameters and mechanical load. Furthermore, an SRF-based optimal pulsewidth modulation (PWM) method is proposed to minimize the low-order harmonic torques, considering the motor parameters and load torque. The two optimal methods are evaluated and compared with sine-triangle (ST) PWM and selective harmonic elimination (SHE) PWM through simulations and experimental studies on a 3.7-kW induction motor drive. The SRF-based optimal PWM results in marginally better performance than the FD-based one. However, the selection of optimal switching angle for any modulation index $(M)$ takes much longer in case of SRF than in case of the FD-based approach. The FD-based optimal solutions can be used as good starting solutions and/or to reasonably restrict the search space for optimal solutions in the SRF-based approach. Both of the FD-based and SRF-based optimal PWM methods reduce the low-order pulsating torque significantly, compared to ST PWM and SHE PWM, as shown by the simulation and experimental results. [ABSTRACT FROM AUTHOR]

Constant-volts-per-hertz induction motor drives and vector-controlled induction motor drives utilize pulsewidth modulation (PWM) to control the voltage applied on the motor. The method of PWM influences the pulsations in the torque developed by the motor. A space-vector-based approach to PWM facilitates special switching sequences involving the division of active state time. This paper proposes a space-vector-based hybrid PWM technique, which is a combination of the conventional and special switching sequences. The proposed hybrid PWM technique results in a lower peak-to-peak torque ripple than conventional space vector PWM (CSVPWM) at high speeds of an induction motor drive. Furthermore, the magnitude of the dominant torque harmonic due to the proposed hybrid PWM is significantly lower than that due to CSVPWM at high speeds of the drive. Experimental results from a 3.75-kW sensorless vector-controlled induction motor drive under various load conditions are presented to support analytical and simulation results. [ABSTRACT FROM AUTHOR]

Dual-comparison one-cycle control for the bidirectional power flow in single-phase grid-connected converters is proposed in this paper. Advantages of dual-comparison one-cycle control when compared to conventional one-cycle control is that it does not give any steady-state dc offset, no light-load instability, and implements unipolar pulsewidth modulation without having to sense the grid voltage. Addition of a fictitious current term, which is generated from the gating signal of one of the active devices, using a bandpass filter, enables the bidirectional power flow. The quality factor of the bandpass filter is shown to impact the total harmonic distortion in current, fundamental displacement angle, and steady-state dc offset. The optimal value of a quality factor, obtained with aid of simulations, gives a superior performance. The current drawn or injected into the grid is seen to lag the grid voltage. The reason for a nonunity displacement power factor is analyzed and a compensation to achieve a unity displacement power factor is also proposed in this paper. Detailed simulation and experimental studies are carried out to validate the proposed control and the high performance that can be obtained. [ABSTRACT FROM AUTHOR]

Paralleled inverters are not only a suitable approach to increase the power capacity, but also have the capability of common mode voltage (CMV) reduction, or even elimination. The original zero CMV modulation scheme for paralleled inverters suffers from the current jump problem in phase-leg currents. This current jump phenomenon amplifies the peak values of differential-mode circulating current (DMCC) and zero-sequence circulating current (ZSCC), which is adverse for the design of coupled inductor and common-mode inductor. This paper introduces the modified modulation scheme, which can keep volt-seconds balance in whole fundamental period and mitigate the current jump in phase-leg currents. In addition, the reduction effect of the DMCC and ZSCC can be achieved. To verify the analysis, both the simulation and experimental results are presented, which validates the proposed methods and show that they are beneficial for DMCC and ZSCC reduction. [ABSTRACT FROM AUTHOR]

Multilevel converters with floating capacitors (FCs) are widely applied in recent years in a wide range of industrial applications from high-voltage direct current systems to high power drives. However, some FC topologies lack complete FC voltage balancing capability due to the inherent topology limitation or the insufficient switching state for capacitor balancing. This will result in large ripples on capacitors at low frequency (such as fundamental frequency), limiting their performance and application, particularly, when the fundamental frequency is very low in low-speed drive operations. Typical examples of those multilevel converters are modular multilevel converters (MMC), nested neutral-point-clamped (NNPC) converter, etc. In order to improve the FC balancing for this kind of multilevel converters, this paper proposes a carrier-based pulse-width modulation (PWM) method, named stair edge PWM method. This method can obtain sufficient redundant switching states for FC voltage balancing by producing multiple levels in one PWM period. The FC voltage balancing is thus achieved at switching frequency, which can greatly reduce the capacitor voltage ripple and therefore enable the use of much smaller FCs. Meanwhile, the voltage stress on each device and low $dv/dt$ feature are still the same as the normal multilevel operation, reserving two of the most salient features of multilevel converters. The proposed method also features much simpler and easier implementation compared with space-vector-based approaches, particularly when high-level converters are considered. An application example using a four-level NNPC converter is provided in this paper. The effectiveness and performance of the proposed method are verified by both simulation and experiment. [ABSTRACT FROM AUTHOR]

In this paper, the characteristics of ripple current of a multimegawatt drive system fed by a pulse-width modulation (PWM) inverter are investigated. Based on the investigation, a novel PWM scheme is devised to reduce the switching loss of the inverter under an identical amount of torque ripple of a motor. The proposed PWM is composed of two parts. The first is minimum torque ripple PWM (MTRPWM), which is optimized in terms of the minimum torque ripple in high modulation index (MI). The second determines the minimum switching frequency while holding the average torque ripple less than the allowable value under various operating conditions. It is termed reduced switching frequency PWM (RSFPWM). Consequently, by simply changing the PWM method from conventional fixed switching frequency continuous PWM to the proposed PWM, MTRPWM and RSFPWM, simulation results show that the switching loss of the inverter driving a 3.5 MW induction motor is reduced to 51.6% while keeping the torque ripple in the allowable boundary, where MI is 1.12. This approach is applied to small-scale experimental sets consisting of an interior permanent magnet synchronous machine (IPMSM) motor-generator set, and an induction machine MG set in an effort to verify the validity and feasibility of the proposed method. Based on these experimental results, the cost indexes of the IPMSM and the induction machine, as defined in this paper, decrease by up to 66% and 77%, respectively, when the proposed method is applied when MI is 1.12 compared with the outcome with the conventional PWM. [ABSTRACT FROM AUTHOR]

This paper presents a novel single source fed isolated gate driver circuit based on the dual-forward converter topology. The two forward converters are paralleled at the secondary side to achieve 0%–100 $\%$ duty cycle range together with galvanic isolation. The gate driver switching frequency is independent of the main pulse-width modulation frequency (PWM). As a result, the gate driver switching devices and magnetics are designed for high frequencies independent of the main PWM frequency. At high frequencies, problems of resonance due to parasitics become significant. This paper discusses this problem and proposes a novel solution to mitigate it. In addition, this paper also presents a novel solution and circuit to produce negative gate pulse for miller clamp. The proposed circuit can be used for any application, irrespective of switching frequency, thus making it a wide band generalized gate driver. The circuit is analyzed and verified experimentally. [ABSTRACT FROM PUBLISHER]

High-resistance ground (HRG) systems have gained popularity in process applications due to their ability to continue operation after a single line-to-ground fault and to limit the escalation of a single line-to-ground fault to a multiphase event. Part I of the companion paper has set the guidelines for designing safe and reliable HRG systems on industrial power systems used with linear loads and the effect of increased line–ground voltage stress on motor loads during fault conditions. However, literature on characteristics and pitfalls of HRG systems when used with nonlinear power converter systems is limited. Part II investigates anomalies of HRG systems used with nonlinear power converters such as neutral voltage shifting, increased line–ground transient fault voltages for both motor and ac source terminals and their voltage compatibility issues, increased neutral grounding resistor power dissipation, susceptibility of ground fault sensing equipment to nuisance tripping, and dc-bus voltage resonance on faults. Part II also investigates HRG zero-sequence fault current characteristics and paths observed under various fault locations in a common ac or a common dc-bus pulsewidth-modulated adjustable speed drive (ASD) system. Part II concludes with a summary of application guidelines when using ASD HRG systems. [ABSTRACT FROM PUBLISHER]

Current measurement and pulsewidth modulation (PWM) are critical components of modern current-controlled voltage source inverters. Current measurements enable accurate and robust closed-loop control of current, while PWM enables the efficient high-bandwidth regulation of the voltage. These two components do not operate independently, however. The synthesized voltage from PWM, a sequential series of discrete voltage levels, from a predefined finite set of possible levels, is only equivalent to the desired voltage on an average basis. As a result, the response of the electrical current to this synthesized voltage deviates from the response to the desired voltage. This deviation from the desired response, when combined with the standard synchronous sampling method, results in current measurement errors. This paper will present an analytical derivation of this current response deviation. This can be used to model the current measurement errors. A better understanding of this phenomenon will result in better design and control of power converter systems. The analytical work will be evaluated and verified using simulations and experimental measurements. [ABSTRACT FROM PUBLISHER]

This paper presents the voltage- and current-limited operation of an interior permanent magnet synchronous machine (IPMSM) using deadbeat direct torque and flux control (DB-DTFC). A commanded air-gap torque and stator flux can be achieved by the end of each pulsewidth modulation (PWM) period using DB-DTFC. However, it may take several PWM periods to achieve a desired air-gap torque that is physically infeasible in one step due to voltage limits. In that case, the torque and flux command trajectories operating over multiple periods can be developed to achieve deadbeat torque and flux response for every PWM period. The torque and flux command trajectories can be developed in different shapes depending on desired objectives. In this paper, a minimum-time ramp trajectory method is proposed to achieve both simple real-time implementation and fast and stable transient dynamics of IPMSM drives. Simulation and experimental results for the minimum-time ramp trajectory method for an IPMSM drive are presented. [ABSTRACT FROM AUTHOR]

It is expected, the growing demand for supercapacitor energy storage system (ESS) in which thousands of supercapacitor cells are connected as a stack for meeting the desired load power. The lifetime of ESS dramatically depends on the operating thermal effects of individual cells. In this paper, a temperature-suppression charging strategy is proposed for supercapacitor ESS to maximize its lifetime. First, the charging current and equivalent series resistance (ESR) construct the supercapacitor thermal model, and the ESR represents the degradation degree of the supercapacitor. Second, the maximization of system lifetime and equalization of unit degradation degree jointly form a convex optimization problem with the charging time constraint. The optimization problem is solved to obtain the equivalent charging current, which is realized through pulse width modulation (PWM) digital control. Simulation and experimental results show that the proposed method has the advantages of reducing ESS operating temperature and maximizing its lifetime. [ABSTRACT FROM AUTHOR]

AC current regulators are susceptible to controller windup, i.e., the condition in which the controller dynamic states ramp the controller output up to very large values when the commanded reference cannot be achieved because of inverter saturation. Recovering from saturation can take considerable time once the linear mode has been restored, which degrades the current regulator's transient performance and can also impact on its stability. This paper proposes an improved formulation using the concept of signal conditioning, where windup is avoided by feeding the controller states entirely from the constrained inverter pulsewidth modulation command. Unlike previous approaches, this technique has the benefit of a simplified realization, since the controller transfer functions do not require algebraic reformulation. This makes it particularly suitable for multiple cascaded resonators used in harmonic compensation systems. The technique has been validated using simulation and experimental investigations for a grid-connected inverter. [ABSTRACT FROM AUTHOR]

Parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) are widely used due to their distinct advantages of high power delivery, modularity, low current rating devices, etc. Along with these advantages, the parallel interleaved 2L VSIs could also be analyzed as a single three-level (3L) VSI. Conventionally parallel interleaved 2L VSIs are modulated using the 2L pulsewidth modulation (PWM) techniques. However, implementation of parallel interleaved 2L VSIs using the 2L PWM techniques may generate a higher ac side current ripple as compared to implementing the parallel interleaved 2L VSIs using 3L PWM techniques. This paper proposes a carrier-based method for implementing different 3L discontinuous PWM (DPWM) techniques for parallel interleaved 2L three-phase VSIs. Comparison of different 2L switching sequences for implementing a 3L DPWM switching sequence based on circulating current, line current ripple, and switching loss is also carried out. Simulation and experimental results are also displayed to validate the proposal. [ABSTRACT FROM AUTHOR]

This paper presents a modular multilevel cascade converter based on triple-star bridge cells (MMCC-TSBC), devoting itself to control and experiment. The TSBC is one of the direct ac-to-ac power converters capable of bidirectional power flow with three-phase sinusoidal currents with any power factor at both supply (input) and motor (output) sides. Therefore, it is suitable for medium-voltage high-power motor drives with regenerative braking, intended to replace a conventional line-commutated cycloconverter using thyristors. This paper provides an intensive discussion on how to control the whole TSBC system, how to regulate and balance the dc mean voltages of all the dc capacitors, and how to mitigate their ac voltage fluctuations. The validity and effectiveness of the proposed control strategy and tactics are verified by a three-phase 400-V 15-kW downscaled model. [ABSTRACT FROM AUTHOR]

This paper presents time-optimal control of an interior permanent-magnet synchronous machine (IPMSM) in voltage-limited and current-limited conditions using deadbeatdirect torque and flux control (DB-DTFC). A commanded air-gap torque and flux can be achieved by the end of each pulse width modulation (PWM) period using the DB-DTFC. However, it may take several PWM periods to achieve a desired torque that is physically infeasible in one step when operating near the voltage limit. The large torque command can be shaped as a feasible trajectory so that the deadbeat torque and flux is achieved for every sample time instant (switching period) along the trajectory. In this paper, the feasible trajectory is dynamically optimized to achieve a large torque command in the shortest time during the voltage-limited and current-limited operation. A loss-minimizing stator flux linkage is used during steady-state operation to reduce the computational complexity of the dynamic optimization and to operate the IPMSM at the loss-minimizing condition. The voltage-limited and current-limited operation of IPMSM drives is evaluated in both the simulation and experiment in this paper. [ABSTRACT FROM PUBLISHER]

This paper presents single- to three-phase dc-link converters with a reduced number of controlled switches for either usual or reduced currents in switches of the rectifier. A suitable model and a control strategy, including a synchronization approach, are developed to obtain the maximum dc-link voltage utilization. Such a synchronization method, associated with the pulse-width-modulated generation signal, forces the input current to have the same phase angle as the input voltage. The main advantage of the proposed converters along with the synchronization method is the reduction of the zero-crossing distortion normally caused by the use of diodes. Simulated and experimental results are presented to confirm the validity of the theoretical expectations. [ABSTRACT FROM PUBLISHER]

For variable-speed drives, the interaction of the machine and the converter is becoming increasingly important, especially for high-speed applications, mainly due to the effect of the converter modulation on the machine losses. The allocation of the losses to different components of the drive system needs to be known in order to choose the ideal machine and modulation combination. In this paper, individual models are introduced for calculating the rotor, copper, and core losses of the machine as well as the inverter losses, taking the modulation type into account. These models are developed by considering two typical high-speed permanent-magnet synchronous motor topologies (slotted and slotless machines) driven by pulse-amplitude modulation (PAM) and pulsewidth modulation (PWM) converters. The models are applied to two off-the-shelf machines and a converter operating with either PAM or PWM. The test bench used to experimentally verify the models is also described, and the model results are compared to the measurements. The results show that PAM produces a higher overall efficiency for the high-speed machines considered in this paper. However, PWM can be used to move the losses from the rotor to the converter at the expense of decreasing the overall drive efficiency. The possible benefits of these results are discussed. [ABSTRACT FROM PUBLISHER]

In this paper, the zero sequence circulating current in open winding permanent magnet synchronous machine (OW-PMSM) drives with common dc bus is systematically analyzed for the first time. It is revealed that the zero sequence circulating current is affected by zero sequence back-electromotive force, cross coupling voltages in zero sequence from the machine side, pulse-width modulation induced zero sequence voltage, and inverter nonlinearity from the inverter side. Particularly, the influences from the cross coupling voltages in zero sequence and parasitic effect of inverter nonlinearity are investigated for the first time in this paper. Then, the synthetic model of the equivalent zero sequence circuit is proposed as well. Each cause is studied independently via analytical modeling, finite element analysis, and experiments. Meanwhile, to tackle this issue, the relevant suppression strategy using frequency adaptive proportional resonant controller is presented and tested on the 3 kW OW-PMSM platform. [ABSTRACT FROM AUTHOR]

Common-mode voltage (CMV) in voltage-source inverters (VSIs) has been well defined and is frequently referred to in the literature. While often referred to, there is no real consistency with respect to how the CMV properties of an individual modulation scheme are evaluated, lacking tools to assess the relative merits or disadvantages of a certain topology or modification of a control scheme. The way that it is analyzed is still mostly a matter of the different authors' foci. In this paper, we propose a metric for the analysis of the CMV, aiming to fill the aforementioned gap. Thereby, the CMV in VSIs is quantified by the number of possible levels and the step sizes between different levels, as well as the respective frequencies of occurrence. The first two are given by the number of levels and the number of phases of the inverter. Depending on the modulation (control) schemes, all possibly available levels or a few of these levels are present in the CMV. We illustrate the use of the tool by applying it to thoroughly study the CMV properties intrinsic to the topologies of multilevel multiphase single- as well as double-ended diode-clamped VSI drive systems. As part of this analysis, we uncover new relationships concerning the existence of zero CMV level. Furthermore, we exemplarily apply the developed tool to the assessment of the CMV properties of selected pulse width modulation (PWM) control schemes and translate the findings into an interpretation of the endangerment of a given drive to suffer damage from inverter-induced bearing currents. The theoretical findings are supported by measurements. This paper also reviews the literature on CMV in multilevel multiphase VSI systems. With the proposed metric in mind, the CMV being mostly discussed as an element of different foci becomes even clearer, confirming again the need for the development of such a tool. [ABSTRACT FROM AUTHOR]

This paper deals with stator-flux-oriented control of permanent-magnet (PM) synchronous motors and synchronous reluctance motors (SyRMs). The variables to be controlled are the stator-flux magnitude and the torque-producing current component, whose references are easy to calculate. However, the dynamics of these variables are nonlinear and coupled, potentially compromising the control performance. We propose an exact input–output feedback linearization structure and a systematic design procedure for the stator-flux-oriented control method in order to improve the control performance. The proposed controller is evaluated by means of experiments using a 6.7-kW SyRM drive and a 2.2-kW interior PM synchronous motor drive. [ABSTRACT FROM AUTHOR]

This paper proposes a new grid current controller for a photovoltaic (PV) module integrated buck inverter using a single pulsewidth modulation switch and an unfolding H-bridge, which significantly reduces switching losses. To achieve this, an internal grid current loop with active damping is presented with an LCL filter to connect it to the utility grid. The problem of the filter natural resonance is solved by means of a virtual impedance (active damping), demanding no additional sensor. Experimental results obtained from a 200-W prototype achieved a European efficiency of 96.27% with a current total harmonic distortion of 3.7%. [ABSTRACT FROM AUTHOR]

Modular multilevel converters (MMCs) are a realistic alternative to the conventional voltage source converters for medium-voltage (MV) and high-voltage direct current (HVdc) applications. The number of submodules (SMs) per arm of the MMC can be as high as 512 to achieve desired high dc voltage levels required for HVdc with a very low total harmonic distortion (THD) (e.g., <0.1%) of the MMC ac-side interface voltage. Although the low THD of the MMC output voltage with a high number of SMs is desirable, the MMC control implementation and complexity is also important to be considered for the high number of SMs. The MMC control complexity significantly increases as the number of SMs increases. Redesigning the number of SMs in MMCs also becomes quite difficult and may require significant control upgrade, which in turn also needs additional tests and validations. This paper presents an MMC scale-up control methodology applicable for MV and HVdc applications. The number of SMs can be conveniently increased or reduced without any significant control modifications. The proposed control method and capacitor voltage balancing algorithm are implemented in the real-time digital simulator and MMC support units based on field-programmable gate array boards. The performance of the proposed MMC control method is investigated for a point-to-point MMC-based HVdc system under various operating conditions. [ABSTRACT FROM AUTHOR]

Electrolytic capacitors are widely used in the dc link of variable frequency drives (VFDs). Their reliability has a significant impact on VFD performance and lifetime. Typically, the lifetime of electrolytic capacitors is specified in vendors’ datasheets at the rated continuous dc voltage and at the rated ripple current at one fixed frequency, under rated temperature, and humidity conditions. In order to analyze and verify their life time specified in the datasheet, a test fixture is needed to apply both adjustable dc-bias voltage and ac ripple current at a specific frequency. In this paper, two portable test fixtures with low kVA requirements are proposed for electrolytic capacitor reliability testing for different dc-bias voltage. The test fixtures can easily be scaled to test large capacitors with high ripple current rating. Multiple capacitor samples or entire capacitor bank assemblies used in VFDs can be tested. Design details of the test fixtures and reliability test results are provided. [ABSTRACT FROM AUTHOR]

Three-phase voltage source pulsewidth modulation (PWM) rectifiers can achieve constant dc voltage and sinusoidal grid currents under ideal grid voltages. However, under unbalanced grid voltage conditions, there are ripples at twice the grid frequency in the dc voltage, and the grid currents become highly distorted. To address the aforementioned problems, control methods developed under ideal grid voltage conditions should be modified. Various techniques have been proposed in the literature to calculate the new current reference or power reference. However, most methods use conventional pq theory and only consider the grid-side power control. Hence, the dc voltage ripples are not completely eliminated. Furthermore, the derived mathematical expressions for reference calculations are usually very complicated. In contrast to current methods, this paper proposes a very simple yet effective direct power control (DPC) method based on extended pq theory. By analyzing the instantaneous extended power of the line inductance, a simple and concise power compensation is analytically derived and added to the original power references. As a result, the dc voltage ripples are significantly reduced, and the grid currents remain sinusoidal even under unbalanced grid voltage conditions. The proposed method is compared to conventional DPC methods, and its effectiveness is confirmed by the presented experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a three-phase four-leg drive for dc-biased sinusoidal current vernier reluctance machine (DC-VRM). By adding an asymmetrical neutral leg to the conventional three-phase inverter, the dc field excitation current can be generated. Compared to the open-winding inverter (conventional drive topology), the three-phase four-leg inverter greatly reduces the number of power devices, and the asymmetrical neutral leg does not have short-circuit straight-through risk. The topology ensures that the stator current can flow in both directions and maximum torque per copper loss can be obtained in DC-VRM. Equivalent carrier-based pulsewidth modulation (PWM) strategy is proposed to produce the dc-biased sinusoidal current and maximize the dc bus utilization. The proposed carrier-based PWM has several different equivalent methods. Compared to the conventional DC-VRM drive, the power loss of the proposed drive with equivalent space vector PWM (SVPWM) can be reduced significantly and can be further reduced by discontinuous PWM minimum (DPWMMIN) in the rated condition. The proposed drive has the characteristics of low cost, high power density, and high efficiency compared to the conventional DC-VRM drive. [ABSTRACT FROM AUTHOR]

In this paper, a highly reliable back-to-back (BTB) power converter is proposed for doubly fed induction generator-based wind turbines (DFIG-WTs). When a power switch open-circuit fault is encountered in either the grid-side converter (GSC) or the rotor-side converter (RSC), a four-switch three-phase (FSTP) topology is formed to avoid using redundant bridge arms, which reduces the power circuit complexity and minimizes the conduction and switching losses. A simplified space vector pulsewidth modulation technique is used to eliminate sector identification and complex trigonometric calculations. In addition, the influence of dc-bus capacitor voltage unbalance on the electromagnetic torque is analyzed in detail. The offset current components are calculated, and they are deducted from the reference values in the modified control strategies to suppress the dc-bus voltage deviation. Moreover, the power loss model of a BTB converter is analyzed in detail, and the efficiency study is performed in various post-fault situations. Simulations in MATLAB/Simulink are carried out to verify the performance of a DFIG-WT based on a FSTP BTB converter. Furthermore, the control hardware-in-the-loop setup with RSC and GSC separately simulated in a digital real-time simulator is applied for experimental verification of the proposed control strategy. [ABSTRACT FROM AUTHOR]

In this paper, in response to the open-circuit fault scenario in the grid-side converter (GSC) of doubly fed induction generator-based wind turbines (DFIG-WTs), a fault-tolerant four-switch three-phase (FSTP) topology-based GSC is studied. Compared with other switch-level fault-tolerant converter topologies, fewer switches, less switching and conduction losses, and simpler converter structure are derived. A simplified space vector pulse width modulation (SVPWM) technique is proposed to improve the output current quality and reduce the computational complexity in the control process. Unified expressions of duty ratios for the two remaining healthy bridge arms are obtained. In addition, the three-phase unbalance phenomenon caused by the capacitive impedance in the faulty phase is analyzed from the ac point of view, and a current distortion compensation scheme is illustrated. Furthermore, a dc-bus voltage deviation suppression strategy is proposed to maximize the dc-bus voltage utilization rate and mitigate the damage to the dc-link capacitors. Simulations are carried out in MATLAB/Simulink2017a to demonstrate the validity of the proposed SVPWM technique and compensation schemes in FSTP GSC for a 1.5-MW grid-connected DFIG-WT when different working conditions are considered. [ABSTRACT FROM AUTHOR]