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Unipolar-pulsewidth modulation (UP-PWM) inverter takes advantages of high power efficiency and small output chokes which is widely used in the industry. However, UP-PWM inverters cannot be used in parallel operation due to a current unbalance problem. This paper studies the current unbalance problem of paralleled UP-PWM inverters with common dc bus and ac bus. First, the problem of unbalanced inductor current is defined and analyzed. Second, a technique to eliminate unbalanced currents is proposed. The proposed current balancing technique only requires one more current sensor in an inverter module rather than changing converter topology or modulation method, which makes it possible to apply UP-PWM inverters in parallel-operation while keeping the advantages of unipolar switching. The proposed current balancing method is verified by both simulation and hardware experiment. Experimental verification is performed on two 1 kW, 400 V input, and 120 V/60 Hz output prototypes, which shows a good agreement to the analytical study. [ABSTRACT FROM AUTHOR]

This paper introduces a three-phase grid-connected inverter for commercial-scale photovoltaic systems. The circuit topology combines an ac-inductor-less active bridge with a parallel-connected pulsewidth modulation inverter acting as an instantaneous reactive power compensator. The active bridge, called a 120° conduction inverter, operates at a switching frequency equal to the grid frequency and outputs a 120° rectangular current, while the compensator eliminates the harmonic currents included in the rectangular current. The main advantage of this strategy is the reduction in size of the required ac inductor by a factor of 4, as well as the reduction of power losses in the switching devices. The theoretical analysis clearly shows that the compensator can synthesize a sinusoidal output current by controlling only instantaneous reactive power, thus eliminating the need for electrolytic capacitors. A 5-kW experimental setup validates the operating principle and the control method of the proposed inverter and exhibits an inverter efficiency as high as 99.2% with Si superjunction mosfets. [ABSTRACT FROM AUTHOR]

Paralleled inverters are not only a suitable approach to increase the power capacity, but also have the capability of common mode voltage (CMV) reduction, or even elimination. The original zero CMV modulation scheme for paralleled inverters suffers from the current jump problem in phase-leg currents. This current jump phenomenon amplifies the peak values of differential-mode circulating current (DMCC) and zero-sequence circulating current (ZSCC), which is adverse for the design of coupled inductor and common-mode inductor. This paper introduces the modified modulation scheme, which can keep volt-seconds balance in whole fundamental period and mitigate the current jump in phase-leg currents. In addition, the reduction effect of the DMCC and ZSCC can be achieved. To verify the analysis, both the simulation and experimental results are presented, which validates the proposed methods and show that they are beneficial for DMCC and ZSCC reduction. [ABSTRACT FROM AUTHOR]

Parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) are widely used due to their distinct advantages of high power delivery, modularity, low current rating devices, etc. Along with these advantages, the parallel interleaved 2L VSIs could also be analyzed as a single three-level (3L) VSI. Conventionally parallel interleaved 2L VSIs are modulated using the 2L pulsewidth modulation (PWM) techniques. However, implementation of parallel interleaved 2L VSIs using the 2L PWM techniques may generate a higher ac side current ripple as compared to implementing the parallel interleaved 2L VSIs using 3L PWM techniques. This paper proposes a carrier-based method for implementing different 3L discontinuous PWM (DPWM) techniques for parallel interleaved 2L three-phase VSIs. Comparison of different 2L switching sequences for implementing a 3L DPWM switching sequence based on circulating current, line current ripple, and switching loss is also carried out. Simulation and experimental results are also displayed to validate the proposal. [ABSTRACT FROM AUTHOR]

Paralleling power converters is a common practice in industries to enhance total power rating, reliability, and availability of the system. In case of fault occurring in systems with parallel converters, the faulty power converter can be isolated and the system can still be operated at reduced power level. In this paper, a grid-connected power converter consisting of two parallel H-bridge converters with low ground leakage current is considered. Two contingency configurations, that are also of low ground leakage current, are proposed to enhance the availability of the system. This is done by reconfiguring the power circuit to a single H-bridge in the case of failure in one of the bridges. The power converter is experimentally tested with the proposed configurations for experimental validation. The results show that the second configuration has better performance in terms of power loss and current total harmonic distortion when operating at lower power level. [ABSTRACT FROM AUTHOR]

This paper presents an energy-recycling class-D low-side gate driver integrated circuit (IC), which can also perform 5-to-15-V level upconversion using a bidirectional flyback converter topology. The gate driver itself is a mini switching regulator that operates at 5–15 MHz to generate 1-μs transition time gate-switching waveforms. In order to maintain uniform charging/discharging currents during transitions, the embedded flyback converter operates in a pulse-frequency modulation mode while charging and in a pulse width modulation mode while discharging the gate node. The required pulses with digitally programmable frequencies and duty cycles are efficiently generated by a custom-designed IC fabricated in a 0.25-μm HV CMOS technology. Also, the presented analysis guides a way to achieve the desired transition time with the maximum efficiency. The prototype IC demonstrates 37.5% energy recycling while driving a 15-V insulated-gate bipolar transistor power switch with 105-nC gate charge at 20 kHz. [ABSTRACT FROM PUBLISHER]

A switching-capacitor-based buck–boost converter (with common ground) for point of load applications is proposed in this paper. It is capable of operating in stand-alone buck or boost mode in addition to its primary operation of performing the buck–boost conversion. The striking feature of the proposed converter is low source current ripple content irrespective of its mode of operation (buck–boost, buck, or boost). First, feasible pulsewidth modulation schemes for the proposed converter are identified and thereafter the corresponding circuit performance analysis, steady-state analysis, and state-space modelling is established. Through steady-state analysis, voltage gain expressions are formulated and equations defining L-C components are derived in terms of their ripple quantities. The state-space models are used to formulate small-signal analysis and to obtain the relevant transfer functions required in the controller design. A voltage-mode/current-mode controller is designed, with a tradeoff in bandwidth, to control the proposed converter and transit it from buck to boost mode or vice versa seamlessly. A 30–55 W, 100 kHz, prototype point of load converter with 36-V input dc source is built to supply power at constant load voltage of either 48 or 28 V. The proposed converters’ effectiveness is demonstrated experimentally in terms of reduced source current ripple along with seamless transition from buck to boost mode and vice versa. [ABSTRACT FROM AUTHOR]

Although the operation of a three-phase current source rectifier (CSR) for ac-to-dc conversion using phase control or low-frequency pulse control is well established in a wide variety of applications, CSR realization using high-frequency pulsewidth-modulation control has been recently studied as a potentially competitive alternative to a voltage source rectifier. In the CSR, reverse blocking gate turn-off switches are realized using series-connected diodes, which prevent any reversal of the dc-link current. A significant consequence of this limitation occurs at light load conditions. The dc-link inductor current enters the discontinuous mode of operation and leads to the loss of the control of the output voltage and a highly distorted input current, which compromise the potential advantages of the approach. This paper characterizes the CSR while operating in the discontinuous conduction mode and proposes a modulation strategy that restores the control of the output voltage and ensures a nearly sinusoidal current at light loads. Simulation and hardware results are provided for a 3-kW laboratory-scale prototype system. [ABSTRACT FROM AUTHOR]

This paper investigates a multilevel inverter composed of series/parallel-connected H-bridges. The presented structure can be used for applications in which the use of semiconductor switches with low-voltage and low-current ratings is intended. A comprehensive system model, an overall control strategy to adjust the output voltage with constant magnitude and frequency, and a level-shifted PWM (LS-PWM) strategy based on a voltage vectors unidimensional analysis and a plane analysis are presented. The LS-PWM is capable of mitigating the low-frequency circulating current, thus generating multilevel voltage signals with low harmonic distortion, maximum number of levels, and low dv/dt. In addition, considering a wide range of values of voltages and currents and various power levels, the total converter losses are reduced compared with the conventional multilevel converters. Two multilevel conventional inverters with the same number of semiconductor switches are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

This paper proposes a zero-voltage-transition (ZVT) pulsewidth-modulated (PWM) synchronous buck converter, which is designed to operate at low voltage and high efficiency typically required for portable systems. A new passive auxiliary circuit that allows the main switch to operate with zero-voltage switching has been incorporated in the conventional PWM synchronous buck converter. The operation principles and detailed steady-state analysis of the ZVT PWM synchronous converter with a passive auxiliary circuit are presented. All of the semiconductor devices aside from the main switch operate under soft-switching conditions. Thus, the auxiliary circuit provides a larger overall efficiency. The feasibility of the auxiliary circuit is confirmed by the simulation and experimental results. [ABSTRACT FROM PUBLISHER]

In this paper for power factor correction (PFC), a modified Landsman converter is introduced. The application is targeted for high-brightness (HB) projection application with brightness control for HB red–green–blue (HB-RGB) light-emitting diode (LED). A pulse-width modulation (PWM) technique is used for intensity control to achieve brightness control of the LED driver. The proposed PFC converter is used to feed a dual output flyback dc–dc converter that supplies power to the forced cooling unit and the LED module with galvanic isolation. The brightness control of LED is performed by synchronous buck converter. The modified Landsman converter operates in discontinuous output inductor current mode for PFC at universal ac mains. A prototype of the proposed LED driver is experimentally verified. The performance of proposed driver is evaluated at full and light-load condition for universal ac mains (90–265 V) over a full range of brightness. The power quality parameters are found within the acceptable limits of harmonic standard IEC 61000-3-2 for universal ac mains. [ABSTRACT FROM PUBLISHER]

In this paper, the switching cell concept is extended to isolated ac–ac converters, and a highly reliable double step-down ac–ac converter is proposed with high-frequency transformer (HFT) isolation. By using the switching cell structure and coupled inductors, the proposed converter has no commutation problem as it is immune from both short-circuit and open-circuit problems, even when all the switches are turned on or turned off, simultaneously. Therefore, it does not require pulse width modulation dead times along with bulky and lossy RC snubbers or voltage-sensing circuitry to implement soft-commutation strategies, resulting in high reliability and high quality output waveforms. The HFT in the proposed converter provides electrical isolation and safety which is required in applications such as dynamic voltage restorer (DVR), solid-state transformer (SST), etc., without the need for external bulky line frequency transformer. Moreover, all the passive components experience twice the switching frequency; therefore, their size can be reduced. The proposed converter is very suitable for application as DVR, to compensate both voltage sags and swells, owing to its ability to provide both inverting and noninverting outputs. A detailed theoretical analysis and operation of the proposed ac–ac converter are provided, and its applications as DVR and SST are also discussed. Experimental results with scaled-down prototype are also provided to verify its performance. [ABSTRACT FROM AUTHOR]

This paper identifies the characteristics of a current source inverter operating in discontinuous conduction mode, and proposes a new multiobjective pulse-width modulation (PWM) method to mitigate voltage boosting and harmonic distortion effects. The method takes into account load impedance effects. Controls are also developed to enable transition between the multiobjective PWM method and conventional PWM as the current source inverter operates in discontinuous and continuous modes of operation. The concept is verified experimentally on a 3 kW test bed. [ABSTRACT FROM AUTHOR]

In this paper, analysis of circulating currents of paralleled single-phase boost converter systems is presented. The dc loop and ac loop circulating currents are clearly explained. In order to eliminate the dc loop circulating currents and reduce switching losses, a simplified pulsewidth modulation strategy is adopted in a paralleled single-phase boost converter. Based on the analysis of circulating currents, common-mode circulating current (CMCC) and differential-mode circulating current (DMCC) are defined. Then, CMCC and DMCC compensators are proposed in a centralized control scheme to reduce the common-mode and differential-mode circulating currents in a parallel system operated in both rectifier and inverter modes with different power sharing for microgrid applications. Converter-paralleled system stability analysis is also presented. Finally, a prototype system is constructed to facilitate the theoretical results as verification. From the experimental results, the proposed control scheme can indeed reduce the circulating currents under equal and/or different power rating conditions in the parallel system. [ABSTRACT FROM PUBLISHER]

Solid-state transformers (SSTs) are an emerging technology that has been developed to improve the stability, reliability, and economic operation of distribution systems. These new transformers are composed of a medium ac voltage (MV) stage, a dc stage, and a low ac voltage (LV) stage. Passive and active dc links are used to construct the dc stage in SSTs in order to offer new functionalities, including hybrid (ac and dc) distribution, reactive power compensation, voltage/frequency regulation, power quality improvement, and distributed generation utilization. On one hand, a distribution SST has its ac stage connected to an MV level, which mandates specific power electronic converter (PEC) topologies, switching element capabilities, and filtering circuits. On the other hand, the dc-link stage has to provide isolation between the MV and LV levels, which requires the employment of isolated dc PECs. Part I of this work provides a review of SST designs and constructions (for deployment in distribution systems), in terms of the required technology, supported functionalities, and construction features. [ABSTRACT FROM AUTHOR]

A five-/nine-level twelve-switch inverter is described for three-phase high-speed electric machines having a low per-unit leakage reactance. By reducing the voltage blocking requirement of the semiconductors, the neutral-point-clamped (NPC) variant of the coupled inductor (CI) inverter topology (NPC-CI) is more suited to high dc bus voltages than the six-switch alternative (six-switch CI). Operational and design details are described for the NPC-CI inverter using a three-limb inductor core, including practical considerations for the inverter construction and operation, 480 V/208 V inductor mass comparison between six- and twelve-switch topologies, natural voltage balancing of the split-capacitor dc link, and voltage stresses of the freewheel diodes. Improvements in machine performance are illustrated using two experimental test rigs: an unloaded 18 000-r/min 15-hp induction machine to illustrate improved harmonic quality when operating with a limited switching frequency and a high fundamental output frequency, and a loaded 2-hp utility speed induction machine to demonstrate transient performance. [ABSTRACT FROM AUTHOR]

This article proposes a common-mode (CM) voltage reduction method using an active power filter (APF) and common-mode transformer (CMT) for a grid-connected three-phase three-level neutral-point-clamped (NPC) AC-DC pulsewidth modulation (PWM) converter. The CM voltage can be caused by switching operations of converters and the CM voltage should be reduced because it is one of the main causes of electromagnetic interference (EMI) noises. In this article, the CM voltage of the three-phase converter with the proposed APF is analyzed to explain the CM voltage reduction using the proposed APF. Based on this analysis, the application of a specific PWM method to the three-phase converter for an optimal reduction of the CM voltage is described. Besides, the APF circuit design and its switching method are proposed considering practical problems such as the self-resonance of inductors and the effect of the dead-time on the CM voltage. To prove the effectiveness of the proposed APF on the CM voltage reduction, experimental results for the CM voltage and current are presented in this article. Furthermore, EMI noise measurement results are shown to verify the performance of the noise reduction capability of the proposed APF. [ABSTRACT FROM AUTHOR]

The isolated dc–ac matrix converter is a promising option to connect dc system and ac system, performing directional power conversion and providing galvanic isolation. Due to the absence of the bulky dc-link capacitor, the converter can be compact. However, when a conventional modulation method is applied to the converter, the coupling of H-bridge and matrix converter will result in numerous harmonics in ac current. This article proposes a new space vector modulation (SVM) strategy for isolated ac–dc matrix converter. It improves the duty cycle calculation to reduce the harmonics in ac current while the number of switching actions remains low. Furthermore, considering the essential commutation process of matrix converter can also impact waveform quality, two-step commutation and optimized zero vectors are adopted to reduce narrow pulsewidth modulation pulses, ensuring the gating signals are always long enough to finish commutation. Simulation and experimental results are provided to verify the performance of the proposed SVM strategy. [ABSTRACT FROM AUTHOR]

To operate a 3-φ induction motor from a voltage source of low magnitude, 3-φ inverters are traditionally cascaded with a boost-type dc–dc converter. However, the use of inductors in the boost stage results in larger volume and weight of the overall motor drive system besides increased losses. To address this issue, an inductor-less boost inverter configuration for 3-φ, low power home appliance motor drives is proposed in this article. The proposed converter is formed by integrating a switched capacitor voltage boosting circuit with a 3-φ inverter. As, the proposed configuration results in an unusual space vector (SV), two novel pulsewidth modulation strategies are proposed: virtual vector space vector modulation (VSVM) and common mode voltage reducing (CMVR) space vector modulation (SVM). The use of VSVM improves the current total harmonic distortion (THD) and reduces the torque ripple while the CMVR SVM results in a 66.6% reduction of CMV without using any external hardware other than the boosting network. As compared to the conventional solutions, the proposed configuration incurs lower losses, improved current THD, and reduced semiconductor requirement. Simulation and experimental results are presented to validate the various claims. A thorough switching and conduction loss analysis is also carried out using the PLECS software. [ABSTRACT FROM AUTHOR]

In order to minimize the common mode leakage current and capability to supply both dc and ac outputs simultaneously, a transformerless wide operating range minimum phase interleaved hybrid converter for photovoltaic applications is presented in this article. The proposed hybrid converter has wide operating ranges of duty ratio (D) and modulation index (Mi), and can be operated at both the conditions, D + Mi ≥ 1 and D + Mi ≤ 1 , which increases the dc gain and improves the ac output quality. Moreover, the proposed hybrid converter exhibits minimum phase behavior as the right half plane zero is eliminated, which enables simpler controller design and facilitates improved bandwidth with higher load current. A hybrid pulsewidth modulation technique is developed for the proposed hybrid converter to minimize the high-frequency common mode voltage terms of the parasitic capacitor and to regulate both the dc and ac outputs simultaneously. The performance of the proposed hybrid converter is compared with other similar topologies to bring out its advantages. Detailed mathematical modeling of the proposed hybrid converter is carried out and a 930-W laboratory prototype is developed to verify its performance. [ABSTRACT FROM AUTHOR]

The conventional step-down dc–dc converters under the single pulsewidth modulation (PWM) control scheme may not provide enough step-down voltage conversion capabilities with considering the minimum on-time and the switching frequency of the power switch. In order to overcome this difficulty, a dual PWM control scheme for designing the high step-down dc–dc converter is proposed in this article. Both high-frequency and low-frequency PWM waveform generators are utilized in synthesizing the dual PWM control of buck converters. The resulting PWM waveform will lead to various switching cycles, and five operating modes of the buck converter, which can be defined accordingly. The operation principle of the proposed converter and its small-signal switched model are presented in detail. One salient feature of the proposed design is that if the duty cycle of the high-frequency PWM is exactly equal to that of the low-frequency PWM, by exploring the volt–second balance condition, the voltage gain can be expressed as the quadratic formula of the duty cycle of the PWM signal when power switches are operated under the continuous conduction mode. Thus, a high step-down conversion ratio and significant reductions of the inductor current ripple can be ensured simultaneously. Since no modifications of the conventional circuit topology are made, the proposed scheme is very cost-effective. Simulation studies and hardware prototype circuit implementations are conducted to validate the proposed design with satisfactory performance. [ABSTRACT FROM AUTHOR]

Impedance source inverters (ISIs) are gaining attention due to features such as single-stage conversion, buck-boost capability, and inherent shoot-through protection. To maintain the required ac output voltage, typically ISIs are operated at a higher dc-link voltage due to constrained modulation index. This also increases voltage stress across capacitors and switches of the converter. This voltage stress is approximately double compared to that of voltage source inverter with preboost stage (Boost-VSI). To mitigate this problem, a new pulsewidth modulation (PWM) scheme for the active-front-end based ISIs (AFE-ISIs) is proposed. The proposed scheme enables the ISIs to produce high ac gain with lower voltage stress across the capacitor and switches. In other words, the proposed scheme blends the advantages of Boost-VSI into ISIs. With the new PWM scheme, there are also reductions in output voltage total harmonic distortion, switching frequency ripple in the inductor current, and power loss in the converter. A prototype of the current-fed switched inverter, an AFE-ISI, is designed, and the proposed PWM scheme is implemented. Experimental results obtained are in accordance with the proposed theory and show that the voltage stress has reduced from 325 V to 203 V for an ac output of 110 V. [ABSTRACT FROM AUTHOR]

A discontinuous pulse-width modulation (PWM) scheme is presented for a six-switch three-limb coupled inductor inverter. Three-level PWM phase output voltages are produced with a reduced switch count and reduced dv/dt stresses on loads and output filters. The PWM scheme described lowers the coupled inductor and semiconductor losses by lowering the inductor winding high-frequency current ripple using two techniques: 1) winding excitation flipping within each carrier cycle; and 2) the inductor magnetic flux is kept within the three-limb core, neglecting natural leakage, by avoiding switching states that produce common-mode voltage excitation of the three-limb inductor. To make best use of the nonstandard switching patterns produced, reference signals are preprocessed before being delivered to the PWM modules using only one carrier signal: representing an approach well suited for implementation in a low-cost digital signal processor. The digital output signals of each PWM module represent the desired switching states of each switch in the inverter. This approach contrasts with previous published work, where postprocessing of the PWM module output signals is necessary using digital logic circuitry, such as a field-programmable gate array. Experimental results, with inductor loss and inverter efficiency comparisons for different operating conditions, confirm that the three-phase six-switch inverter PWM patterns lower the high-frequency current ripple in the inductor windings and, hence, significantly lower the inverter losses and increase the power conversion efficiency. [ABSTRACT FROM PUBLISHER]