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Applying pulsewidth modulation (PWM) to control the gain in audio codecs for mobile applications leads to several advantages, such as the smooth control of tuning parameters, smaller silicon area, and lower power consumption, as compared with other tuning techniques using programmable gain amplifiers and zero crossing detectors. The PWM has to be embedded into the main signal path, preferably in a closed-loop control scheme, in order to exploit its benefits. However, the insertion of dithering and offset controls in a gain setting loop poses the problem of controlling their effects in all gain conditions. This paper reports a novel technique aimed at solving the associated issues and limitations, and provides the experimental proof of the concept through the implementation of a test-chip design on silicon. In particular, this paper reports the design and experimental results of a delta–sigma analog-to-digital converter featuring a click-free gain control technique, dithering insertion, and idle-tone shifting, which has been implemented in a 40-nm complementary metal–oxide–semiconductor technology for commercial telecom audio codec applications. [ABSTRACT FROM PUBLISHER]

This paper presents the design and implementation of a rail-to-rail 460-kS/s 10-bit successive approximation register analog-to-digital converter (ADC) for the power-efficient capacitance measurement. The specifications of ADC are optimized at system level, emphasizing the ADC following a switched-capacitor capacitance-to-voltage (C2V) converter. To be compatible to the output of C2V, a bootstrap switch with body effect reduction is adopted to provide the rail-to-rail processing ability. The charge redistribution converter is implemented by a single-ended cascaded binary-weighted capacitive digital-to-analog converter (DAC). The total area of the DAC array is not only limited by the matching behavior but also by the noise performance of C2V. To relax the settling requirement and improve the power efficiency, self-timing technique is employed which borrows extra half clock period for open-loop settling of preamps. The balance between noise and power consumption of dynamic comparator with preamps is also considered. The ADC circuit was implemented in 0.18- \mu m CMOS technology and occupies an active area of 0.18 \mathrm{mm}^{2} . The tested prototype achieves a signal-to-noise-plus-distortion ratio of 54 dB and a spurious-free dynamic range of 68 dB. The integral nonlinearity and differential nonlinearity are 0.5 and 0.34 least-significant-bit, respectively. The total power consumption is 21 \mu $ W corresponding to 110 fJ/conversion-step figure of merit. [ABSTRACT FROM PUBLISHER]

This paper presents a power-efficient capacitive-sensor interface solution for high-speed and high-resolution subnanometer displacement measurement systems. The proposed solution utilizes a zoom-in capacitance-to-voltage converter stage to remove the offset posed by the large nominal sensor capacitance, which would otherwise dominate the dynamic range. The realized zoom-in factor is 100. The designed circuit uses a correlated-double-sampling technique to cancel both the amplifier offset and the reset noise. First, a printed-circuit-board solution was realized to verify the principle of operation and its limitations. Then, an integrated circuit was designed, fabricated, and tested. Measurement results show that the achievable capacitance resolution is better than 30 aF, from a sensor with a nominal capacitance of 10 pF, which translates into a dynamic range of 18 b. The measurement latency is only 5 \mu\s. This performance is achieved with only 2.4-mW power consumption. [ABSTRACT FROM AUTHOR]