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This paper presents a modified version of the sine wave histogram test for analog-to-digital converter (ADC) characterization. To accurately estimate the transition levels, the input signal has to fulfill strict conditions, which are coherent sampling and uniform distribution of the phases. Noncoherent sampling of the sine wave leads to systematic errors in the transition level estimation, while the nonuniform distribution of the phases increases the variance of the results using the original sine wave histogram test method. The source of the errors is the improper modeling of the histogram of the measured signal. This paper shows that the true histogram of the measured sine wave can be reconstructed by estimating the phases of the sampled signal. It is shown that integrating this information into the estimation of the transition levels can significantly decrease the effect of noncoherent sampling, thus the ADC can be characterized accurately even if the conditions are not fulfilled. The proposed method is verified on both simulated and real measurement data. [ABSTRACT FROM AUTHOR]

This paper proposes a novel linear direct-digital converter for sinusoidal encoders (LDCS) to measure the angular position of a rotating shaft. The outputs of a sinusoidal encoder vary as sine and cosine functions of the shaft angle. The proposed LDCS, which has a low component count, processes these outputs and renders a linear accurate direct-digital output for full-circle range. The LDCS is suitable for both static and dynamic measurements of the shaft angular position. The working principle of the LDCS is mathematically derived and explained in this paper. An elaborate evaluation of non-ideal parameters affecting the LDCS operation is carried out and reported. Furthermore, the static and dynamic performances of the LDCS are verified using simulation and emulation studies. The output nonlinearity obtained during emulation studies, for static measurement, is 0.027 %. A close agreement between simulation and emulation results is observed during these studies. Later, a tunneling magnetoresistance (TMR) angle sensing unit which acts as a representative sinusoidal encoder is fabricated. The LDCS is interfaced with the sensing unit, and several experimental tests are carried out. The worst-case nonlinearity in the static measurement of shaft angle is 0.29 %. Additional tests which study the dynamic performance and effect of mechanical misalignments of the combined TMR-LDCS system is also revealed in this paper. [ABSTRACT FROM AUTHOR]

In spectral analysis, achieving coherent sampling, especially when signals have large distortion, has been a challenge for many years. This paper introduces three algorithms to resolve this issue. In comparison to previous algorithms, and two widely used methods in industry: windowing and four-parameter sine wave fit, these new algorithms are capable of obtaining accurate spectral results of the signal, while achieving high accuracy as well as computational efficiency. The novel contribution of this paper is that not only does it propose two new algorithms, but also it analyzes their advantages and limitations in detail, providing their trade-offs and different fields of applications. Extensive simulations and measurements are performed to validate these algorithms. Combined with their high accuracy, computational efficiency, and robustness against signal purity, these algorithms are readily available to be implemented for bench or on-chip testing. In addition, it is suitable for data converter spectral testing when noncoherent sampling is present, and spectrally pure test signal source is not available. [ABSTRACT FROM PUBLISHER]

This paper presents a completely new approach to measure the jitter at the output of a sample-and-hold circuit. A cyclostationary stochastic process is used to model the entire noise of the measurement system. This approach relies on the calculation of a cyclostationary variance, representing a complete description of the noise of the measurement system. This provides the basis for conducting powerful analyses of how the various noise sources contribute to the cyclostationary variance, enabling the user to gain a deep insight into the noise behavior of the system. A new jitter estimator is derived that provides some new and unprecedented features. First, it is robust against the second harmonic of the input signal, and second, it allows for the elimination of cyclostationary noise contributed by the data acquisition device. A stochastic model of the method is derived and a thorough analysis of the uncertainty of the proposed estimator is presented. This results in a formula that allows for the prediction of the measurement uncertainty and another formula that allows for the calculation of the required number of samples in order to meet a given uncertainty. The method proved to be accurate in Monte Carlo simulations and in measurements as well. A jitter in the range of 22 fs out of a 10-GS/s sample-and-hold integrated circuit was successfully measured with a standard deviation of 230 as. [ABSTRACT FROM PUBLISHER]

In high-speed analog-to-digital converters (ADCs), two main factors contribute to high power consumption. The first is the super linear relationship with the sampling rate; i.e., by doubling the sampling rate, the power consumption more than doubles. The second factor arises from the consumption of analog circuitry responsible to mitigate the jitter noise. By employing a multichannel sampling system, one can achieve high sampling rates by incorporating multiple low sampling-rate channels, which results in a linear scaling of power consumption with the number of channels. The main drawback of this system is the timing mismatch between the sampling channels. In this paper, we intend to jointly compensate the jitter noise and the timing mismatch between the channels using statistical methods. We first approximate the acquisition system and derive a stochastic model. Then, we propose an iterative maximum likelihood algorithm to estimate the parameters of the input signal. We further evaluate the Cramér-Rao lower bound (CRLB) for the estimation error to examine the proposed algorithm. Simulation results indicate that our algorithm is capable of closely following the CRLB curve for reasonable values of jitter noise and a wide range of timing mismatch errors. Moreover, it is shown that the mismatch-compensated multichannel sampling system performs almost equivalently to a single-channel high rate sampler without having its shortcomings. [ABSTRACT FROM AUTHOR]

Analog-to-digital converters (ADCs) are becoming increasingly more common to be involved in most systems with integrated circuits. One of the difficulties being faced is to be able to accurately and cost-effectively test the continually higher performance of ADCs. A part of this test is being able to assess the dynamic linearity of the ADC through dynamic spectral testing. The standard test method for ADCs can be difficult to implement accurately and cost-effectively due to the stringent requirements. This paper develops an algorithm that relaxes the requirements on the linearity of the test signal and of the need to achieve coherent sampling. The standard test requires that the input signal linearity be about 20 dB purer than the ADC under test along with always maintaining coherent sampling. This algorithm will reduce the purity requirement by allowing the test signal to be less pure than the ADC under test while also completely removing the need for coherent sampling. The proposed method will be able to test a 16-b ADC with a target total harmonic distortion (THD) of around −95 dB using a test input signal that has a THD as bad as −50 dB. A test signal with this level of purity would be easy to design as well as be easily accessible in most systems that are being designed. The accuracy and robustness of these methods are demonstrated through simulation and measurement results. [ABSTRACT FROM AUTHOR]

Applying pulsewidth modulation (PWM) to control the gain in audio codecs for mobile applications leads to several advantages, such as the smooth control of tuning parameters, smaller silicon area, and lower power consumption, as compared with other tuning techniques using programmable gain amplifiers and zero crossing detectors. The PWM has to be embedded into the main signal path, preferably in a closed-loop control scheme, in order to exploit its benefits. However, the insertion of dithering and offset controls in a gain setting loop poses the problem of controlling their effects in all gain conditions. This paper reports a novel technique aimed at solving the associated issues and limitations, and provides the experimental proof of the concept through the implementation of a test-chip design on silicon. In particular, this paper reports the design and experimental results of a delta–sigma analog-to-digital converter featuring a click-free gain control technique, dithering insertion, and idle-tone shifting, which has been implemented in a 40-nm complementary metal–oxide–semiconductor technology for commercial telecom audio codec applications. [ABSTRACT FROM PUBLISHER]

This paper designs and experimentally demonstrates an electronic hardware architecture to measure impulse signals without resorting to high-speed analog-to-digital converters (ADCs). The proposed architecture is based on a frequency-domain approach. It consists of multiple channels to down-convert the input signal, each of which obtains a small portion of the input's spectrum. Overlapping bands are designated in between every two adjacent channels, so that multiple narrow-band outcomes can be accurately merged to construct the entire spectrum through postprocessing. The resultant complex-valued spectrum is equivalent to that where the impulses are directly measured in the time domain. The architecture in this paper resembles traditional superheterodyne receivers, and hence, its circuit implementation is simple and robust and has low cost. In our circuit implementation, all the components involved (like oscillators and mixers) are commercially available and have low costs. The circuit is tested by two types of input impulses, both having spectra centered at 2.1 GHz. The input signals' spectra (including both magnitude and phase) obtained by our circuit show excellent agreement with the data measured by a 40-GHz oscilloscope. When the input signal-to-noise ratio is as low as 2 dB, the output of our frequency-domain approach is equivalent to that of a 4-b high-speed ADC. [ABSTRACT FROM AUTHOR]

In cognitive radio (CR) networks, the role of spectrum sensing (SS) is crucial to enable an efficient exploitation of the radio spectrum resource. The need to measure spectrum occupancy turns CRs to be de facto measurement instruments, so it becomes crucial to analyze how real instrumentation peculiarities could affect performance in spectral measurements (i.e., SS performance). In this paper, a commercial software-defined radio (SDR) is adopted as cognitive device, and its capability to accurately measure occupied spectrum is analyzed in comparison also with a simulation setup, where the same analog-to-digital converter (ADC) is modeled and simulated, and equivalent signal-to-noise ratios (SNRs) are replicated. To this aim, a suitable experimental setup has been designed, metrologically characterized, and tuned. Experimental results prove how nominal SNR typically adopted for testing the performance of SS methods is not sufficient to model the impairments of a real acquisition chain, even jointly with a modeling of the digitization process. To assure a reliable SS method validation, new approaches have to be considered for enhancing the accordance between the performance predicted in the simulation environment and the experimental one reachable on real devices. Since different architectures of CRs are present on the market, the experimental tests should be preferred for a reliable SS performance assessment. [ABSTRACT FROM AUTHOR]

In this paper, a dynamic fruit sorting machine weighing system has been studied and optimized to improve weight measurement precision. This new approach relies on the combination of a fast nonstationary filtering technique with a centrifugal force compensation method. The proposed architecture uses the distributed approach, where an intelligent sensor captures a raw signal and applies an adaptive filter. Subsequently, the value obtained is transmitted to a central unit that applies a weight compensation function to improve measurement precision. The second stage considers regression models to capture the existing relationship and introduces the correction compensating working principle of the sorting machine. All provided analyses used the real signal acquired under industrial conditions from testing the sorting machine prototype. Moreover, the classical filtering approach has been used for the purposes of comparison and performance evaluation. The application of the developed scheme allows one to achieve an average absolute error of about 3 g and standard deviations do not exceed 1 g for any of the operating modes in the range up to 1 kg. [ABSTRACT FROM AUTHOR]

This paper proposes a novel method for demodulating low-frequency amplitude-modulated (AM) signals provided by sensors. The method relies on a digital timer that carries out the demodulation and digitization simultaneously, without requiring a rectifier, a mixer, a low-pass filter, or an analog-to-digital converter. This timer-based demodulator extracts the amplitude of the AM signal by measuring the period of a reference signal that is altered by the AM signal itself. The period measurement undergoes a deviation that carries information about the amplitude of the AM signal. The feasibility and also the limitations, such as the nonlinearity and aliasing effects, of this novel demodulator are proved theoretically and experimentally. The concept is also applied to measure an inductive displacement sensor in a range of ±30 mm. A nonlinearity error of 0.5% full-scale span and a resolution of 9 bits are achieved for an overall measuring time of 100 ms. [ABSTRACT FROM PUBLISHER]

Accurate spectral testing plays a crucial role in modern high-precision analog-to-digital converters’ (ADCs’) evaluation process. One of the challenges is to be able to cost-effectively test the continually higher resolution ADCs accurately. Due to its stringent test requirement, the standard test method for ADCs can be difficult to implement with low cost. This paper proposes an algorithm that relaxes the requirements of precise control over source amplitude and frequency, and of the need to achieve coherent sampling. The algorithm divides the output data into segments, and estimates drift fundamental via Newton iteration. By removing the estimated drift fundamental and replacing with a coherent, nondrift fundamental in time domain, accurate spectral results can be achieved. Various simulation results have validated the accuracy of the proposed algorithm. The proposed algorithm is capable of tolerating various test condition variations such as any-level of noncoherency, various input frequency range and different numbers of segmentations. In addition, several measurement results from different ADCs have verified the accuracy of the proposed algorithm, which is able to accurately obtain spectral performance of an 18 b high-resolution ADC. Such algorithm relaxes the standard test requirement such as precise control over source frequency and amplitude, which dramatically reduces the test setup complexity and cost. [ABSTRACT FROM PUBLISHER]

In this paper, three- and four-parameter least squares (LS) sine fitting algorithms are investigated. It is pointed out that the three-parameter fitting is well conditioned in its standard form, both for short and long records. Then, the conditioning of the four-parameter fitting (4PF) is investigated. A scaling factor is derived in order to ensure good conditioning of the equations. A Monte Carlo analysis is carried out to demonstrate that in practical cases, using this scaling factor ensures good conditioning for the four-parameter system. It is also shown that parameters can be determined precisely using direct pseudoinverse calculation for both methods. Hence, in this case, there is no need to use the computationally more demanding decomposition methods, although these are generally recommended for the solution of LS problems. In addition, data centering for time instants is introduced in order to further improve the numerical properties of the 4PF. It is shown that with this method, the four-parameter problem can be approximated with a diagonal matrix. Finally, an evaluation method is presented to significantly decrease roundoff errors of the widely used LS methods. [ABSTRACT FROM AUTHOR]

This paper characterizes the metrological properties of a dual-channel high-resolution digitizer designed for use in a system to calibrate standard resistors with values between 1 \m \Omega and 10 \Omega at frequencies from 40 Hz to 10 kHz. The possibility of using a digitizer to measure the complex voltage ratio is analyzed for both digitizer operating modes: the dual-channel mode with a simultaneous sampling and the single-channel mode with a sequential sampling in which an additional external multiplexer is used. The method of acquiring samples presented in this paper was used to investigate and compare the short-time stability and temperature influences on the metrological properties of the digitizer. This makes it possible to reduce the influence of the instability of the generator, being the signal source for the tested digitizer, on the research results. Moreover, presented in this paper are the frequency characteristics of the magnitude and phase of the complex voltage ratio, as well as the research results of the digitizer linearity and the phase measurement accuracy. All measurements discussed here were performed for both digitizer operating modes. [ABSTRACT FROM PUBLISHER]

In this paper, the timing mismatch compensation problem in the implementation of a time-interleaved analog-to-digital converter (TIADC) is investigated. The investigation leads to a novel multichannel Lagrange polynomial interpolation timing-mismatch compensation algorithm (MLPI-TMCA). A multichannel Lagrange compensation filter (MLCF) in the form of a finite-impulse response (FIR) filter is also developed for real-time implementation. The design of the compensation system is done in three steps. First, the coefficients of the MLCF are computed based on the mismatch parameters of the TIADC. Second, an Nth order FIR filtering process is performed for each sub-ADC. Third, a multiplexer is used to combine the output of each compensation filter in an orderly manner into the final compensated output signal. The computational complexity of this timing mismatch compensation system is of order N. Computer simulation results showed that MLPI-TMCA is computationally efficient and not sensitive to timing mismatch fluctuations. The actual implementation of a four-channel 320-MHz 12-bit TIADC showed that the MLPI-TMCA is able to efficiently compensate the timing mismatch in a real-time manner and produced about 30-dB spurious-free dynamic range (SFDR) enhancement when the input signal frequency is 70 MHz, whereas the multirate filter banks compensation method produced about 19 dB of SFDR enhancement under the same condition. Thus, the MLPI-TMCA and its multichannel filter implementation provides a good solution for TIADC real-time timing mismatch compensation and may be employed in TIADC chip design due to its implementation advantages. [ABSTRACT FROM PUBLISHER]

The semiconductor industry tends to constantly increase the performances of developed systems with an ever-shorter time-to-market. In this context, the conventional strategy for mixed-signal component design, which is based only on analog design effort, will no longer be suitable. In this paper, a digital correction technique is presented for analog-to-digital converters (ADCs). The idea is to use a lookup table (LUT) for the online correction of integral nonlinearity (INL). The main challenge for this kind of technique is the cost in time and resources to estimate the actual INL of the ADC needed to load the LUT. In this paper, we propose to extract INL with a very rapid procedure based on spectral analysis. We validate our technique on a 12-bit folding-and-interpolating ADC and we demonstrate that the correction is efficient for a large range of application fields. [ABSTRACT FROM AUTHOR]

This paper describes a method of calibrating gain errors in each channel of Hadamard modulated parallel delta-sigma (ΠΔΣ) converters. The ΠΔΣ converters extend traditionally bandwidth-limited ΔΣ modulators to applications such as wireless communications that require high-resolution wide-bandwidth converters. The focus of this paper is on the development and convergence of an adaptive calibration algorithm. A hardware implementation that verifies this paper can be found in an earlier work. The calibration is done in real time and is accomplished by adding an additional channel that is linearly dependent on the ΠΔΣ channels that are used. By introducing this redundancy, an adaptive recursive least squares (RLS) algorithm is used to correct for gain errors within the channels. To demonstrate the calibration scheme, an eight-channel ΠΔΣ converter with second-order ΔΣ modulators and an oversampling ratio of 4 was simulated in MATLAB. Simulation results show a 40-dB reduction in unwanted distortion tones caused by 1% gain mismatches. [ABSTRACT FROM AUTHOR]

In this paper, the authors present a new practicable method and the related measurement station for digital-to-analog converters (DAC) characterization. The method relies on the accurate reconstruction of a sine-wave test signal generated by the DAC under test based on the simultaneous acquisitions of the signal attained by filtering the DAC output and the difference between the DAC output and the filter output. Thus, due to straightforward data processing, the signal generated by the DAC is gained with a resolution much better than the resolution (usually poor) of the analog-to-digital converter (ADC) exploited for the acquisition. The main feature of the method is the ease of implementation that requires only traditional electronics and actual measurement instrumentation. In this paper, the authors also suggest simple rules aimed at evaluating the resolution achievable by each guessed measurement station. To confirm the expected encouraging outcomes, experimental results obtained through a measurement station implemented by using a two-channel 8-bit digital scope and based on the presented method are discussed. In particular, signals generated by 12- and 14-bit DACs have been acquired and processed with the measurement station and reconstructed, with a resolution greater than 17 equivalent bits, due to the proposed method. [ABSTRACT FROM AUTHOR]

Embedded impedance spectroscopy is gaining importance in the Internet of Things (IoT) era, where a new class of impedance spectroscopy devices is needed to fulfill a suitable frequency range, size, power consumption, and costs. In this paper, we investigate the feasibility of embedded impedance spectroscopy measurement systems with a focus on power-aware systems. We propose a novel embedded architecture based on a low-cost microcontroller and using a reduced number of electronic components. In order to enable the system for measuring higher frequencies up to 10 MHz, we use the undersampling technique on a relatively simple microcontroller with 12-bit in-built analog-to-digital converters and a sampling rate of 1 mega samples per seconds (MSPs). For the impedance calculation in the range of $100~\Omega -1 \text{M}\Omega $ , the Discrete Fourier Transform (DFT) is implemented directly on the same microcontroller. The experimental validation shows a maximal standard deviation of 0.5% in amplitude measurement and a standard deviation of 0.55° in phase measurement, which are sufficient for various applications of wearable solutions. The system design provides an outstanding performance considering low-cost, small foot print, and low-power consumption. [ABSTRACT FROM AUTHOR]

The compressive sensing theory is implemented by means of analog-to-information converter (AIC) that provides a digitized and compressed output $y$ directly from its analog input signal $x$. A reconstruction algorithm, in turn, is needed to obtain a reconstructed signal $\hat {x}$ that estimates $x$ from $y$. This algorithm can be far away from the AIC, linked through a communication channel, and embedded in a remote machine, for instance. In general, $\hat {x}$ is evaluated in order to test the AIC itself and, in consequence, the performance of the reconstruction algorithm affects the test result of the AIC-under-test and, as a result, can invalidate the AIC test at all. Few state-of-the-art works have proposed the test methods that take into account only the AIC output $y$. However, they take into consideration a single-sine test signal to follow the IEEE Standard 1241 for analog-to-digital converter testing. In this paper, two new AIC test methods are introduced in which only the AIC outputs, that is, only the compressed outputs $y$ , are taken in account. In the first one, multisine signals can be applied and, in the second one, four-parameters sine-wave fit methods, as recommended by the IEEE Standard 1241, can be applied. Experimental results were obtained for two different AIC implementations (namely, random demodulator and random modulation preintegrator) and the signal-to-noise and distortion ratio (SINAD) of both was measured directly from the AIC output proving that the proposed AIC test methods are effective. [ABSTRACT FROM AUTHOR]

Testing of high-resolution, digital-to-analog converters (DACs) with gigahertz clock rates is a challenging problem. The bottleneck is fast and accurate output measurement. This paper presents a novel high-performance DAC testing approach that uses a flash analog-to-digital converter (ADC) to achieve high- speed data acquisition, adopts the wobbling technique to provide a sufficient resolution, and processes the data with a sophisticated algorithm to guarantee high test accuracy. Simulation results show that, by using a 6-bit ADC and wobbling, the static linearity of 14-bit DACs can be tested to better than 1-LSB accuracy. The experimental results that are included in the paper also affirm the performance of the algorithm. This method provides a solution to both the production and on-chip testing problems of high- performance DACs. [ABSTRACT FROM AUTHOR]

Characterization and testing of analog-to-digital converters (ADCs) are important for many reasons. A histogram test is a common method to characterize the linearity features of an ADC. Two commonly used stimulus signals are sine waves and Gaussian noise. This paper presents a metrological comparison between Gaussian and sine-wave histogram tests for wideband applications, that is, we evaluate the performance of the characterization of the ADC and the usability of postcorrection. A postcorrection procedure involves the characterization of the ADC nonlinearity and then the use of this information by processing the ADC output samples to remove the distortion. The results show that the Gaussian histogram test gives reasonable accuracy in measuring nonlinearities. However, it does not result in a suitable model for postcorrection in wideband applications. A single-tone sine-wave histogram will be a better basis for postcorrection. The best result can be obtained if the lookup table is trained with several single-tone sine waves in the frequency band. [ABSTRACT FROM PUBLISHER]

This paper investigates some aspects and features of electrochemical noise measurement instrumentation. A comparison of the resolutions of different analog-to-digital converters demonstrates that converters possessing a resolution of at least 24 bits are preferable due to the significant voltage drift of electrochemical systems. Operational amplifiers having various input types are considered. It is shown that low-noise amplifiers with bipolar input stages are capable of working with low-impedance objects only, such as electrochemical power sources, and that FET input stage amplifiers must be applied when testing the modeling of electrochemical cells having an impedance greater than $50~\Omega $. [ABSTRACT FROM AUTHOR]

Assessing high-frequency (HF) distortion (HFD) in power systems is a new challenge in the framework of in situ power quality monitoring. The International Electrotechnical Commission (IEC) suggests the use of a high-pass filter in the measurement chain, which can be analog (with a dedicated channel for HF assessment) or integrated into its digital form into the signal processing (SP) stage, in order to reduce the measurement uncertainty. This paper proposes a desynchronized processing technique (DPT) as an effective alternative to the other digital filtering techniques presented in the literature, which also allows for a potential simplification of the measurement hardware. The DPT performance is analyzed by means of numerical experiments and laboratory measurements performed using two different test beds and both 16- and 24-bit analog-to-digital converters (ADCs). The test beds are used to evaluate the combined contribution of the ADC and the SP stage to the whole measurement chain uncertainty and identify achievable accuracy levels for different frequency ranges and magnitudes of HFD. The results highlight the strengths of the DPT compared to other techniques and demonstrate its potential to include HF in a comprehensive waveform distortion assessment in power systems. [ABSTRACT FROM AUTHOR]

As analog-to-digital converters become faster, this will allow them to become closer to their intended sensor. This will foster an environment that will continue to allow a paradigm shift in which digital systems replace analog ones, thus mitigating many nonideal effects, lowering costs, and providing more compact computational platforms. In parallel with this trend, the importance of decimation filters will continue to expand, as the high-speed data will need to be downsampled prior to ingestion y a decision-making element, such as a digital signal processor running constant false alarm rate (CFAR) algorithms, neural networks, and the like. Ideally, these decimation filters should have as much stopband attenuation as possible and should not be hindered by timing bottlenecks. However, on a fixed-point processor, like a field-programmable gate array (FPGA), finite word-length effects are in opposition to this goal. To break this nexus, this paper employs a revolutionary integerization technique based on multidimensional continued fractions strategically coupled with an efficient multiplierless architecture design strategy. Multidimensional continued fractions have been known within the mathematical community for some time, which include the popular Furtwängler algorithm and the ordered Jacobi-Perron algorithm, but have been left unexplored in the engineering community until recently. Simultaneous rational representations (SRRs) are another member of the multidimensional continued fraction family and are employed here to create fixed integer transforms with computationally optimal representations. In addition, this paper also focuses on hardware implementations in low-cost FP- GAs or application-specific integrated circuits, which benefit from multiplierless implementation to save hardware real estate. From a computational perspective, carefully choosing how to represent the coefficients of a transform may have dramatic effects on how many operations are consumed to implement it. In a low-order example, the number seven may be expressed as 2³ - 20 or 2² + 2¹ + 20. This concept coupled with SRRS is explored in this paper to yield low-power high-speed implementations for embedded systems. [ABSTRACT FROM AUTHOR]

This reply comments on the results and conclusions of the above paper. The authors analyze the proposed numerical method (the trapezoidal rule) for numerical integration as well as the possible sources of error in this type of processing, and derive analytical expression for them. In addition, the authors provide comments on the principle of signal reconstruction proposed in the above paper and show that the postprocessing operation is not necessary. It has been presented that no doubts exist in the experimental results given in the commented papers, with an accuracy of 0.01%. [ABSTRACT FROM AUTHOR]

This paper presents the linearity characterization of an analog-to-digital converter (ADC). The input signal is noise, which allows low analog area overhead for built-in self-test (BIST). The linearity error estimation is proposed based on the spectral analysis of only the output of the converter. This paper presents the underlying theory and practical results supporting the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

As it currently stands, waveform generators are being employed in many diverse areas, such as radar applications, communication systems, simulation, and testing. There is considerable interest in exploring the beacon of opportunity posed by using digital signal processor (DSP)-based systems to replace costly and inadequate conventional waveform generators. The availability of high performance DSPs allows for the design of highly flexible equipment capable of real-time processing. The arbitrary waveform generator introduced in this paper consists of a DSP, a FIFO memory, a video palette, and a PC interface. A program running on the PC creates a digital representation of a waveform according to user parameters and sends it to the DSP's RAM. The DSP algorithmically converts the digital representation to a point-by-point representation of the desired analog signal. The data points are sent to the FIFO buffer, which latches the data to a video palette that serves a three-channel digital-to-analog converter. The system employs a high-speed serial port interface to communicate with a PC, to allow for readily programmed signals. In addition to the production of traditional signals, such as sinusoids and square waves, a mathematical tool known as splines is employed to aid in the development of customized arbitrary waveforms. Finally, a picture of our new device is presented in the paper. [ABSTRACT FROM AUTHOR]

A practical analog-to-digital converter (ADC) introduces quantization error in excess of the ideal value and one way of expressing this is by comparing the value of this error with that of an ideal ADC. This comparison is known as the effective number of bits (ENOBs). It is accepted practice to measure ENOB using the signal-to-noise and distortion (SINAD) ratio of a sine-wave input. This paper extends ENOB theory to any arbitrary waveform by including the crest factor of the input signal. It is now possible to apply the ENOB concept to wideband systems. Measuring the SINAD of an arbitrary or multitone waveform with precision normally requires the use of laboratory standard test equipment. However, International Electrotechnical Commission standard 60748-4-3 specifies an alternative method for wideband SINAD measurements that may also be suitable for built-in test. It is essentially a multitone test using two pseudorandom signal sources and is sometimes known as the double comb-filter (DCF) method. This paper demonstrates the requirements for a practical implementation of a DCF-based system for measuring an ENOB of up to 24 bits. It is shown that in a practical application, DCF ENOB and sine-wave ENOB results have similar levels of accuracy, but in the presence of amplitude nonlinearity the differing test signal amplitude weightings cannot fundamentally produce the same ENOB figure. It is shown that DCF ENOB is more representative of communications system performance and therefore extends the use of ENOB to wideband applications. [ABSTRACT FROM PUBLISHER]

A quasi-digital dc current sensor with rated current of ±600 A while overload current of about ±750 A is proposed in this paper. The new sensor is based on the open-loop self-oscillating fluxgate technology, but its originality is using a microcontroller unit to detect the duty cycle of the exciting voltage of the fluxgate. Compared with the published similar method, the whole signal chain of the new sensor is quasi-digital and without low-pass filter and analog-to-digital converter required when connected to digital systems. A precisely theoretical equation with respect to the linear dependence between the duty cycle and the current to be measured is established. Based on the equation, factors affecting the sensor sensitivity, accuracy, and resolution are determined, which constitutes the theoretical basis on the optimization design of the new sensor. The sensor linearity is improved using the least-squares polynomial fitting method. Some key specifications including the linearity, repeatability, and power supply effect of the sensor are characterized. The measurement results show that the linearity of the new sensor with the theoretical equation is better than 1.7% in the full scale of ±600 A, and can be improved to 0.3% when the fifth-order polynomial fitting method is used. [ABSTRACT FROM PUBLISHER]

This paper presents the design and implementation of a rail-to-rail 460-kS/s 10-bit successive approximation register analog-to-digital converter (ADC) for the power-efficient capacitance measurement. The specifications of ADC are optimized at system level, emphasizing the ADC following a switched-capacitor capacitance-to-voltage (C2V) converter. To be compatible to the output of C2V, a bootstrap switch with body effect reduction is adopted to provide the rail-to-rail processing ability. The charge redistribution converter is implemented by a single-ended cascaded binary-weighted capacitive digital-to-analog converter (DAC). The total area of the DAC array is not only limited by the matching behavior but also by the noise performance of C2V. To relax the settling requirement and improve the power efficiency, self-timing technique is employed which borrows extra half clock period for open-loop settling of preamps. The balance between noise and power consumption of dynamic comparator with preamps is also considered. The ADC circuit was implemented in 0.18- \mu m CMOS technology and occupies an active area of 0.18 \mathrm{mm}^{2} . The tested prototype achieves a signal-to-noise-plus-distortion ratio of 54 dB and a spurious-free dynamic range of 68 dB. The integral nonlinearity and differential nonlinearity are 0.5 and 0.34 least-significant-bit, respectively. The total power consumption is 21 \mu $ W corresponding to 110 fJ/conversion-step figure of merit. [ABSTRACT FROM PUBLISHER]

This paper demonstrates a fully integrated built-in self-test (BIST) \(\Delta \Sigma \) analog-to-digital converter (ADC) based on the proposed in-phase and quadrature waves fitting (IQWF) procedure. The IQWF procedure enables accurately measuring the phases and amplitudes of test responses so as to enhance the test accuracy of the BIST circuitry. The all-digital BIST circuitry, with on-chip stimulus generator and response analyzer, conducts single-tone functional tests to test for the ADCs characterization results such as signal-to-noise-and-distortion ratio (SNDR), dynamic range (DR), frequency response, input-referred offset, and gain error. Since the IQWF procedure is performed successively in real time, the BIST circuitry does not need huge memory to store all the output samples like conventional fast Fourier transform (FFT) analysis does. The overall hardware overhead only consists of 16.6 k digital gates. The fully integrated BIST \(\Delta \Sigma \) ADC has been fabricated in 0.18- \(\mu \) m CMOS. Measurement results show that the BIST circuitry reports a peak SNDR of 88.0 dB and a DR of 92.6 dB while the corresponding FFT-based analog tests result in 88.8 and 94.1 dB, respectively. Particularly, the BIST circuitry achieves a test bandwidth as wide as the ADCs 20-kHz rated bandwidth, which is the widest to the best of our knowledge. The proposed BIST ADC can be tested without costly external test resources and is thus well suited for the applications in which conventional test resources are not available such as 3-D ICs. [ABSTRACT FROM AUTHOR]

In this paper, the measuring and calibration techniques useful for ensuring the traceability of nonconventional voltage transformer (VT), used in ac power plant up to 52 kV, are described and discussed. In particular, a setup made by commercially available devices is presented and an in-depth accuracy analysis is performed by considering all the uncertainty sources located in the measurement chain. The obtained results prove that it can be used for the calibration of 0.5 accuracy class low-power VTs. In addition, the sources that contribute more to the uncertainties on the ratio and phase errors are highlighted and suggestions on where to act to further improve the accuracy of the presented setup are given. [ABSTRACT FROM AUTHOR]

This paper introduces the importance of biosignal quality assessment and presents a pattern classification approach to differentiate clean from contaminated electromyography (EMG) signals. Alternatively to traditional bottom-up approaches, which examine specific contaminants only, we present a top-down approach using a one-class support vector machine (SVM) trained on clean EMG and tested on artificially contaminated EMG. Both simulated and real EMG are used. Results are evaluated for each contaminant: 1) power line interference; 2) motion artifact; 3) ECG interference; 4) quantization noise; 5) analog-to-digital converter clipping; and 6) amplifier saturation, as a function of the level of signal contamination. Results show that different ranges of contamination can be detected in the EMG depending on the type of contaminant. At high levels of contamination, the SVM classifies all EMG signals as contaminated, whereas at low levels of contamination, it classifies the majority of EMG signals as contaminant free. A transition point for each contaminant is identified, where the classification accuracy drops and variance in classification increases. In some cases, contamination can be detected with the SVM when it is not visually discernible. This method is shown to be successful in detecting problems due to single contaminants but is generic to all forms of contamination in EMG. [ABSTRACT FROM AUTHOR]

In built-in self-test (BIST) environment, clipping is hard to avoid if one wants to obtain full range performance of an analog-to-digital converter (ADC). This could be due to several factors such as circuit component mismatch, noise, clock jitter, and so on. Furthermore, coherency is a challenging task to implement in BIST as its accuracy requirement on frequency of input signal is extremely high. This paper proposes a new spectral testing method with the efficiency and accuracy similar to the straightforward fast Fourier transform, but it can simultaneously handle amplitude clipping and noncoherent sampling. By replacing a noncoherent and clipped fundamental with a coherent and unclipped fundamental, correct spectral specifications can be obtained. Simulation results show accurate spectral parameters of four ADCs with different resolutions. The proposed method is validated using measurement result of a commercial 16-bit ADC. The algorithm error is quantitatively bounded using theoretical analysis and also justified with simulation result. [ABSTRACT FROM PUBLISHER]

This paper proposes a multirate processing technique for obtaining integer and fractional derivatives of digital signals with an improved signal-to-quantization noise ratio. The technique consists of an oversampling analog-to-digital conversion unit with a dithering process and multistage down sampling process followed by an half-band finite impulse response (FIR) differentiator with high performance cascaded using a decimator with a factor of two. In the cascaded multistage processing, each stage contains a simple half-band low-pass FIR filter followed with decimation by two. The proposed technique uses an extremely small size for each half-band low-pass filter, hence requiring much less memory and computational complexity in comparison with the single-stage process. Computer simulations and experimental data processing demonstrate the effectiveness of the proposed method. [ABSTRACT FROM PUBLISHER]

This paper proposes a computationally efficient calibration structure for online estimation and compensation of offset, gain and frequency response mismatches in M-channel time-interleaved (TI) analog-to-digital converters (ADCs). The basic idea of the proposed approach is to reserve some sampling instants for estimating and tracking the mismatch parameters of sub-ADCs with reference to a known input. Since the estimation problem is analogous to a standard system identification problem, we propose two simple variable digital filter (VDF) based adaptive filter structures which are derived from the least mean squares (LMS) and normalized LMS algorithms. On the other hand, the reservation of some sampling instants in the normal operation of TI ADC implies that part of samples have to be sacrificed. Based on a general time-varying linear system model for the mismatch and the spectral property of a slightly oversampled input signal, we also propose a novel iterative framework to solve the resulting underdetermined problem. It not only embraces a number of iterative algorithms for the tradeoff between convergence rate and arithmetic complexity but also admits efficient update structure based again on VDFs. Therefore, thanks to the well-known efficient implementation of VDFs, the adaptability of both estimation and compensation algorithms allows us to combine them seamlessly to form an online calibration structure, which is able to track and compensate for the channel mismatches with low complexity and high reconstruction accuracy. Finally, we demonstrate the usefulness of the proposed approach by means of computer simulations. [ABSTRACT FROM AUTHOR]

Power consumption of high-speed low-resolution analog-to-digital converters (ADCs) can be reduced by means of calibration. However, this solution has some drawbacks such as time slot allocation for calibration and die area increase. This paper presents a 5-bit 1-Gs/s ADC without calibration, fabricated in 90-nm CMOS. Low power consumption has been ensured by operating at both architecture and comparator levels. A folded interpolated architecture has been adopted. However, compared to standard solutions that use static preamplifiers, the interpolation technique has been implemented by taking recourse to dynamic comparators, enabling significant power saving. Moreover, despite the high operating frequency, intrinsic matching has been ensured while keeping low power consumption. The ADC uses double-tail dynamic comparators, operating with a fixed bias current and with reduced kickback noise. Large input transistors are used to guarantee the targeted matching, thereby avoiding calibration. The ADC achieves 4.3b-ENOB (effective number of bits) and 260-MHz effective resolution bandwidth while consuming 7.65 mW from a 1.2 V supply. The ADC figure of meritis 0.39 pJ/conv. step, which is the state-of-the-art performance for an uncalibrated ADC at this sampling frequency and resolution. [ABSTRACT FROM AUTHOR]

In this paper, we present an adaptive calibration method for correcting channel mismatches in time-interleaved analog-to-digital converters (TIADCs). An equivalent signal recombination structure is proposed to eliminate aliasing components when the input signal bandwidth is greater than the Nyquist bandwidth of the sub-ADCs in a TIADC. A band-limited pseudorandom noise sequence is employed as the desired output of the TIADC and simultaneously is also converted into an analog signal, which is injected into the TIADC as the training signal during the calibration process. Adaptive calibration filters with parallel structures are used to optimize the TIADC output to the desired output. The main advantage of the proposed method is that it avoids a complicated error estimation or measurement and largely reduces the computational complexity. A four-channel 12-bit 400-MHz TIADC and its calibration algorithm are implemented by hardware, and the measured spurious-free dynamic range is greater than 76 dB up 90% of the entire Nyquist band. The hardware implementation cost can be dramatically reduced, especially in instrumentation or measurement equipment applications, where special calibration phases and system stoppages are common. [ABSTRACT FROM AUTHOR]

In a previous paper, we reported an algorithm that can be used to accurately measure sampling timing errors in a data acquisition system that encounters nonuniform sampling. In this paper, we first study the sensitivity of the algorithm to input frequency inaccuracy. We then investigate the dependency of the accuracy of the algorithm on the number of effective bits in an analog-to-digital (A/D) converter. It is observed that, if the initial timing error is "reasonably large," then the residual timing error decreases by one order of magnitude for each increase in the number of effective bits by four. Finally, we propose the use of "alias sampling" to "magnify" the timing error so that the algorithm's sensitivity is greatly improved and can be used to estimate a much smaller timing offset with only a modest number of effective bits in the A/D converter. [ABSTRACT FROM AUTHOR]

This paper presents a data acquisition unit which synchronously samples multiple channels in a manner such that the time of day at which each sample is taken is known. This allows measurements taken at multiple locations to be compared with confidence. The intended application is wide area electrical power system measurements, in particular phasor measurement units (PMUs). The novelty of the authors’ design is the application of an open hardware development platform to discipline a commodity analog-to-digital converter (ADC) to a broadcast time signal, usually but not exclusively GPS. The methodology used creates a driver layer for the ADC to achieve real-time sampling in a nonpreemptive Linux environment. The use of open hardware and software addresses the need for a transparent instrument for use in research and development of PMU technology. Through a choice of either a software or hardware phase-locked loop, the ADC is controlled to acquire exactly 256 samples per nominal power system cycle (i.e., 50/60 Hz), precisely time synchronized to GPS, at 16-b resolution and 94.2-dB SNR. The design of a printed circuit board expansion board featuring all necessary components is provided. The performance of the system is evaluated. Interoperability and data exchange with other systems is achieved by use of open schemas and communication protocols. This allows rapid integration with popular numerical simulation environments. [ABSTRACT FROM AUTHOR]

This paper describes a high-speed delta-sigma modulator with 65-nm CMOS technology for ultrasound imaging systems. The delta-sigma modulator is based on a 4th-order single-loop switched-capacitor architecture with a 4-bit quantizer. The designed modulator has the advantages associated with input-feedforward architecture, such as the reduced output swing of the integrator, which relaxes the amplifiers' design requirements. Due to the power and area overheads and the timing constraint of the active adder in the conventional multibit input-feedforward modulator, we use an adder-less input-feedforward delta-sigma architecture. As a result, the designed architecture eliminates the extra power consumption and silicon area required by the adder. The designed architecture also relaxes the timing requirement for the quantizer and the dynamic element-matching block compared with the conventional delta-sigma modulator. The modulator achieves a dynamic range of 76dB and a peak signal-to-noise-plus-distortion ratio of 72.3 dB in a signal bandwidth of 6 MHz. The power consumption is 18.5 mW with 1.2-V supply voltage, and the chip core size is 0.25 mm^2. The energy required per conversion step is 0.46 pJ/conv. [ABSTRACT FROM PUBLISHER]

The aim of this paper consists in identifying the main design specifications of a portable analyzer that allows the vocal signal of a person under monitoring to be acquired and stored. Suitable calibration procedures will be also defined for the microphone used in the portable device in order to ensure the traceability of the obtained measurements. The collected data will be used to identify voice disorders, to prevent an improper use of the voice, and to evaluate the vocal effort induced by noisy and/or reverberant environments. The vocal analyzer is based on a contact microphone worn by the person under monitoring and a portable microcontroller-based unit that hosts the conditioning circuitry, analog-to-digital converter, and storing memory. Two alternative sensors are investigated as contact microphones: an accelerometer and an electret condenser microphone. The former is expected to exhibit a negligible sensitivity to airborne effects, and the latter would provide a larger bandwidth, thus allowing parameters related to the vowel quality to be estimated. Particular attention will be paid toward traceability assurance and uncertainty estimation, and a calibration procedure for each of the estimated parameters will be proposed. In this paper, a data-acquisition-board-based setup has been used instead of a portable microcontroller unit in order to easily perform tests that allow the used microphones to be characterized and the calibration procedures for the parameters of interest to be assessed. Experimental results are reported that refer to the estimation of the parameters sound pressure level (SPL) and fundamental frequency (F0). [ABSTRACT FROM AUTHOR]

This paper analyzes the statistical performance of analog-to-digital converter (ADC) effective-number-of-bit (ENOB) estimators provided by sine-fitting algorithms. Accurate expressions for the estimator bias and standard deviation that hold regardless of the overall ADC output noise characteristics are derived. These expressions are then particularized for ADC output noise composed of tones (both harmonics and spurious tones) and additive white noise. Two specific cases of ideal ADCs and ADCs affected by harmonics, spurious tones, and additive white Gaussian noise are also analyzed. In particular, it is shown that, for values of the number of acquired samples commonly used in ADC testing practice, the sine-fitting ENOB estimators are statistically optimal since they are almost Gaussian, unbiased, and efficient. The accuracies of all the derived expressions are verified through both computer simulations and experimental results. [ABSTRACT FROM PUBLISHER]

Static linearity and spectral performance are the most important parameters that need to be measured in an analog-to-digital converter (ADC) test. Testing these two types of parameters contributes the most significant part of ADC test cost. The relationship between integral nonlinearity (INL) and spectral performance has been used to reduce test cost in many research works. This paper comprehensively investigates the relationship and presents a low-cost test method that measures ADCs' spectral performance based on measured INL values. By making use of INL measurement results, the method eliminates dedicated hardware and test time for spectral performance measurement. It only needs a small amount of computation to obtain ADC's spectral performance. The method is useful in application where spectral performance only needs to be measured at low frequency. Simulation and experimental results show that the proposed method achieves the same measurement accuracy as a standard fast Fourier transform method. [ABSTRACT FROM PUBLISHER]

In this paper, a prototype setup for measuring wideband periodic waveforms whose bandwidth surpasses the analog bandwidth of a radio-frequency receiver is presented. Three major challenges arise in the analog-to-digital stage when measuring such wideband waveforms: the availability of a high sampling rate based on a good amplitude resolution; the availability of the required analog bandwidth to capture the full waveform; and achieving the previous requirements in a cheap way. Those challenges are more pronounced when using wideband modulated signals to test nonlinear devices and when measuring/sensing wideband spectra for cognitive radio applications. For periodic signals, undersampling techniques based on the evolved harmonic sampling can be used to reduce the sampling rate requirements while satisfying a good amplitude resolution. For sparse signals, a technique based on channelization and signal separation is proposed. This technique splits the spectrum of the waveform into parallel channels, downconverts them to the analog frequency band of the analog-to-digital converter (ADC), spreads the channel information, sums them, and then digitizes with a single ADC. Using reconstruction algorithms based on \ell1-norm minimization, the information of the parallel channels can be separated. The original wideband spectrum can be then reconstructed after de-embedding of the channelization process. [ABSTRACT FROM PUBLISHER]

In this paper, a methodology for the power-optimal design of high-resolution low-bandwidth switched-capacitor \Delta\Sigma modulators ( \Delta\Sigma\Ms) is presented. The most power-efficient \Delta\Sigma architecture is identified among single-loop feedback and feedforward topologies with different loop orders N, oversampling ratios OSR, and quantizer resolutions B. Based on this study, an experimental prototype has been implemented in a 0.18- \mu\m CMOS process. It achieves a signal-to-noise ratio of 95 dB over a signal bandwidth fBW of 10 kHz. The prototype operates with a 1.28-MHz sampling rate and consumes 210 \mu\W from a 1.8-V supply. [ABSTRACT FROM PUBLISHER]

This paper overviews a number of \Sigma\Delta modulation techniques to implement efficient analog-to-digital converters intended for low-voltage wideband multimode wireless telecom systems. The \Sigma\Delta architectures under study combine different strategies—unity signal transfer function (USTF), resonation, loop-filter order reconfiguration, and concurrency—in order to increase performance while keeping high robustness against circuit errors. Practical considerations involving timing issues—derived from the combined use of different noise-shaping techniques—are analyzed in order to evaluate the feasibility of the proposed \Sigma\Delta topologies. As an application, the design, circuit implementation, and experimental characterization of a flexible 1.2-V 90-nm CMOS sixth-order three-stage cascade SC \Sigma\Delta modulator is presented. The modulator uses local resonation in the last two stages and USTF and programmable (either three or five levels) quantization in all stages. The chip reconfigures its loop-filter order (second, fourth, sixth order) and the clock frequency (from 40 to 240 MHz) and scales the power consumption according to required specifications. These reconfiguration strategies are combined with the capability of concurrency in order to digitize up to three different wireless standards simultaneously. Experimental measurements show the flexibility of the proposed circuit, featuring a programmable noise shaping within a 100-kHz–10-MHz signal band, with adaptive power dissipation, thus demonstrating to be a suitable solution to digitize signals in future software-defined-radio mobile terminals. [ABSTRACT FROM PUBLISHER]

Timing skews in time-interleaved analog-to-digital converter (ADC) (TIADC) greatly degrade the spurious-free dynamic range of the TIADC, which can be improved effectively by digital compensation algorithms. Literature review shows that many nonblind compensation algorithms required the accurate timing skew parameters measured before the compensation process. In this paper, the blind timing skew estimation (TSE) for the TIADC system is investigated. With the evaluation of the working rationale of the TIADC system and the undersampling nature in each sub-ADC, the relation between the output digital spectra of the sub-ADCs and the source analog spectrum is formulated. A novel subband partition approach has been proposed, and the corresponding expression of the output digital subband spectra of the sub-ADCs in terms of the output digital subband spectra of the TIADC is obtained. With the assumption of the source spectra sparsity, the nonoverlapping frequency points can be determined from the output digital subband spectra of the sub-ADCs. Making use of the determined nonoverlapping frequency points, the phase information of the output digital subband spectra of the sub-ADCs can be employed to provide a good metric to estimate the timing skews, and a closed-form expression of the TSE has been derived. As the result, the source spectrum sparsity-based blind TSE (SS-BLTSE) algorithm has been developed and evaluated. Computer simulation results show that the SS-BLTSE algorithm provides good TSE performance for arbitrarily narrow or wideband source signals. Moreover, it has many merits over the existing blind TSE algorithms, such as there is no prior requirement of the source signal except that it has certain spectrum sparsity, no limit to the number of the sub-ADCs, and the frequency of the input signal can be approaching the Nyquist frequency. [ABSTRACT FROM PUBLISHER]

Treadmills are frequently used training devices; however, inappropriate jogging habits may result in chronic sports injuries. This paper proposes a reaction-force-measuring system and realizes it on constructing treadmills to measure users' feet reaction forces during their exercise period. The proposed reaction-force-aware treadmill can measure reaction forces of jogging subjects at speeds ranging from 1 to 16 km/h, without requiring the subjects to wear any measuring equipment. The feet-reaction-force-measuring system is mainly composed of load cell sensors, signal-amplifying circuits, and low-pass-filtering circuits. This measuring system cooperates with other components, i.e., a central controller, motors, and a liquid-crystal-display-based user interface to form the whole treadmill system. The electrical signals sensed by the load cells are transmitted to an 8052-based central controller through analog-to-digital converters. Then, the central controller transforms the electrical signals into force values. Apart from the literatures, the proposed work possesses three attractive features: 1) measuring reaction forces of users unobtrusively; 2) realizing all the required circuits as a highly integrated embedded system to achieve high efficiency and flexibility; and 3) providing a novel interactive interface between treadmills and users in terms of reaction force monitoring. From the experimental results, we can know that the measuring accuracy of the proposed work is within 1% due to the flexibility in adjusting the amplifying ratio for signal conversion. This work provides a precise, reliable, and economic reaction-force-measuring scheme for treadmill users. Such reaction force measurement enables users to be aware of the reaction forces exerted to them in terms of quantitative data and therefore keep themselves from related sport injuries in advance. [ABSTRACT FROM AUTHOR]