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The presence of error floor in low density parity check (LDPC) codes is of great concern for potential applications of LDPC codes to data storage channels, which require the code to maintain the near capacity error correcting performance down to frame error rates of 10-12. In order to investigate the error floor of LDPC codes under magnetic recording channels used in data storage systems, we extended the trapping set based estimation method to predict the error floor under magnetic recording channels. The goal is to accurately estimate the error rates in the error floor region for certain types of LDPC codes under the partial response channel. First, we use field-programmable gate array (FPGA) hardware simulation to find the trapping sets that cause the decoding failure in the error floor region. For each trapping set, we extract the parameters that are key to the decoding failure caused by this trapping set. Then we use a much simpler in situ simulation with these parameters to obtain the conditional decoding failure rate. By considering all the trapping sets, we obtain the overall frame error rate in the error floor region. The estimation results under the magnetic recording channel are within 0.3 dB of the direct simulation results. [ABSTRACT FROM AUTHOR]

Recently, 32 k-bit sector size for hard disk drives is being investigated to take advantage of the superior performance of long error correcting codes. Meanwhile, low-density parity-check (LDPC) codes have been actively investigated for obtaining coding gains over conventional Reed-Solomon (RS) codes mainly for 4 k-bit sectors. In this paper, the coding gain of a 32 k-bit LDPC code over a 4 k-bit LDPC code, a 32 k-bit RS code, and a 4 k-bit RS code in magnetic recording channels is investigated. The decoding complexity of 32 k-bit LDPC codes and 4 k-bit LDPC codes is also discussed. It is important to evaluate whether the coding gains are enough to justify the increased complexity. Using the 32 k-bit LDPC code, 0.8-dB gain over the 32 k-bit RS code or the 4 k-bit LDPC code (the two schemes coincidentally showed similar performance) at 32 k-bit block error rate (BLER)10-3, and 1.6-dB gain over the 4 k-bit RS code were obtained. It is shown that 32 k-bit LDPC codes require a larger number of iterations than the 4 k-bit LDPC codes. It is also shown that there is much room to improve the design of 32 k-bit LDPC codes than the code used in the simulation. To illustrate the potential, quasicyclic LDPC codes with column weights up to 13 with girth 6 are investigated. [ABSTRACT FROM AUTHOR]

In this paper, we investigate RS plus LDPC concatenated architectures for perpendicular magnetic recording channels. Using simulations, we find the optimal code rate and iterative scheme for the concatenated codes, compare their performance in both random noise and media defects, and show that those whose inner LDPC codes have lower column weights exhibit better performance. In addition, we estimate the performance of the concatenated codes with inner LDPC codes of column weight two, at very high signal-to-noise ratios, and find their error floors. [ABSTRACT FROM AUTHOR]

Two-dimensional magnetic recording (TDMR) is a new magnetic recording paradigm that aims to record one bit of information in one or a few grains, with the goal of achieving a recording density of nearly 10 Tbit/in². In addition to the usual noise, a TDMR channel experiences the problem that some bits are never recorded because of the randomness of grain size and location. Thus, it is believed that a key component of a TDMR channel is two-dimensional (2-D) signal processing along with a strong error correction code. In this study, the TDMR channel is investigated based on a random Voronoi grain model and a signal processing architecture is proposed. Here, a 2-D linear minimum mean squared error (LMMSE) equalizer and a low-density parity-check (LDPC) code are employed and the effects of unwritten bits are modeled by a Gaussian mixture model. In numerical simulations, the proposed architecture shows the feasibility of user bit densities near 10 Tbit/in² for media with a 20 Tgrains/in² grain density. [ABSTRACT FROM AUTHOR]

In magnetic recording, a standard code architecture consists of an outer Reed-Solomon code in concatenation with an inner parity code. The inner parity code is used to detect and correct common error events. Generally, a parity code with short block length performs better, as multiple error events within one block and, consequently, miscorrection are less likely. In this paper, we study an inner code that offers the same system performance as a parity code with very short block length, even as short as the symbol length (in bits) of the outer Reed-Solomon code, but with higher code rate. This code is a tensor-product code, with a Bose-Chauduri-Hocquenghem (BCH) code and a short parity code as constituent codes. The decoder for this code is not much more complex than the optimal decoder of the baseline parity-coded channel; in fact, the only additional steps are Viterbi detection matched to the channel and decoding of the BCH code. [ABSTRACT FROM AUTHOR]

A postprocessing approach is proposed which uses a single-parity, interleaved block code for correcting the errors made by a Viterbi detector. The code proposed here was simulated for an EPR4 channel with two sets of interleave depth D and code word length N with rates 39/40 and 19/20. Simulation showed a realized coding gain of 1.33 dB at a BER = 10-5 and 1.59 dB at a BER = 10-6 for the code with 39/40 rate. The corresponding numbers for the code with 19/20 rate are 1.54 dB and 1.76 dB. [ABSTRACT FROM AUTHOR]