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Nonlinear transmission lines (NLTLs) are passive networks with the capability of modulating baseband pulses. These networks are used for generating RF pulses at high-power levels. NLTLs have a unique performance in high-power RF pulse generation among all the generators based on the solid-state technology. A high-power rectangular pulse is injected to the line, gradually evolved into an oscillatory pulse while propagating through the network, and finally, in the form of a high-power RF pulse, is delivered to the load. Properly terminating an NLTL, in order to transfer the maximum available RF power to the load, is an important problem. In this paper, an accurate analysis is presented, which gives a closed-form formula for the output RF power in lossy NLTLs. Using this analysis, optimal resistive terminating load for RF applications of NLTLs is extracted. The output central frequency is also investigated in this paper. All the obtained theoretical results are verified by SPICE simulations and measurements in two implemented NLTLs. [ABSTRACT FROM AUTHOR]

Impedance translation using passive N-path mixers has been used to achieve local oscillator (LO)-defined series bandstop and shunt bandpass filtering. In this paper, we generalize N-path filtering using a correlator-based approach and propose N-path passive mixers driven by orthogonal sequences. Such sequence-driven N-path filters can potentially reject or select signals based on their properties in the spectral, spatial, and code domains. Specifically, a Walsh-function (WF) sequence (WF-seq)-based N-path shunt filter is implemented, demonstrating the feasibility of shunt bandstop filtering using LO sequences other than nonoverlapping pulses. The WF-seq approach enables reconfigurable concurrent filtering at two different frequencies with shunt operation avoiding penalties due to the switch drive overlap. A 65-nm CMOS implementation achieves 20-dB rejection at one frequency and 14-dB rejection concurrently at two frequencies between 0.3 and 1.4 GHz. The reconfigurable bandstop filter is implemented using analog gyrators and consumes 35–62.5 mW and achieves 2.9-dB noise figure and −2.5–5-dBm IIP3. [ABSTRACT FROM AUTHOR]

This paper presents a nonlinear resonator circuit based on the Duffing equation to enhance the bandwidth of wireless power harvesting and wireless power transfer systems. The Duffing resonator circuit can be implemented with passive components. In this paper, analysis of an electrical Duffing resonator is presented. The detailed discussion of the Duffing resonator’s properties is provided. As a proof of principle, a wireless power harvester employing such a nonlinear resonator has been designed and tested. It is shown that the Duffing resonator circuit enhances the bandwidth of the harvester by 2.7 times compared with a harvester using a linear resonator with the same quality factor, while achieving a similar amplitude level near the resonance frequency. Furthermore, the bandwidth of the nonlinear resonator is independent of its quality factor ( $Q$ ). [ABSTRACT FROM PUBLISHER]

Quasi-lumped-element low-pass filter (LPF) and high-pass filter (HPF) based on substrate-integrated suspended line (SISL) technology are presented in this paper. Double interdigital capacitor, which has advantages of high capacitance density and high quality factor, is analyzed and designed to minimize the filter size. Based on the theoretical analysis, quasi-lumped-element SISL LPF and HPF prototypes are designed. The experimental results show that the SISL LPF achieves ultra-wide stopband up to 24 \textfc ( \textfc is the cut-off frequency) with compact size of 0.180~\lambda g \times 0.082~\lambda g ( \lambda g is the guide wavelength at \textfc) . The SISL HPF features the low insertion loss of only 0.3 dB, while the size is only 0.108~\lambda g \times 0.085~\lambda g . Moreover, the methods of substrate excavation and packaging optimization are proposed to further enhance the performance of SISL LPF and SISL HPF. By doing so, the stopband of SISL LPF is further extended to 32 fc, and the insertion loss of SISL HPF is significantly reduced to 0.1 dB. [ABSTRACT FROM PUBLISHER]

In this paper, a two-stage broadband CMOS stacked FET RF power amplifier (PA) with a reconfigurable interstage matching network is developed for wideband envelope tracking (ET). The proposed RF PA is designed based on Class-J mode of operation, where the output matching is realized with a two-section low-pass matching network. To overcome the bandwidth (BW) limitation from the high- Q interstage impedance, a reconfigurable matching network is proposed, allowing a triple frequency mode of operation using two RF switches. The proposed RF PA is fabricated in a 0.32-\mu\m silicon-on-insulator CMOS process and shows continuous wave (CW) power-added efficiencies (PAEs) higher than 60% from 0.65 to 1.03 GHz with a peak PAE of 69.2% at 0.85 GHz. The complete ET PA system performance is demonstrated using the envelope amplifier fabricated on the same process. When measured using a 20-MHz BW long-term evolution signal, the overall system PAE of the ET PA is higher than 40% from 0.65 to 0.97 GHz while evolved universal terrestrial radio access adjacent channel leakage ratios are better than -\33 dBc across the entire BW after memoryless digital pre-distortion. To our knowledge, this study represents the highest overall system performance in terms of PAE and BW among the published broadband ET PAs, including GaAs HBT and SiGe BiCMOS. [ABSTRACT FROM AUTHOR]

In this paper, a novel matching circuit design method utilizing a genetic algorithm (GA) and the measured S-parameters of randomly moved coil configurations is discussed. Through the detailed comparison of different matching circuit topologies, the superiority of active matching circuits is clearly demonstrated, and potentially there is 21.4% improvement in the wireless power transfer efficiency by using a four-cell active matching circuit, which can create 16 different impedance values. Also, the matching circuit design simulation can be further simplified by choosing a much smaller subset of representative impedance values for the utilized time-changing coil configuration through the employment of $k$ -means clustering and use only these values for the derivation of the optimal matching circuit. This heuristic approach could drastically reduce the time for the matching circuit design simulation, especially for matching circuit topologies with a larger number of cells. [ABSTRACT FROM PUBLISHER]

This paper is focused on the synthesis of capacitively loaded coupled lines for the design of bandpass filters with compact size and spurious suppression. The filters consist of cascaded pairs of coupled lines periodically loaded with patch capacitors. The loading capacitances provide a slow-wave effect to the coupled lines useful for filter miniaturization, whereas periodicity introduces bandgaps that can be controlled in order to achieve spurious suppression. Filter design is achieved following an automated process based on aggressive space mapping (ASM) optimization. The two reported examples, a third-order filter with central frequency f0 = 1.0 GHz, 8% fractional bandwidth, and 0.1-dB ripple level and a fifth-order filter with central frequency f0 = 1.8 GHz, 8% fractional bandwidth, and 0.1-dB ripple level, demonstrate the potential of the proposed ASM-based design approach, as well as the effectiveness of the loading capacitances to reduce filter size and reject the spurious bands. Significant size reduction in both filters is achieved, whereas the out-of-band rejection is better than 30 and 45 dB in the third-order and fifth-order filters, respectively, up to at least 4f0 . [ABSTRACT FROM PUBLISHER]

This paper presents a frequency-agile in-band full-duplex (FD) receiver based on a switched-capacitor continuous-mode vector modulator (VM). The passive VM presented in this paper provides simultaneous downmixing, attenuation, and phase shifting and is used to generate a baseband canceler signal for self-interference (SI) cancelation. A prototype FD receiver is implemented in CMOS 130 nm technology. The receiver is tunable from 0.1 to 0.95 GHz. In FD mode at 900 MHz, the receiver has an effective input-referred third-order intercept power (IIP3) of +7 dBm, SI-to-noise-and-distortion-ratio (SINDR) of ≈ +65.3 dB at −27.5 dBm SI in 15 MHz bandwidth, and noise figure (NF) degradation of less than 1 dB. [ABSTRACT FROM AUTHOR]

This paper presents the first demonstration of nanowatt-level CMOS wakeup receiver (WuRx) front ends (FEs) that utilize microelectromechanical system (MEMS)-based matching networks (MNs). The first FE uses a fully MEMS-based MN (MMN) that operates at 88.8 MHz. It consists of a large array of lithium niobate resonators that are fabricated on the same die. Measurements of the integrated WuRx FE with the MMN indicate that its loaded voltage gain achieves a bandwidth of 0.78 MHz with a quality factor of 114. The second FE uses a hybrid MN (HMN) that operates at 457 MHz. It consists of an aluminum nitride laterally vibrating resonator as well as eight discrete inductors and capacitors surrounding the MEMS device. Measurements of the integrated WuRx FE with the HMN indicate that it achieves a sensitivity of −54 dBm with 7 nW of average dc power consumption without a digital correlator. [ABSTRACT FROM AUTHOR]

Compact balanced bandpass filters based on a combination of multisection mirrored stepped-impedance resonators and interdigital capacitors are presented in this paper. The considered filter topology is useful to achieve wide bandwidths for the differential mode, with broad stop bands for that mode, as well as very efficient common-mode suppression. By conveniently adjusting the transmission zeros for both operation modes, the differential- and common-mode stopbands can be extended up to significantly high frequencies. Filter size and this differential- and common-mode stopband performance are the main relevant characteristics of the proposed balanced filters. The potential of the approach is illustrated by the design of a prototype order-5 balanced bandpass filter, with central frequency f0 = 1.8 GHz, 48% fractional bandwidth (corresponding to 55.4% −3-dB bandwidth), and 0.04-dB ripple level. The filter is automatically synthesized by means of an aggressive space-mapping software tool, specifically developed, and two (pre- and post-) optimization algorithms, necessary to determine the transmission-zero frequencies. The designed filter is as small as 0.48\lambda g \times 0.51\lambda g , where \lambda g is the guided wavelength at the central filter frequency, and the differential-mode stopband extends up to at least 6.5 GHz with more than 22-dB rejection. The common-mode suppression is better than 28 dB from dc up to at least 6.5 GHz. [ABSTRACT FROM PUBLISHER]

This paper presents a fully integrated gallium-nitride high-electron-mobility transistor (GaN-HEMT) Doherty power amplifier (DPA) based on a compact load network for small-cell applications. The gate width of the transistor is optimized to have a load impedance of 100~\boldsymbol\Omega with a shunt inductor that can compensate for the output capacitor using a parallel resonance. A quarter-wave transmission line (TL) with a characteristic impedance of 100~\boldsymbol\Omega is realized using a high-pass \pi -type lumped network for the carrier amplifier. The on-chip input network, including a power splitter, a quarter-wave TL, and matching networks for the carrier and peaking amplifiers, is designed using lumped components. The circuits are simplified by merging the multiple shunt components at a node into an inductor or a capacitor. As a result, the load network has only two shunt inductors. To verify the proposed circuits, a 2.6-GHz DPA integrated circuit (IC) was designed and implemented using a 0.4- \mu \textm GaN-HEMT process. The implemented IC, which was mounted on a quad-flat no-lead package, exhibited a high drain efficiency of 54.4% at an average output power of 37.6 dBm with an adjacent channel leakage power ratio of −27.0 dBc using a downlink long-term evolution signal having a channel bandwidth of 10 MHz and a peak-to-average power ratio of 6.5 dB. [ABSTRACT FROM PUBLISHER]

This paper proposes an adaptive RF front-end (RFFE) architecture that uses an electrical-balance duplexer (EBD) and tuned surface acoustic wave (SAW) resonators to enable adaptive dual-frequency isolation suited for LTE's frequency-division duplex (FDD) mode of operation. Alternatively, in the in-band full-duplex (IBFD) mode, the EBD cancels the in-band TX self-interference directly at RF for increased channel capacity. Furthermore, the EBD's balance network is optimized to reduce the TX insertion loss (IL) below the nominal 3-dB limit in the FDD mode. A 0.18-μm SOI CMOS prototype implements the EBD, low-noise amplifier, and SAW-tuning capacitor banks. The chip is mounted to a module substrate together with the SAWs and matching components. The RFFE achieves >50-dB dual-frequency isolation and 2.6-3.4-dB TX IL in FDD mode, has +58/+42-dBm TX/RX-path IIP3 for an increased IBFD-link budget and handles up to +27.5-dBm TX power in both modes. [ABSTRACT FROM AUTHOR]

Non-Foster elements are highly desired to overcome the bandwidth limit of electrically small antennas, cloaking, and metamaterials. However, they are prone to be unstable and thus it is quite challenging to implement non-Foster circuits in practice. Hence a rigorous and effective method of analyzing the stability should always be the priority when designing a non-Foster network. This paper applies normalized determinant function to analyze the stability of non-Foster circuits. A floating-version negative capacitor based on Linvill’s negative impedance converter is taken as the example. Factors affecting the stability in the practical design are thoroughly investigated, including device parasitics, dc biasing, distributed transmission line in the layout and load impedance. Circuit parameters are substituted with practical values to reduce the complexity of calculation. Finally, experiments are conducted to verify the analysis. [ABSTRACT FROM AUTHOR]

Tunable matching networks (MNs) are essential components for agile radio frequency systems. To optimally design such networks, the total area they cover on the Smith chart needs to be determined. In this paper, the coverage areas of typical MNs have been determined analytically for the first time. It has been found that the coverage area is encompassed by up to five arcs. Analytical expressions for the centers and radii for these arcs have been derived. The theoretical analysis is provided for four typical MNs and verified by circuit simulation and measured data. Moreover, a dynamically load-modulated power amplifier has been designed using the presented theoretical techniques, which demonstrates a measured improvement in the power added efficiency of up to 5% in the frequency range of (0.8–0.9) GHz. [ABSTRACT FROM AUTHOR]

By adding a complex isolation component between two 90^\circ transmission lines at an arbitrary phase angle from the input terminal, a small Wilkinson power divider provides physical separation and electrical isolation between two output ports. General design equations for the complex isolation component are derived from even- and odd-mode analysis. Parallel and series RLC circuits are chosen to realize complex isolation components, respectively. Considering the bandwidths of S22, S33, and S32, inductors in both parallel and series RLC components are omitted to get the widest bandwidths; mathematical proof and design examples are also presented in this paper. A coupled line section with a compensating capacitor is introduced to reduce the circuit size, where characteristic impedances between even and odd mode are different in the coupled line section, and their electrical lengths are also different in inhomogeneous medium. Mathematical equations and simulation examples prove that the compensating capacitor compensates the characteristic impedance difference in the homogeneous medium and the electrical length difference in the inhomogeneous medium. Finally, an experimental circuit shows good agreement with the theoretical simulation. [ABSTRACT FROM AUTHOR]

The constraint on the Wiatr–Pospieszalski (WP) parameter \Theta W\!P= 4 NTo / Tm\leqslant 2, where \N is the Lange invariant and Tm the minimum equivalent noise temperature and To=\290~ \left ( \K \right ), has been suggested as a validation tool for the characterization of active microwave devices, despite its acknowledged limitations. This paper provides a solid theoretical background on \Theta W\!P that is used to investigate noisy linear two-port networks. In particular, parallel feedback is discussed thoroughly in order to understand its effect on the \Theta W\!P parameter and determine the conditions for which \Theta W\!P is larger or smaller than 2. A suitable expression that explains the conditions for \Theta W\!P of on-chip devices to be less than 2 is obtained. The theoretical results are supported by a scalable GaN device model extracted from measurements providing further insight into the noise performance of microwave devices. Finally, the investigation is applied to passive two-port networks to highlight the singular properties of \Theta W\!P=2. The broad result of this paper's investigation is that the constraint \Theta W\!P\leqslant 2 is not a property of the noise parameter matrix as the constraint 1\leqslant \Theta W\!P is; yet, the threshold \Theta W\!P=2 is demonstrated to have unique features for both active and passive two-port networks. Alternative and original demonstrations of the 1\leqslant \Theta W\!P constraint are also obtained as a byproduct of the investigation. [ABSTRACT FROM AUTHOR]

To reduce the weight of a satellite, an internal wireless system (IWS) for satellites was proposed in a previous study. It is a system that can communicate between the satellite’s subsystems by using wireless communication modules. In this paper, we propose a complete IWS for a satellite using microwave wireless power transmission technology. The design of a 5.8-GHz high efficiency rectifier circuit-based charge pump circuit is also presented. Furthermore, we introduced a class-F load that can process the third harmonic components. The rectifying efficiencies of a normal charge pump rectifier and a charge pump rectifier with the class-F load are theoretically compared. To improve the conversion efficiency of the charge pump rectifier, the applied voltages of diodes are adjusted. Owing to inserting the class-F load and adjusted the applied voltage of diodes in this circuit, the conversion efficiency of the charge pump circuit at 30 mW increases to about 78% at 30 mW in the simulation, and to about 71% conversion efficiency in the experiment. In addition, the output voltage is higher than 5 V at an optimal load 1300 $\Omega $ . [ABSTRACT FROM PUBLISHER]

This paper describes the voltage doubler (VD) behavior of a 2.45-GHz VD-type rectenna. An important feature of the developed VD-type rectenna is the absence of the charge pump capacitor that is present in conventional VDs. Based on the circuit simulation and measurement results, the developed VD-type rectenna shows drastic improvement to the radio frequency-to-direct current (RF–dc) conversion efficiency in comparison with a half-wave rectifier (HWR)-type rectenna at output loads exceeding $100~\Omega $ . From the simulation, both the VD- and HWR-type rectennas show VD behavior, even without the charge pump capacitor. This behavior was found to be attributable to the electric charge stored in the junction and package capacitances of the Schottky barrier diode in the rectennas. Additionally, it was found that the improvement of the RF–dc conversion efficiency is caused by the voltage conservation in the series diode. This improvement is dependent on the microwave period and the electric discharge time constant. When the microwave period is comparable with the electric discharge time constant, the VD-type rectenna conserves a dc voltage even when the input microwave voltage is negative. These phenomena were observed by analyzing the voltage and current waveforms of the rectenna equivalent circuit obtained via circuit simulation. [ABSTRACT FROM AUTHOR]

This paper describes a coplanar waveguide coupled to two split-ring resonators that, in turn, are loaded with two different reactive elements. By these means, balanced composite right/left-handed-like (CRLH-like) and also dual balanced CRLH-like (D-CRLH-like) responses can be obtained with the same structure showing opposite propagation characteristics. This behavior is achieved by simply varying one of the reactive elements, i.e., the capacitive or inductive load. The physical behavior of these transmission lines has been successfully explained by means of a single equivalent circuit. Besides, the proposed transmission lines have an extended bandwidth due to the balanced nature of the structure. The bandwidth of these lines can be electronically controlled using varactor diodes reverse-biased by an external dc voltage. Thus, a reconfigurable cell with CRLH-like and D-CRLH-like propagation has been designed and manufactured. The simulated and measured results show fractional bandwidths from 0% (no transmission) to 9.3% for simulations and from 0% (no transmission) to 8.7% for measurements. Undoubtedly, these new proposed transmission lines will be useful for designing reconfigurable devices that can be used in future communication systems such as radar, wireless applications, global positioning systems, or radio-frequency identification systems, among others. [ABSTRACT FROM PUBLISHER]

This paper presents the detailed design and demonstration of a Ka-band single-chip transmit (TX)/receive (RX) front-end in 0.13- \mu \textm SiGe BiCMOS technology. The front-end includes single-pole double-throw (SPDT) switches, low-noise amplifier, loss compensation amplifiers (LCAs), phase shifter, and power amplifier. Distributed structures are utilized in gain amplifiers to ensure broadband performance while stacked structure is adopted in power amplifier to deliver high output power in the TX mode. A 5-b phase shifter with design strategies for low rms phase/gain errors serves as the common leg of the RX and TX paths. In the RX mode, measurements show a gain of 17 dB, an output P\mathrm { {-1~dB}} of −1 dBm, an rms phase error less than 4°, and an rms gain error less than 0.6 dB with 0.528-W dc power from 30 to 40 GHz. In the TX mode, measurements show a gain of 14 dB, an output P\mathrm { {-1~dB}} of 20.5 dBm, an rms phase error less than 3.7°, and an rms gain error less than 0.55 dB with 1.587-W dc power from 30 to 40 GHz. The whole front-end occupies $3.2 \times 2.2$ mm2 including the testing pads. By choosing inductors and capacitors with reasonable values, designing a well-matched SPDT switch with high isolation, and optimum ordering of phase shift cells and LCAs in the phase shifter design, this TX/RX front-end achieves excellent rms phase/gain error performance without any trimming in a system-level measurement at Ka-band. [ABSTRACT FROM AUTHOR]

A design methodology for a compact millimeter-wave on-chip bandpass filter (BPF) is presented in this paper. Unlike the previously published works in the literature, the presented method is based on quasi-lumped elements, which consists of a resonator with enhanced self-coupling and metal–insulator–metal capacitors. Thus, this approach provides inherently compact designs comparing with the conventional distributed elements-based ones. To fully understand the insight of the approach, simplified LC-equivalent circuit models are developed. To further demonstrate the feasibility of using this approach in practice, the resonator and two compact BPFs are designed using the presented models. All three designs are fabricated in a standard 0.13- $\mu \text{m}$ (Bi)-CMOS technology. The measured results show that the resonator can generate a notch at 47 GHz with the attenuation better than 28 dB due to the enhanced self-coupling. The chip size, excluding the pads, is only $0.096 \times 0.294$ mm2. In addition, using the resonator for BPF designs, the first BPF has one transmission zero at 58 GHz with a peak attenuation of 23 dB. The center frequency of this filter is 27 GHz with an insertion loss of 2.5 dB, while the return loss is better than 10 dB from 26 to 31 GHz. The second BPF has two transmission zeros, and a minimum insertion loss of 3.5 dB is found at 29 GHz, while the return loss is better than 10 dB from 26 GHz to 34 GHz. Also, more than 20-dB stopband attenuation is achieved from dc to 20.5 GHz and from 48 to 67 GHz. The chip sizes of these two BPFs, excluding the pads, are only $0.076\times 0.296$ mm2 and $0.096\times 0.296$ mm2, respectively. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate, for the first time, an isolating bandpass filter with low-loss forward transmission and high reverse isolation by modulating its constituent resonators. To understand the operating principle behind the device, we develop a spectral domain analysis method and show that the same-frequency nonreciprocity is a result of the nonreciprocal frequency conversion to the intermodulation (IM) frequencies by the time-varying resonators. With appropriate modulation frequency, modulation depth, and phase delay, the signal power at the IM frequencies is converted back to the RF frequency and adds up constructively to form a low-loss forward passband, whereas they add up destructively in the reverse direction to create the isolation. To validate the theory, a lumped-element three-pole 0.04-dB ripple isolating filter with a center frequency of 200 MHz and a ripple bandwidth of 30 MHz is designed, simulated, and measured. When modulated with a sinusoidal frequency of 30 MHz, a modulation index of 0.25, and an incremental phase difference of 45°, the filter achieves a forward insertion loss of 1.5 dB and a reverse isolation of 20 dB. The measured nonmodulated and modulated results agree very well with the simulations. Such nonreciprocal filters may find applications in wideband simultaneous transmit and receive radio front ends. [ABSTRACT FROM AUTHOR]

Even though CMOS-based power amplifiers (PAs) provide reductions in size and cost for wireless local area network (WLAN) applications, their performances must be improved to match those of HBT-based PAs. In this paper, a design methodology for WLAN CMOS PAs is proposed to obtain broadband performances with a compact area using the wafer-level package technology. To achieve a highly linear output power with high efficiency across a 1-GHz bandwidth in a 5G-band PA, a reconfigurable interstage matching network and a broadband compact output transformer are proposed. For applications requiring a high linear transmission power, an integrated CMOS PA in a full transmitter chain must support the operation with external HBT-based PAs. A structure involving a main internal PA with an external PA driver is proposed to support the external PA mode with low-current consumption. The proposed structure does not require additional components or an output port and does not have the performance degradation of the main internal PA. The implemented 2.4G-band/5G-band CMOS PA using 40-nm CMOS technology has an average output power in the ranges of 19.1–19.2/18.6–18.8 dBm in the respective ranges of 2.4–2.5/4.9–5.9 GHz and concurrently complies with the −32-dB error vector magnitude (EVM) requirement. The power-added efficiencies (PAEs) for the 2.4G-band/5G-band CMOS PA with a −32-dB EVM is 12.9%/12.2% at 2.45/5.5 GHz. To the best of the authors’ knowledge, the presented PA exhibits the state-of-the-art minimum variation with high PAE and an output power in the range of 4.9–5.9 GHz compared to the fully integrated WiFi CMOS PAs reported thus far. [ABSTRACT FROM AUTHOR]

This paper presents an architecture for differential Colpitts voltage-controlled oscillators (VCOs) in complementary metal–oxide–semiconductor (CMOS) that utilizes three design techniques to extend the tuning range (TR) of the VCO, while maintaining a low phase noise (PN) and a low power consumption. First, a switched-capacitor bank based on a variable capacitive feedback technique is introduced to achieve a wide TR with a minimal PN degradation. Second, a $G_{m}$ -boosting technique using interstage inductors is employed to lower the power consumption and relax VCO startup issues. Third, a dynamic forward-body self-biased technique is used to further reduce the power consumption and PN of the proposed structure. As a proof of concept, a 26.3-GHz differential Colpitts VCO is designed and fabricated in a 65-nm CMOS process. Based on the measurement results, the VCO achieves a PN of −122.1 dBc/Hz at 10-MHz offset from the center frequency, and a TR of 20%. The circuit consumes 2.3 mW from a 1-V supply and excluding the pads occupies a 0.22 mm2 of silicon area. Compared to the recently published CMOS VCOs within the same frequency range, the proposed VCO simultaneously achieves a wide TR, low power dissipation, and low PN, resulting in a figure of merit (FOM) and FOM incorporating the TR (FOM $_{T}$) of −187 and −193 dBc/Hz at 10-MHz offset from the center frequency, respectively. [ABSTRACT FROM AUTHOR]

This paper presents an investigation of methods for improving homogeneity inside various dielectric phantoms situated in a 10.5-T human-sized magnetic resonance imaging. The transmit ${B} _{1}$ (${B} _{1}^{+}$) field is excited with a quadrature-fed circular patch probe and a 12-element capacitively loaded microstrip array. Both simulations and measurements show improved homogeneity in a cylindrical water phantom, an inhomogeneous phantom (pineapple), and a NIST standard phantom. The simulations are performed using a full-wave finite-difference time-domain solver (Sim4Life) in order to find the ${B} _{1}^{+}$ field distribution and compared to the gradient-recalled echo image and efficiency result. For additional field uniformity, the wall electromagnetic boundary conditions are modified with a passive quadrifilar helix. Finally, these methods are applied in simulation to head imaging of an anatomically correct human body model (Duke, IT’IS Virtual Population) showing improved homogeneity and specific absorption rate for various excitations. [ABSTRACT FROM AUTHOR]

This paper presents a novel concept for realizing an RF power limiter for protecting superconductor digital receivers. A lumped-element niobium (Nb)-based filter is used as a protection circuit. It consists of lumped-element resonators formed using spiral inductors and metal–insulator–metal capacitors integrated on a multilayer Nb process. The circuit operates as a filter at low-power levels and as a reflector at high-power levels. The lumped-element filter circuit is studied in detail to explain the performance of the filter at high-power levels. It is concluded that some of the lumped-element inductors switch from being inductors when operating at low-power levels to being capacitors when operating at high-power levels. When the lumped-element inductors switch to capacitors, the filter circuit that consists of LC resonators switches to a circuit that consists of capacitors, causing the input power to be reflected back. Both the theoretical and experimental results are presented to verify this phenomenon. In addition to applications in RF power limiters, the concept can be employed to realize transmit/receive (T/R) switches in order to isolate the (T/R) circuit from the receive circuit. [ABSTRACT FROM AUTHOR]

In this paper, an ultra-compact low-pass filter (LPF) with wide stopband is proposed based on lumped L-C structure in through-silicon via-based 3-D stacked configuration. The spiral inductor (L), interdigital capacitor (C), and the proposed LPF are theoretically analyzed based on parasitic parameters and equivalent circuit models. To evaluate the characteristics, the proposed LPF is simulated by HFSS, fabricated with CMOS-process-compatible technology, and measured with de-embedding method. Simulation and measured results are in good agreement. Compared with the other literature, the proposed LPF has the most compact size of $0.028\lambda _{g }\times 0.017 \lambda _{g}$. ($\lambda _{g}$ is the guide wavelength at $f_{c}$.) With the cutoff frequency at 10.05 GHz, the filter has an insertion loss of 0.14 dB and reflection loss over 13 dB from dc to 9 GHz in the passband. The suppression levels are better than 20 dB from 20.4 up to 40 GHz in the stopband. [ABSTRACT FROM AUTHOR]

This paper presents a new type of a low-loss miniaturized coplanar-waveguide (CPW) transmission line (TL) by employing distributed loading, capacitors and inductors, in 0.18- $\mu \text{m}$ complementary metal–oxide–semiconductor (CMOS) technology. The capacitors are realized by vertical parallel plates made of vias, and a group of open stubs inserted to the signal line, whereas the inductors are realized by high impedance lines. Then, the proposed CPW-TL is employed to design a miniaturized millimeter wave ultra-wideband low-loss Wilkinson power divider/combiner (WPD/C). The proposed distributed loading results in reducing each WPD/C arm length by more than 50% without changing its characteristic impedance and insertion loss (IL). The design is fabricated in 0.18- $\mu \text{m}$ CMOS technology and tested. The measured results show a wideband performance from dc to 67 GHz with 1-dB IL and isolation greater than 15 dB from 36 to 67 GHz. In addition, the fabricated WPD/C achieves an excellent amplitude imbalance and phase imbalance of less than 0.16 dB and 0.45°, respectively. The core chip size is $336 \times 165\,\,\mu \text{m}^{2}$ , which is almost 32.8% compact compared to the recently proposed WPD in the same technology. [ABSTRACT FROM AUTHOR]

This paper presents a periodic electromagnetic bandgap (EBG) structure in the integrated fan-out wafer-level package (InFO-WLP) technology for gigahertz-band noise suppression. The proposed EBG structure consists of an $LC$ resonator with two symmetrical spiral inductors in series and a shunt metal–insulator–metal capacitor between power and ground planes. The third-order equivalent model of the EBG structure is also proposed and extracted by field solver ANSYS Q3D to model the performance. In addition, the EBG arrays with different sizes of unit cell and the corresponding stopband bandwidth and isolation were characterized. The measurement results show that the proposed $1 \times 4$ EBG array of 600- $\mu \text{m}$ square unit cell can achieve a 29.5-GHz stopband bandwidth together with an over 30-dB isolation level. Furthermore, by using the InFO-WLP technology, the proposed EBG structure is integrated with an RF low-noise amplifier (LNA) fabricated in a 16-nm FinFET technology as a case study to validate the power noise immunity. The experimental results show that the measured output spectrum of LNA integrated with the proposed EBG structure at the power plane can suppress the noise tone from −37.37 to −68.65 dBm. [ABSTRACT FROM AUTHOR]

The performance of additively manufactured microwave passive elements and interconnects continues to improve as better materials, and process techniques are developed. In this paper, laser-enhanced direct print additive manufacturing (LE-DPAM) is used to fabricate capacitors and inductors for coplanar waveguide (CPW) circuits. Acrylonitrile butadiene styrene is used as the dielectric that is printed using fused deposition modeling, and DuPont CB028 conductive paste is deposited using microdispensing. These two techniques are combined with picosecond-pulsed laser machining to achieve $\simeq 12$ - $\mu \text{m}$ slots on printed conductors, producing aspect ratios greater than 2:1. The same laser is used to fabricate vertical interconnections that allow for the fabrication of multilayer inductors. Inductances in the range of 0.4–3 nH are achieved, with a maximum quality factor of 21, selfresonance frequencies up to 88 GHz, and an inductance per unit of area of 5.3 nH/mm2. Interdigital capacitors in the range of 0.05–0.5 pF are fabricated, having a maximum quality factor of 1000, a capacitance per unit area of 1 pF/mm2, and selfresonances up to 120 GHz. All the components are made on the center line of a CPW that is 836- $\mu \text{m}$ wide. The results show that LE-DPAM enables the fabrication of compact passive circuits that can be easily interconnected with MMIC dies, which at the same time can be manufactured as part of a larger component. This enables the fabrication of structural electronics that are functional into the millimeter-wave frequency range. Bounds on the inductances and capacitances per unit area are related to material and geometry limitations. [ABSTRACT FROM AUTHOR]

Benefiting from advantageous features of fast tuning, small size, and easy integration, the electronic impedance synthesizer (EIS) has been developed for on-wafer load–pull characterization systems, tunable matching networks, reconfigurable devices and systems, and so on. The previous designs of the EIS were mostly based on the empirical data instead of a closed-form design. Moreover, incomplete figures of merit (FOM) were chosen to optimize and evaluate the EIS. In this paper, we propose and present, first of all, a semiclosed-form design procedure for the distributed EIS. Then, a particle swarm optimization method is introduced to optimize the proposed nonuniformly distributed EIS, which comprises an adjusting circuit and a nonuniformly distributed circuit. Experimental results demonstrate that the proposed nonuniformly distributed structure can not only improve the Smith chart coverage but also reduce the size, compared to the uniform counterpart. The fabricated nonuniform EIS operating from 0.8 to 2.5 GHz, exhibits a good agreement between theory and measurement. Furthermore, the most comprehensive FOM are presented to evaluate the fabricated EIS. [ABSTRACT FROM AUTHOR]

A single-output, band selecting interposer is designed to combine three identical all-digital CMOS transmitter (Tx) chips. The open-drain CMOS Txs are flip-chip connected to the primary windings of three frequency selecting transformers realized on a single PCB interposer. The secondary windings of the three transformers are connected in series and they share a single output. Across 0.4 to 4 GHz, a peak power higher than 22.9 dBm is achieved collectively by the three sub-Txs with a drain efficiency (DE) better than 25%. The peak powers/DE of the three sub-Txs are 28.6 dBm/50%, 27.4 dBm/49%, and 24.7 dBm/34%, at 0.85, 2.1, and 3 GHz, respectively. This paper further demonstrates that the band selection can be achieved via reconfiguring the CMOS inverse Class-D switching power amplifiers. As demonstrated via continuous wave and 64-quadratic-amplitude modulation, WLAN, and LTE modulation tests, the reconfigurable Tx package exhibits high power and efficiency across all supported bands. [ABSTRACT FROM AUTHOR]

In this paper, we present a low-power low-noise integer-N divider-less digital phase-locked loop (PLL) with high resolution. Phase detection is performed by a proposed analog-to-digital converter (ADC)-based time-to-digital converter composed of subsampling, charge pump (CP), time-domain variable-gain amplifier, and successive-approximation register (SAR) ADCs. Subsampling is well known for its high detection gain. The CP and the pulse generating circuit are also introduced to form the time-domain integral variable-gain amplifier, enhancing the resolution. An SAR ADC voltage signals into the digital domain, avoiding the use of analog filter which occupies large area. Moreover, compared to the conventional analog phase detectors, the SAR-ADC phase detector saves more area and power consumption. The novel PLL is implemented in a standard 65-nm CMOS process, occupying an area of 0.12 mm2. It presents an in-band phase noise of −108 dBc/Hz and an rms jitter of 357 fs at the operating frequency of 5 GHz. In addition, the proposed ADC-PLL achieves a competitively good figure of merit of 243 dB with a power consumption of only 3.9 mW. [ABSTRACT FROM AUTHOR]

A recently proposed technique for enhancing near field, wireless energy transfer is to add resonant coils between the transmitter and the receiver. It also has the potential to provide a simple method for enhancing read range of near field radio frequency identification (RFID) systems. In spite of this, its application to the RFID context has not been, yet, deeply analyzed. This paper models and analyzes a half-duplex, frequency shift keying RFID system with one additional coil between the reader and the tag, considering both phases (charging and reading) of this bidirectional operation. A three-coil RFID system was designed using a commercial tag (RI-INL-R9QM widely used in cattle identification), reader (using a TMS3705), and the additional resonant coil (whose radius and quality factor were optimized). In addition, the influence of high coil quality factor is addressed for steady-state and transient response. The designed system increases almost $2.7 \times $ the original RFID read distance (from 16 to 43 cm). The analytical design and measurements data are in good agreement. The design procedure can be applied not only to other RFID systems but also to other systems that use the same channel to energize and transfer data, such as some implantable medical devices. [ABSTRACT FROM PUBLISHER]

Supplementary solutions are provided for the swapped port coupler proposed by Jeong and Kim in the above paper. It is shown that the solution given in the above paper using uncoupled line section is not the only one for the coupler operation and a more generalized solution is presented through the extended analysis. The newly proposed solutions make it possible to design the swapped port coupler based on coupled lines with variable coupling coefficients or adjustable values of the lumped capacitor. [ABSTRACT FROM PUBLISHER]

This paper presents the design, fabrication, and measurement of a reconfigurable quadrature hybrid coupler and a tunable low-loss reflective-type phase shifter built using the Cavendish Kinetics RF microelectromechanical systems switched capacitor devices. The quadrature coupler tunes from 1.5 to 2.2 GHz with 20–50-MHz steps, and > 20-dB reflection and isolation. The phase shifter covers 360° at 2.0 GHz with an insertion loss of 2.0 ± 0.5 dB at different phase states. The linearity measurements show that these devices can handle up to 5 W of input power at 1.8–2.2 GHz with an input third-order intercept point (IIP3) > 44 dBm} over all phase states. The measured second and third harmonic components are < -90 dBc at 30 dBm of RF input power. The application areas are in-phase shifters for micro and pico base-stations in the 1.7–2.3-GHz range. [ABSTRACT FROM PUBLISHER]

This paper presents a high-speed and low feed-through sampler with two-channel time-interleaved track-and-hold amplifiers (THAs). The THA is based on switched buffer with active inductors load such that wide bandwidth in track-mode and small-signal feed-through in hold-mode can be both achieved within compact area. Furthermore, one clock-controlled auxiliary transistor is also introduced to cancel clock feed-through in hold-mode. With two-channel accurate on-chip clock and its distribution network, double sampling rate is achieved due to the two-channel time-interleaved structure used. The chip was fabricated in 65-nm RF-CMOS process with core area of 0.07 mm^2 and power consumption of 211 mW. The measurements show that the S-parameters matched input and output up to 40 GHz with 19.3-GHz bandwidth in track-mode, the spurious-free-dynamic-range above 35 dB and total harmonic distortion below -\30 dB up to 6 GHz when the sampling rate is 16.26 GS/s for one channel. [ABSTRACT FROM AUTHOR]

Nonlinear transmission lines (NLTLs) are one of the most prominent solid-state sources of high-power RF pulses. However, there is no integrated mathematical basis, which predicts adequately the generated waveforms on an NLTL and those delivered to the load. This analysis is required for designing and optimizing these transmission lines. Most works in this area are related to experimental studies and results. In this paper, we have developed a theoretical basis, which predicts all the required characteristics of the generated RF pulses on a lossy NLTL. The RF amplitude, the maximum voltage, and the central frequency of the generated pulses at each node of an NLTL are formulated. All the obtained formulas were verified by SPICE simulations and experimental measurements. The comparisons made with the data obtained from the reported experimental studies of the other researchers in this field reinforce these analytical results as well. [ABSTRACT FROM AUTHOR]

In this paper, an adaptive N-path filter design technique is presented. The filter designed by this method can be reconfigured to different shapes, e.g., Butterworth or Chebyshev with variable bandwidth (BW), based on the user requirements. In addition, an analytical synthesis procedure is introduced to realize high-order bandpass filters (BPFs) based on N-path architecture with a prescribed set of specifications. A proof-of-concept BPF is fabricated and measured in a 65-nm CMOS process. The filter can be reconfigured to realize different filter shapes by changing coupling capacitors. The BW of the proposed filter is also tunable. The passband of the filter is tunable from 0.2 to 1.2 GHz with a gain of 14.5–18 dB, a noise figure of 3.7–5.5 dB, and a total power consumption of 37.5–52.7 mW. The channel BW can be varied from 20 to 40 MHz and the filter out-of-band third-order intercept point ( $\Delta f=50$ MHz) is 25 dBm. [ABSTRACT FROM AUTHOR]

In this paper, a microstrip reconfigurable wideband filtering power divider (FPD) with tunable center frequency (CF), bandwidth (BW), and power division is presented. The proposed structure consists of two trimode stub-loaded resonators, a three-line coupled structure loaded two varactor diodes, and two output parallel-coupled lines loaded a lumped capacitor. The CF and BW of wideband filtering response can be tuned by controlling the varactor diodes loaded onto the open end of trimode resonators. Meanwhile, the power division ratio (PDR) is controlled by tuning the coupling strength between the center line and sidelines of three-line coupled structure. Compared with the conventional wideband FPDs, the capacitor loaded onto the parallel-coupled line of two output ports is to enlarge the coupling, which can increase the return loss (RL), and thus relieve the limitation of the line space between two coupled lines. A complete design procedure with analytical design equations for driving parameters of the structure is described. The measured results show that the CF can be tuned from 0.86 to 1.32 GHz with RL better than 16 dB, while the 1-dB BW can be tuned from 180 to 710 MHz. The measured isolation is better than 21 dB from dc to 2.5 GHz. Then, the achieved PDR can be tuned from 1:1 to 3:1. The proposed circuit can be also utilized as a switchless bandstop filter, where the isolation is better than 20 dB from dc to 19 GHz. The proposed tunable wideband FPD exhibits good RL, wide range of frequency and BW control, wide harmonic suppression, high isolation, and multifunctional application. [ABSTRACT FROM AUTHOR]

With rapidly increasing switching speeds and surge current requirements, placement of local decoupling capacitors is becoming critically important in high-speed low-power designs. In this paper, utilizing the driving-point impedance (viewed from the device pin) as a metric, a new method is presented for the placement of decoupling capacitors in parallel-plate power ground pairs of high-speed circuits. In the proposed approach, instead of using the traditional trial-and-error method to identify an appropriate placement distance, the process is formulated in the form of a transcendental function. The resulting function is solved using Newton–Raphson (N-R) iterations to give a direct solution for the distance. Also, an analytical representation based on Hankel functions for the driving point impedance and its derivatives is developed to speed up the N-R iterations. The proposed method is validated by comparing the results with the full-wave electromagnetic simulations. [ABSTRACT FROM PUBLISHER]

In this paper, a model for the input impedance of a hot-wire electro-explosive device (EED) based on differential-mode measurements is proposed. The model represents the EED using three transmission line segments in cascade. The characteristics of each segment are estimated according to data reported in the literature and to measurements of the differential-mode input impedance of actual EEDs in the ultrahigh frequency range. The experimental procedure and model are presented in detail. In addition, the impedance measurements and the predictions of the proposed model are compared with previous results reported in the literature. [ABSTRACT FROM PUBLISHER]

Modern wireless network operators are consistently looking for improvements in the wireless access infrastructure that minimize size, weight, and power. Therefore, compact multiband RF and wideband RF solutions offer an attractive role in forthcoming fifth generation networks. This paper presents a novel compact wideband RF transmitter architecture that is based upon an undersampled digital predistortion (DPD) methodology. The proposed architecture minimizes the required number of RF/analog components in the system by using RF-DAC-based direct RF sampling at the forward transmitter data path and one undersampled analog-to-digital conversion (ADC) with certain bandpass filters at the DPD sampling receiver path. Extensive experimental results validate that the DPD-enabled RF transmitter bandwidth can be significantly increased using the proposed multirate track-and-hold amplifiers architecture. Experimental tests achieved multiple GHz DPD bandwidths with satisfactory linearization performance via very compact sampling receiver that has one undersampled ADC. Particularly, we evaluated three application scenarios: 1) three-band carrier aggregated LTE signals (each one occupying 20-MHz instantaneous bandwidth), the linearization performance achieved 50-dBc adjacent channel power ratio (ACPR) with more than 1-GHz bandwidth using ADC running at 76.8 and 61.44 MSPS; 2) single-band LTE signal with continuous 100-MHz instantaneous bandwidth, the linearization performance achieved −48-dBc ACPR using 61.44-MSPS ADC; and 3) single-band LTE signal with continuous 20-MHz bandwidth at 4 GHz, the linearization performance achieved −54-dBc ACPR using 61.44-MSPS ADC. [ABSTRACT FROM PUBLISHER]

In this paper, the capacitively coupled LC resonators with loaded p-i-n diodes are used to develop fixed-response filter-integrated single-pole double-throw (SPDT) switch. The filter-integrated on-state channel with reverse-biased p-i-n diodes can be designed and synthesized using the coupled-resonator filter theory, and the off-state channel with forward-biased p-i-n diodes exhibits high suppression. A 1-GHz filter-integrated SPDT switch with ripple bandwidth of 195 MHz is designed to demonstrate the proposed design concept. Measured results show that it has a low on-state insertion loss (IL) of 1.03 dB, a wide passband, high off-state suppression (OSS), high port-to-port isolation, and compact circuit size. Since both the properly misaligned resonant frequencies of LC resonators and weakly coupling between LC resonators also result in high suppression, a frequency-agile filter-integrated switchless SPDT switch without p-i-n diodes can be designed by using the varactor diodes to realize the corresponding capacitors. A frequency-agile filter-integrated switchless SPDT switch with constant 1-dB fractional bandwidth of 19.5% is also designed. Measured results show that its operating frequency can be tuned from 0.612 to 1.088 GHz with corresponding frequency tuning range of 58% and IL varying from 2.8 to 2.3 dB. Good return loss, high OSS, and port-to-port isolation can be also observed. [ABSTRACT FROM AUTHOR]

This paper presents systematic analysis and design of a megahertz multiple-receiver (RX) wireless power transfer (WPT) system driven by a Class E power amplifier. Both circuit-level and system-level analyses are conducted to discuss the characteristics of the WPT system. In order to simultaneously manage the power flow and maximize the overall system efficiency, a new control scheme is proposed that combines maximum efficiency point tracking and time-division multiplexing. Through the proposed scheme, RXs with different loading and coupling conditions can be charged by the same transmitter with simplified design and control strategy. Finally, the proposed control scheme is validated using an example 6.78-MHz three-RX WPT system. The experimental results show that various power requirements can be quickly and stably satisfied, and the overall average system efficiency can reach as high as 71.7%. [ABSTRACT FROM PUBLISHER]

A new topology of a low-power F-band reflection amplifier for active reflectarrays is proposed and demonstrated using a CMOS fully depleted silicon-on-insulator 28-nm process. The design enables frequency response and center frequency tuning, as well as phase control of the reflected signal. The chip consumes a core area of only 90\times 80~\mu\textm^2 and is incorporated into a $2\times 2$ printed reflectarray antenna, implementing the first co-polarized active reflectarray. Such implementation enables, for the first time, active reflectarrays with dual polarization ability, which can be used for full-duplex links, as well as polarization diversity applications. Design considerations for a stable reflection amplifier, as well as measurement results of the reflection amplifier and reflectarray, are presented in this paper. Variable stable gain of 5–25 dB at the frequency range of 106–127 GHz was achieved, with noise figure of 10.5–11.7 dB. The total power consumption was 6–20 mW, depending on the chosen frequency response. An active antenna gain of 28 dBi was measured for the $2\times 2$ reflectarray. [ABSTRACT FROM AUTHOR]

In this paper, a surface acoustic wave (SAW)-less receiver (RX) front-end adopting switchable front-end architecture has been presented for second-generation/third-generation/fourth-generation cellular applications. Depending on the RX–transmitter (TX) frequency separation, a favorable down-mixing architecture is selected between a current-sampling mixer and a voltage-sampling mixer. The proposed switchable architecture meets the specification of an input-referred second-order intercept point (IIP2) for the SAW-less RX while minimizing the power consumption. The implemented RX front-end consists of a wideband capacitor cross-coupled common-gate low-noise amplifier, a 25% duty-cycle passive mixer with IIP2 calibration circuitry, a baseband transconductor, and a trans-impedance amplifier. Fabricated in a 65-nm CMOS process, the SAW-less RX front-end provides conversion gain of 42 dB, and achieves noise figure of below 3.3 dB, out-of-band input-referred third-order intercept point of -\2 dBm, and IIP2 of more than 56 dBm. It draws an average current of 14.8 mA from 1.2 V. The die area is 1.71 mm^2. [ABSTRACT FROM PUBLISHER]

This paper presents the development and demonstration of a high-efficiency rectifier for millimeter-wave-to-dc energy conversion. It is a critical circuit block that renders possible the use of a single CMOS chip die with no substrate and wiring, as the implementation of a batteryless, yet active tag for next-generation high data-rate millimeter-wave identification technologies. We also propose an architecture of a reader-tag system that addresses the underlying technical challenges. The rectifier is based on a differential drive cross-coupled topology that has been shown to work at UHF frequencies only so far. In this paper, we investigate significant challenges in implementing this topology at millimeter-wave frequencies with good power conversion efficiency (PCE). The analyses, design, and results presented in this work demonstrate the feasibility of achieving this by minimizing simultaneously the small on-resistance and the reverse leakage current in the MOS transistors, and by reducing losses and parasitic capacitances through proper transistor sizing and layout optimization. Using a standard 65-nm bulk CMOS process, a chip was designed, fabricated, and tested under different input and output loading conditions. The rectifier exhibits an overall PCE of 20% at 24 GHz, 18% at 35 GHz, and 11% at 60 GHz under RF available driving power of 6, 6, and 3 dBm, respectively, and output load resistance of 1, 1, and 2 \k\Omega, respectively. These PCE performances at millimeter-wave frequencies have never been reported in the literature. [ABSTRACT FROM AUTHOR]

This paper presents the system and circuit design of a compact radio frequency (RF)-powered 2.4-GHz CMOS transmitter (TX) to be used for autonomous wireless sensor nodes (WSNs). The proposed TX utilizes the received dedicated RF signal for both energy harvesting as well as frequency synthesis. A TX RF carrier is derived from the received RF signal by means of a delay locked loop and XOR-based frequency multiplier. The 50- $\Omega $ load is subsequently driven by a tuned switching RF power amplifier (PA) with 25% duty cycle input for high global efficiency. The design is fabricated in 40-nm CMOS technology and occupies a die area of 0.16 mm2. Experimental results show a rectifier with 36.83% peak efficiency and power management circuit with 120-nA current consumption that enables a low start-up power of −18.4 dBm. The TX outputs a continuous 2.44-GHz RF signal at −2.57 dBm with 36.5% PA drain efficiency and 23.9% global efficiency from a 915-MHz RF input and supports ON–OFF keying modulation. [ABSTRACT FROM PUBLISHER]

A miniaturized wideband interferometry-based sensor for complex dielectric spectroscopy of liquid chemicals is presented in this paper. Two composite right-/left-hand (CRLH) transmission lines (TLs) are employed in a direct downconversion architecture. The material under test (MUT) is placed in direct contact with the printed interdigital capacitor of the artificial TL as the sensing component. Since the employed CRLH TL provides nonlinear dispersion characteristics, improved sensitivity with wideband (4.2–8 GHz) operation is achieved compared with resonator- or TL-based interferometers. The sensor circuit board is realized based on common printed circuit board technology, and the fluidic polydimethylsiloxane channels are fabricated and bonded to the circuit board using 3-D printing and soft lithography techniques. The measured results of pure liquid chemical characterization suggest the mean squared errors of ~1.1% and ~1.6% for \epsilon ^\prime r and \epsilon ^\prime \prime r , respectively, compared with the MUT’s theoretical model. Moreover, binary mixture characterization is carried out based on \epsilon ^\prime r measurements with an accuracy of 1%. [ABSTRACT FROM PUBLISHER]