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This paper reports the RF packaging design for electrooptic modulators operating in the millimeter-wave domain and discusses the RF and optical performances of the module. An \LiNbO3 phase modulator has been integrated in a compact housing offering a 1.0-mm RF coaxial input connector. A coplanar waveguide on a low dielectric-loss alumina substrate has been designed to transition the RF field from the connector to the modulator. A RF insertion loss in the 1–2.5-dB range has been measured for the module over the 70–110-GHz bandwidth. A half-wave voltage comprised between 8.6 V at dc and 20 V at 110 GHz was calculated based on the observation of the optical modulation sidebands over the entire 110-GHz bandwidth. The optical insertion loss of the module was measured at 2.8 dB. [ABSTRACT FROM AUTHOR]

CMOS RF switches support watt-level RF output power while enabling signal processing with high speed. Typically, RF FET switches offer a tradeoff between a power handling and modulation bandwidth. This paper investigates the cause of compression in a FET switch, and the analysis suggests the optimization of the gate driving impedance for a stacked-FET switch. A design methodology is presented to realize watt-level power handling with high fractional bandwidth (FBW). The measurements demonstrate a BPSK modulator that can handle up to 10 W with wide FBW. The high-power, low-insertion loss, and high-modulation bandwidth demonstrate record performance. [ABSTRACT FROM AUTHOR]

This paper presents a high-efficiency 60-GHz on–off keying (OOK) transmitter (TX) designed for wireless network-on-chip applications. Aiming at an intra-chip communication distance of 20 mm, the TX consists of a drive amplifier (DA), a high-speed OOK modulator, and a transformer-coupled voltage-controlled oscillator. For high efficiency, a common-source topology with a drain-to-gate neutralization technique is chosen for the DA. A detailed mathematical design methodology is derived for the neutralization technique. The bulk-driven OOK modulator employs a novel dual feedthrough cancellation technique, resulting in a 30-dB on–off ratio. Fabricated in a 65-nm bulk CMOS process, the TX consumes only 19 mW from a 1-V supply, and occupies an active area of \ 0.077 mm^2. A maximum modulation data rate of 16 Gb/s with 0.75-dBm output power is demonstrated through measurements, which translates to a bit-energy efficiency of 1.2 pJ/bit. [ABSTRACT FROM AUTHOR]

A wideband sub-harmonically pumped (SHP) modulator and demodulator fabricated in 0.15-\mum GaAs pseudomorphic high electron-mobility transistor technology are demonstrated in this paper. The chip is appropriate for emerging 60-GHz multi-gigabit communication applications. Digital modulation degradation resulting from in-phase/quadrature mismatch is effectively minimized by the proposed power-locked loop system. By overcoming the bandwidth limitations and quadrature errors in amplitude and phase, the sideband suppression ratio exhibits broadband performance with the feedback mechanism. By using the SHP mixer structure, the dc offset problem is mitigated because of decreased 2\,\times\, local oscillator leakage. In addition, sub-circuit design considerations and feedback stability are described in this paper. The SHP modulator and demodulator demonstrate flat conversion-gain responses of -\14 \pm \2 dB and -\14 \pm \1 dB, respectively, from 51 to 68 GHz. Properties of multi-gigahertz modulation and demodulation bandwidths show the potentials for gigabit applications. The amplitude and phase imbalances are restricted within 0.3 dB and 5^\circ (\pm\2.5^\circ), respectively, regardless of modulation or demodulation. High data-rate digital modulation and demodulation are successfully performed through 16-QAM and 64-QAM schemes within four channels of the IEEE 802.15.3c standard with outstanding error vector magnitude performances. [ABSTRACT FROM PUBLISHER]

RF pulsewidth modulation (PWM) has been proposed as an efficiency improving technique for power amplifiers (PAs) handling varying envelope signals. The core idea is to modulate the varying envelope into a square-wave signal such that the width of each pulse is varied according to the envelope, and any phase in- formation is contained in the timing of the pulses. The square wave signal can give a theoretical efficiency of 100% for the subsequent PA. Such a system differs significantly from a conventional up-conversion and PA and, therefore, a significant design challenge results. The first important step is to generate the PWM signal. This paper demonstrates a functional modulator for Universal Mobile Telecommunications System operating at 2 GHz. The modulator is designed in a GaAs HBT process and uses low-frequency feedback combined with predistortion to obtain a high spectral purity. Measurements show a Universal Mobile Telecommunications System PWM signal with more than 10-dB margin to the modulation mask and an error vector magnitude of less than 1.5% rms (requirement: 17.5%). [ABSTRACT FROM AUTHOR]

Sub-harmonic modulator and demodulator are presented in this paper using 0.13-μm standard CMOS technology for millimeter-wave (MMW) wireless gigabit direct-conversion systems. To overcome the main problem of local oscillator (LO) leakage in direct-conversion systems, the sub-harmonically pumped scheme is selected in this mixer design. An embedded four-way quadrature divider is utilized in the sub-harmonic Gilbert-cell design to generate quadrature-phases LO signals at MMW frequency. For broadband applications, a broadband matching design formula is provided in this paper to extend the operational frequency range from 35 to 65 GHz. To improve the flatness of conversion loss at high frequency, high-impedance compensation lines are incorporated between the transconductance stage and LO switching quad of the Gilbert-cell mixer to compensate the parasitic capacitance. The sub-harmonic modulator and demodulator exhibit 6 ± 1.5 dB and 7.5 ± 1.5 dB measured conversion loss, respectively, from 35 to 65 GHz. For MMW wireless gigabit applications, the gigabit modulation signal test is successfully performed through the direct-conversion system in this paper. To our knowledge, this is the first demonstration of the MMW CMOS sub-harmonic modulator and demodulator that feature broadband and gigabit applications. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate the first implementation of the integrated system-on-package (SOP) 60-GHz gigabit modulator and demodulator on liquid-crystal polymer (LCP). LCP provides an organic low-cost low dielectric-constant platform suitable for millimeter-wave passive design and packaging. Firstly, we demonstrate a 60-GHz planar bandpass ifiter and RF/baseband duplexer as the building blocks of the integrated module. Measurement results show `∼3-dB insertion loss in the bandpass filter, as well as the RF path of the duplexer, and a higher than 30-dB isolation between the baseband and RF outputs. We utilize those building blocks in the design and implemented a hybrid 60-GHz antiparallel diode-pair-based 4 × sub-harmonic mixer suitable for direct up or down conversion. Measurement results indicate a better than 17-dB insertion loss with 1.25-GHz baseband bandwidth for the 4 x mixer. Input 1-dB compression point of -2 dam has been measured. Two sub harmonic mixers are integrated back-to-back to perform the simultaneous binary phase-shift keying modulation and demodulation of the pseudo- random binary sequences. Eye diagrams show a better than 13-dB SNR for a data rate up to 1.5 Gb/s. 40-GHz versions of the 4 × sub harmonic mixer and the back-to-back chain have also been im- plummeted. Hence, we present the first integrated millimeter-wave gigabit SOP modulator and demodulator on LCP. [ABSTRACT FROM AUTHOR]

In this paper, low-voltage evolution and high-speed operation mixer design are presented for millimeter-wave (MMW) CMOS in-phase/quadrature (I/Q) modulator and demodulator. The modified Gilbert-cell mixer architecture, which eliminates the three-level transistors stacking in the conventional Gilbert-cell mixer, can operate at a reduced supply voltage while maintaining reasonable performance. In addition, IF transimpedance amplifier buffer and wideband RF design are introduced to increase the operation speed of the mixer for MMW gigabit wireless transmission link applications. Using a 0.13-\mum CMOS process, the I/Q modulator and demodulator formed with the modified Gilbert-cell mixers are demonstrated at the MMW. Under 1.2-V standard supply voltage, the modulator and demodulator exhibit excellent conversion gain (CG) flatness of -\3.5 \pm \1.5 dB and -\3 \pm \1.5 dB from 41 to 69.5 GHz and 31 to 69 GHz, respectively. For 60-GHz wireless personal area network applications, \pi/4 differential quadrature phase-shift keying, 16 quadrature amplitude modulation, and binary phase-shift keying modulation signal tests are successfully performed through the direct-conversion system. The results show that the presented monolithic microwave integrated circuits can operate at low-voltage and low-power while providing good CG and high data rate, even up to multigigabit. [ABSTRACT FROM AUTHOR]

The problems of RF identification are discussed. It is shown that the use of passive transponders is preferable, but weak energy of the system in this case reduces the operation distance and decreases the noise immunity of the system. In this paper, it is proposed to use the homodyne method of selecting the useful signal. This solution allows to increase the energy and the noise immunity of the system (the operation distance is increased). Furthermore, the interrogator can treat several transponders simultaneously. [ABSTRACT FROM AUTHOR]

Traditional TEM-based I/O communication through either PCB traces or free space has significant path loss and electromagnetic (EM) interferences that are hardly employed toward low-power and dense I/Os for data server. We propose a 0.1–1 THz or sub-terahertz (THz) I/O interface using surface plasmonic polariton (SPP) interconnects in CMOS to obtain high-energy efficiency and low-crosstalk interconnect. The surface wave can be established with on-chip generation and further deployed for signal propagation by corrugating periodical grooves onto the traditional transmission line. It will result in a strongly localized electromagnetically wave onto the surface of top-layer metal in wideband, leading to the broadband low EM coupling between many core and memories. Moreover, we have also developed a high on/off ratio split-ring-resonator-based modulator to support the sub-THz I/O communication. The proposed SPP interconnect achieves data rate of 25 Gb/s with 0.016 pJ/b/mm energy efficiency at 140 GHz in 65-nm CMOS. In addition, two surface-wave channels placed with 2.4- \mu \textm spacing exhibits an average −28-dB crosstalk ratio. [ABSTRACT FROM PUBLISHER]

A low-current direct-conversion transmitter (TX) is obtained by combining an efficient single-balanced 25% duty-cycle passive mixer with a low-bias single-ended driver. The nonlinearity of such architecture is aggravated by strong harmonics at the mixer output folding down to the fundamental frequency due to driver nonlinearity. To address this, a baseband mathematical model of the passive mixer plus nonlinear driver is derived. Then, based on this model, a novel digital-predistortion approach is disclosed. Implemented in 40-nm CMOS, the modulator and driver combined consume 45 mW when delivering a +3-dBm Release 99 WCDMA signal with 0.9% error vector magnitude (EVM) and -59-dBc adjacent-channel leakage power ratio (ACLR). In long-term evolution (LTE) mode, the TX delivers +0-dBm 10-MHz LTE 16QAM with -53-dBc ACLR and 1.2% EVM. [ABSTRACT FROM AUTHOR]

The effort to confine the electromagnetic field by silicon passive metadevices has made the design of an on-chip wideband sub-terahertz (sub-THz) I/O redriver feasible, paving a new way toward energy-efficient and crosstalk-immune ON–OFF keying (OOK) communications. Two metadevices, namely spoof surface plasmon polaritons (SPPs) metawaveguide and split-ring resonator (SRR), are exploited to build the sub-THz low-crosstalk silicon channel and high-ON–OFF-ratio modulator, respectively. A sub-THz signal source combining the merit of spoof SPPs and SRR is introduced. A 140-GHz dual-channel redriver composed of these metadevices is fully integrated in a 65-nm CMOS technology. The redriver realizes both 27–1 and 231–1 13.5 Gb/s/lane for dual-channel OOK modulation. The measured energy efficiency is 2.6 pJ/bit/lane and the bit error rate (BER) is ≤10−12, demonstrating a crosstalk-immune sub-THz I/O system. The power consumption is 35.1 mW/lane and the active area of the redriver is 0.23 mm2. [ABSTRACT FROM AUTHOR]

A comparison of envelope elimination and restoration (EER) and envelope tracking (ET) is discussed and a ‘hybrid’ wideband EER power amplifier (PA) for the WLAN 802.11g system is proposed. A 60% efficiency (the output envelope signal power/input dc power) DC-20-MHz wideband envelope amplifier is designed for wideband EER and wideband ET (WBET) applications. A design method is developed to optimize the efficiency of the envelope amplifier for a given peak-to-average ratio and average slew rate of the envelope signal. An experimental ‘hybrid’ Class-E EER system shows an overall efficiency (modulated RF output power/envelope amplifier dc input power) of 36% and power-added efficiency (the modulated RF output power/envelope amplifier dc input power plus RF input power) of 28% for a WLAN 802.11g signal at 19-dBm (80 mW) output power at 2.4 GHz. Digital predistortion, time alignment, and memory effect mitigation are implemented. The measured 3 % error vector magnitude exceeds the 802.11g specification for 5% for a 54-Mb/s modulation signal. [ABSTRACT FROM AUTHOR]

This article presents a high data rate, high-efficiency 60-GHz on–off keying (OOK) CMOS transmitter and receiver. The transmitter consists of a voltage-controlled oscillator (VCO) and a modulator. The receiver consists of a low-noise amplifier, detector, and limiting amplifier (LA) and has a compact design. An analysis of the on–off isolation of the modulator and bandwidth of the LA reveals that the proposed transformer (TF) between the modulator and the VCO can improve the on–off isolation, and the feedforward capacitor can enhance the bandwidth. Implemented in the 65-nm CMOS technology, the transmitter and the receiver consume dc powers of 12.1 and 21 mW, respectively, at 12.5 Gb/s. Moreover, they occupy core chip areas of 0.09 and 0.06 mm2, respectively. The transceiver system is constructed with on-board Yagi–Uda antennas, and it achieves 12.5 Gb/s wireless OOK data transmission for a pseudorandom binary sequence of length 27 −1 with a bit error rate of less than 10−12. The proposed transceiver system achieves an energy efficiency of 2.65 pJ/bit. [ABSTRACT FROM AUTHOR]

A low-power and high data-rate fully integrated 60-GHz on–off keying (OOK) transceiver for short-range wireless communication is demonstrated. The transceiver consists of a switch, transmitter, and receiver and uses OOK modulation for a compact and low-power design. With a highly efficient Tx, high-speed modulator/demodulator, and wideband characteristic, the transceiver has low-power and high data-rate capability. Implemented in 90-nm CMOS technology, the transmitter and the receiver consume 31 and 36 mW at 10.7 Gb/s and occupy an active footprint of 0.15 and \ 0.29 mm^2, respectively. The transceiver with an on-board Yagi–Uda antenna achieves 10.7-Gb/s wireless OOK data transmission over 10 cm at a bit-error rate of less than \10^-12 for \2^7 -\1 pseudorandom binary sequence. As a result, the proposed transceiver achieves energy efficiency of 6.26 pJ/bit. [ABSTRACT FROM PUBLISHER]

We propose optimized ON/OFF states of the backscattered amplitude shift keying (ASK) modulator for the passive RF identification (RFID) tags. This takes into account both the reader receiver sensitivity and tag antenna mismatch conditions. Based on the analysis of the, power transfer between the passive RFID tag and reader, we derived the optimum configuration of the ASK modulator. It maximizes the harvestable power to enhance, the identification range between the tag and reader. The performance of the proposed modulator configuration was superior to the conventional scheme. We also developed an optimization procedure of the modulator for a given receiver sensitivity of the reader and various antenna mismatch conditions of the tag. [ABSTRACT FROM AUTHOR]