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In this article, a moving accumulative sign filter (MASF) voter model and a low-power serial voting circuit are proposed for high-speed clock data recovery (CDR). Different from the previously reported parallel voter and moving average majority voter (MV), the proposed design is based on the MASF algorithm and adopts a two-stage voting structure. Only D-flip-flop (DFF) and basic logic gates are used to realize the serial voting function of the four continuous lead/lag/hold decision signals. The proposed MV realizes the signal processing of the four-phase error information without using traditional gain and quantization operations. In addition, by eliminating the redundant output state, the input noise of the digital filter of CDR can be reduced, which could also reduce the power consumption of the subsequent circuits due to less logical flips. As a result, the proposed serial MV can operate at a half baud rate in a high-speed CDR and it can reduce the chip area by removing the demultiplexer unit and the moving average filter. The proposed MV circuit is implemented for a high-speed CDR using a 40-nm CMOS process, which shows a 12-GHz maximum operating speed. The measured power consumption of the whole voter at 10 GHz is only 0.55 mW and the core chip area is $8.6\,\times \,25.4\,\,\mu \text{m}^{2}$. [ABSTRACT FROM AUTHOR]

Spread-spectrum clocking (SSC) is an active solution to attenuate electromagnetic interference (EMI) in Gb/s serial communication systems by slightly modulating the phase-locked loop (PLL) output clock frequency. This article presents a phase-compensated spread-spectrum clock generator (SSCG) with the state-of-the-art EMI reduction and clock rms jitter performance. A 32-slice scaled resistor-based buffer is proposed to realize the phase interpolator (PI). The proposed design has no static current and low complexity without active device matching requirement. The 32-slice PI structure can achieve a simulated 22-dB EMI reduction with a 32-step triangular modulation profile. The proposed SSCG chip with a charge-pump-based fractional- $N$ radio frequency (RF)-PLL and a source-series-terminated (SST) driver is fabricated using a 55-nm CMOS process. Measurement result shows that EMI reduction of the 5-GHz output clock power spectrum is 19.44 dB under 0.5% down-spread. The rms jitters with SSC-off and SSC-on, adopting a second-order clock recovery in oscilloscope, are 630 and 640 fs, respectively. The normalized power consumption is 9.3 mW/GHz, and the core area occupation is 0.092 mm2. [ABSTRACT FROM AUTHOR]