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This article presents a power amplifier (PA) design, which consists of eight class-D PA units on a single 28-nm CMOS die and a coupled-line power combiner on printed circuit board. The PA utilizes tri-phasing modulation, which combines polar and outphasing components in a way that eliminates linearity-degrading effects of multilevel outphasing while maintaining the back off efficiency.Each PA unit contains a cascoded output stage with a 3.6-V supply voltage, and multilevel operation is enabled by ON/OFF logic circuitry. Our analysis shows that the choice of power-combiner type is vital for reducing PA supply and ground ripple and thus ensuring reliable operation.Accordingly, the power combiner is implemented with extended Marchand baluns, which consist of input transmission lines and coupled-line sections. Unlike the original Marchand balun, our new topology is feasible for implementation under the layout restrictions caused by the multiple-unit PA on a single die.Measurement results show the PA achieving a peak output power of 29.7 dBm with a 34.7% efficiency, and operation with aggregated Long Term Evolution (LTE) signals at 1.7-GHz carrier frequency is verified with bandwidths up to 100 MHz. [ABSTRACT FROM AUTHOR]