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In this paper, the stress memorization technique (SMT) effects upon ultra-wideband RF switch performance are investigated for the first time. Low insertion loss (IL), high isolation, ultra-wideband (dc to 50 GHz) single-pole double-throw (SPDT), and single-pole four-throw (SP4T) switches designed with commercial 0.13- \mu \textm high-resistivity (HR) trap-rich SOI technology with/without SMT are presented and investigated. 2.5 V nMOS transistor ( Lg = 0.2~\mu \text{m} ) with low R\mathrm{\scriptscriptstyle ON} {^\ast} C\mathrm{\scriptscriptstyle OFF} from GF 130RFSOI PDK is used. It is found that channel mobility of switch transistor is improved by SMT and thus switch performance can be further improved. Moreover, the impact of transistor channel length, which has dominant effects on both IL and isolation of the switches, under different gate bias on switch performance are also studied and verified experimentally. Low measured IL of less than 2.1 dB and good isolation of better than 27 dB from dc to 50 GHz are obtained for the SPDT switch. For SP4T switch, the measured IL of less than 2.6 dB and isolation of better than 27 dB are achieved from dc to 35 GHz. The active chip areas of designed SPDT and SP4T switches are compact with size of only 0.214 \times 0.19~\text mm^2 and 0.36 \times 0.19~ \text mm^2 , respectively. [ABSTRACT FROM AUTHOR]

A fully integrated 93.4–104.8-GHz 57-mW fractional- ${N}$ cascaded phase-locked loop (PLL) with true in-phase injection-coupled quadrature voltage-controlled oscillator (QVCO) is reported. By cascading the fractional- ${N}$ PLL and the subsampling PLL, good phase noise, high resolution, and wide acquisition range are achieved simultaneously. The transformer-based true in-phase injection coupled technique is adopted in the QVCO to obtain both low phase noise and low-power consumption. The proposed cascaded PLL was fabricated in a 65-nm CMOS technology with silicon size of 0.88 mm2. The measured phase noise of QVCO and PLL is −113.26 and −106.63 dBc/Hz at 10-MHz offset, respectively. The FOM and FOMT of the QVCO at 10-MHz offset are −178.4 and −180.0 dBc/Hz, respectively. The frequency resolution of the 100-GHz output is less than 3.6 kHz. [ABSTRACT FROM AUTHOR]

Quasi-lumped-element low-pass filter (LPF) and high-pass filter (HPF) based on substrate-integrated suspended line (SISL) technology are presented in this paper. Double interdigital capacitor, which has advantages of high capacitance density and high quality factor, is analyzed and designed to minimize the filter size. Based on the theoretical analysis, quasi-lumped-element SISL LPF and HPF prototypes are designed. The experimental results show that the SISL LPF achieves ultra-wide stopband up to 24 \textfc ( \textfc is the cut-off frequency) with compact size of 0.180~\lambda g \times 0.082~\lambda g ( \lambda g is the guide wavelength at \textfc) . The SISL HPF features the low insertion loss of only 0.3 dB, while the size is only 0.108~\lambda g \times 0.085~\lambda g . Moreover, the methods of substrate excavation and packaging optimization are proposed to further enhance the performance of SISL LPF and SISL HPF. By doing so, the stopband of SISL LPF is further extended to 32 fc, and the insertion loss of SISL HPF is significantly reduced to 0.1 dB. [ABSTRACT FROM PUBLISHER]