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Two fully integrated chipsets covering the entire E-band frequency range, 71–76/81–86 GHz, have been demonstrated. These designs, which were implemented in 0.13-\mu\m SiGe BiCMOS technology, use a sliding IF superheterodyne architecture. The receiver (Rx) chips include an image-reject low-noise amplifier, RF-to-IF mixer, variable gain IF amplifier (IF VGA), quadrature IF-to-baseband (BB) de-modulator, tunable BB filter, phase-locked loop (PLL) synthesizer, and a frequency quadrupler. At room temperature the Rx chips achieve a maximum gain of 73 dB, 6-dB noise figure, better than -\12-dBm input third-order intercept point, more than 65-dB dynamic range, and consume 600 mW for lower band (LB) (71–76 GHz) and higher band (HB) (81–86 GHz) alike. The transmitter (Tx) chips include a power amplifier, image reject driver, variable RF attenuators, power detector, IF-to-RF up-converting mixer, IF VGA, quadrature BB-to-IF modulator, PLL, and a frequency multiplier. The Tx chips achieve a power 1-dB compression point (P1dB) of 17.5/16.6 dBm, saturated power (Psat) of 20.5/18.8 dBm on a single-ended output, up to 39-dB gain with an analog controlled dynamic range of 30 dB, and consumes 1.75/1.8 W for the LB and HB, respectively. This state-of-the-art performance enables the usage of complex modulations and high-capacity transmission. [ABSTRACT FROM PUBLISHER]

Proposes a peeling algorithm for extraction of the heterojunction bipolar transistor (HBT) small-signal equivalent circuit. Accuracy of direct extraction for the determination of equivalent-circuits of HBT; Determination of the accuracy and robustness of the whole algorithm; Extraction of all the elements using exact closed-form equations.