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A 79-GHz adaptive-gain and low-noise ultra-wideband radar receiver RF front-end integrated circuit in 65-nm CMOS is presented in this paper. The receiver consists of an adaptive-gain low-noise amplifier (AGLNA) and a ${ g}_{ m}$ -boosted sub-harmonic mixer (SHM). The proposed AGLNA controls the gain with adaptive biased circuits, which lowers the gain as the received signal power increases to provide wide dynamic range to the radar receiver without any external controls. We analyzed the input impedance of a cascode amplifier with a parallel resonant inductor, which improves the noise figure. The proposed ${ g}_{ m}$ -boosted SHM uses a transformer-based feedback network with NMOS bleeding circuits to provide a high conversion gain. The SHM was designed to use a differential local oscillator (LO) signal to have a simple structure and operate at low LO power. The measured conversion gain range was from 16 to $-{\hbox{7.5 dB}}$ with a received power range from $-{\hbox{45}}$ to $-{\hbox{5 dBm}}$ at 79.5 GHz. The measured noise figure was 10.5 dB and the measured 2LO-to-RF isolation was 70 dB. The chip area is ${\hbox{0.47}}\times {\hbox{1.23}}~{\hbox{mm}}^{2}$ .

This paper presents a fully integrated W-band 4-GHz bandwidth (BW) pseudo-noise (PN)-coded pulse compression radar transmitter (TX) in a CMOS technology. The PN-coded pulse compression scheme is adopted to obtain high spectral density and to lower the TX leakage using a 63-bit PN code generator based on linear feedback shift registers. We propose a sub-harmonic pumped pulse former and a pulsed power amplifier for high TX efficiency with the suppression of local oscillator (LO)/2LO leakage. A frequency synthesizer including a frequency divider chain generates a sub-harmonic LO signal, as well as a 5-GHz digital clock. Digital blocks with the PN-code generator are synchronized with the clock signal, which makes all pulses start with the same phase. The proposed TX achieves 14.5-dBm maximum output power with the tuning range of 75–81.5 GHz, and the phase noise is ${-}{\hbox{95.2}}$ dBc/Hz at a 1-MHz offset in the range of LO frequencies. In pulse mode, it generates a 4-GHz BW RF pulse signal, which corresponds to a range resolution of 7.5 cm, and the average dc power dissipation is 160 mW.

This paper presents a 77-GHz CMOS power amplifier (PA) with a parallel power combiner based on a transmission-line transformer (TLT). An inter-stage matched cascode power cell structure is applied to obtain high output power and efficiency, where a simple matching network between the common-gate and common-source stage is introduced. The parallel power combiner based on a broadside-coupled TLT is analyzed and compared with a series power combiner. The PA is fabricated using a 65-nm RF CMOS process. It achieves the saturated output power of 15.8 dBm, the power-added efficiency of 15.2%, and the power gain of 20.9 dB with a supply voltage of 2.0 V at 77 GHz.