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The effects of the nonlinear drain-to-source capacitance ( $C_{\mathrm {DS}}$ ), or the varactor effect, on the operation of continuous-mode class-B/J power amplifiers (PAs) are described in terms of the mathematical analysis as well as experimental validation. The nonlinear $C_{\mathrm {DS}}$ generates harmonic current when the class-B/J drain voltage is applied across it, modifying the theoretical load trajectories on the Smith chart. This is shown to significantly deviate from the continuous-mode assertion of constant power and efficiency. A novel measurement approach called voltage–pull is used to investigate the effects of the second harmonic generation by the varactor in a class-B/J PA mode. Theoretical and experimental results showed the nonlinear $C_{\mathrm {DS}}$ degrades the drain efficiency compared to class-B on one half of the class-B/J design space while improving the other half due to the energy upconversion and downconversion, respectively. This paper provides an approach for die nonlinear characteristic optimizations for transistor manufacturers.

A novel graphical power amplifier (PA) design tool, the “clipping contour,” is introduced and described. Using the now well-publicized continuous Class-B/J voltage waveform formulation as a starting point, a process is derived that allows contours to be constructed on a Smith chart that define the “zero-grazing” fundamental and harmonic impedance conditions. Theoretical equations are defined and solved whereby the contours can be drawn in real time in a computer-added design environment. A key and novel result from this theory is the definition of a 2-D harmonic design space that opens up rapidly as small concessions from optimum power and efficiency matching conditions are made. A design example is described and fabricated, which demonstrates the utility of using the second harmonic clipping contour during the PA design process. A 10-W GaN demonstrator gives measured continuous wave power > 8.5 W, efficiency > 60%, and better than -30-dB adjacent channel power ratio over a bandwidth of 1-2.9 GHz.

Recently, X -parameters have been introduced to model active device nonlinear behavior. In addition to providing a measurement-based tool to numerically predict nonlinear device behavior in computer-aided design, they can also provide the designer of nonlinear circuits an analytical design tool. Exploiting this design tool aspect, this work presents an application that combines the nonlinear vector network analyzer PNA-X and a passive tuner to extract a transistor load-independent X -parameter model, focused around targeted circuit impedances for optimal performance. Furthermore, an experimental search algorithm, based on X -parameters analytical computations and developed by Peláez-Pérez , has been used and experimentally validated in this paper, aimed to speed up the characterization and design process, minimizing the number of load-pull measurements necessary to provide an accurate transistor X -parameter model for use in analytical and/or numerical circuit design. Ministerio de Ciencia e Innovación | Ref. TEC2011-29264-C03-03

In this paper, an extended version of the continuous class-F-1 mode power amplifier (PA) design approach is presented. A new formulation describing the current waveform in terms of just two additional parameters, while maintaining a constant half-wave rectified sinusoidal voltage waveform, allows multiple solutions of fundamental and second-harmonic impedances that provide optimum performance to be computed. By varying only the imaginary parts of fundamental and second-harmonic impedances, it is shown that output performance in terms of power and efficiency is maintained constant and equal to that achievable from the standard class-F-1 . Indeed, when presenting resistive second-harmonic impedances, it will be demonstrated that the fundamental load can be adjusted to maintain satisfactory output performances greater than a certain predetermined target value. The measurements, conducted on a GaAs pHEMT device at 1 GHz, show a good agreement with the theoretical analysis, revealing drain efficiencies greater than 70% for a very large range of load solutions, which can translate to an ability to accommodate reactive impedance variations with frequency when designing broadband PAs.

Mathematical analysis of Doherty amplifiers have assumed many simplifications. Most notably, the peaking amplifier does not contribute power into the load and the peaking stage has an observed impedance of infinity. This paper will show that these simplifications impair the performance of a single-input Doherty amplifier and that phase tuning for compensation is needed to improve the overall system performance. The dual-input Doherty amplifier is capable of overcoming the limitations of power-dependent phase imbalance and phase compensation lines at the input of the peaking stage; however, the characterization of such an architecture is not straightforward. A new measurement technique is proposed to measure dc current, dc voltage, and output power levels to allow unique characterization of a dual-input Doherty amplifier. Phase compensation lines at the input of the peaking amplifier will be shown to be not required, as long as correct offset lines are calculated for both the carrier and peaking stage and that the λ/4 transmission-line length is not necessarily required for active load-pull. Results of a dual-input inverse load modulated Doherty amplifier are presented where the peaking stage delivers 10 dB less of maximum output power than the carrier, while still maintaining Doherty behavior. The peaking stage can therefore be implemented with a smaller device than the carrier.

The extended continuous class-F mode RF power amplifier (PA) is presented for the first time. The introduction and experimental validation of this novel PA mode demonstrates a new design space over a wide band of frequencies. This paper will show that high output power and drain efficiency, equivalent to the class-F mode, can be maintained by varying the reactive components of fundamental and second harmonic impedances in accordance with the new formulation of the voltage waveform. Additionally it will be shown that, by varying both phase and magnitude of the fundamental and second harmonic impedances, a yet wider design space can be achieved, where the efficiency is maintained at a level greater than a certain target value. For the validation of this new theory, an experimental investigation was carried out on GaAs pseudomorphic HEMT devices and demonstrates that high output power and drain efficiency between 75%-83% can be achieved over a wide range of fundamental and second harmonic loads.

After calibration, since the systematic imperfections of the envelop load-pull (ELP) components were now fully accounted for, the user is able to rapidly set accurate terminations with full Smith chart coverage. This functionality has been achieved by optimizing the hardware configuration of the envelop load-pull concept. Development of a system whose systematic errors could be described by a magnitude invariant error flow model was critical. As a consequence, a robust calibration mechanism, that is analogous to the one-port error correction of a vector network analyzer, was exploited and comprehensively verified. After calibration, since the systematic imperfections of the ELP components were now fully accounted for, the user is able to set accurately terminations with full Smith chart coverage. Finally, measurements on commercially available transistor devices are presented that verify the rapid nature, accuracy, flexibility, reliability, and ease of calibration of the multiharmonic load-pull system.

The design and implementation of a class-J mode RF power amplifier is described. The experimental results indicate the class-J mode's potential in achieving high efficiency across extensive bandwidth, while maintaining predistortable levels of linearity. A commercially available 10 W GaN (gallium nitride) high electron mobility transistor device was used in this investigation, together with a combination of high power waveform measurements, active harmonic load-pull and theoretical analysis of the class-J mode. Targeting a working bandwidth of 1.5-2.5 GHz an initial power amplifier (PA) design was based on basic class-J theory and computer-aided design simulation. This realized a 50% bandwidth with measured drain efficiency of 60%-70%. A second PA design iteration has realized near-rated output power of 39 dBm and improved efficiency beyond the original 2.5 GHz target, hence extending efficient PA operation across a bandwidth of 1.4-2.6 GHz, centered at 2 GHz. This second iteration made extensive use of active harmonic load-pull and waveform measurements, and incorporated a novel design methodology for achieving predistortable linearity. The class-J amplifier has been found to be more realizable than conventional class-AB modes, with a better compromise between power and efficiency tradeoffs over a substantial RF bandwidth.

This paper presents a comprehensive study on the effective utilization of large-signal measurement data in the nonlinear computer-aided design (CAD) process. To achieve this goal two distinctive, yet mutually complementary, approaches have been integrated. Measured nonlinear data was, in the first instance, directly integrated into a nonlinear CAD simulator, and in the second instance, utilized for a direct extraction of behavioral model parameters. The formulation of the developed model is based on the polyharmonic distortion approach. The combination of both the direct utilization of nonlinear data and the subsequent model generation into an integrated nonlinear design procedure offers rapid, yet reliable, deployment of the CAD-based design environment for complex large-signal simulations.

A measurement system combining vector corrected waveform measurements with active harmonic load-pull extends, for the first time, real-time experimental waveform engineering up to the 30-W power level. The vector correction procedure is presented in this paper. A novel harmonic load-pull approach based on the real-time measurement capability of the system is demonstrated on a 4-W LDMOS device. A 20% increase in maximum output power to 4.7 W without degrading gain and efficiency is realized. Waveform analysis at various drive and load conditions directly identifies nonlinear capacitance effects being a key design issue for the design of highly efficient power amplifier.

An accurate database for active and passive MMIC components valid up to millimeter-wave frequencies has been established. The CAE models for the transistors and the passive CPW-components; which include the coplanar T-junction, are derived from on-wafer S-parameter measurements up to 63 GHz. For noise modeling of the MODFETs up to millimeter-wave frequencies, an approach based on the temperature noise model reported by M.W. Pospiezalski (1989) has been used. The parameter T/sub d/, which is required for the temperature model, is extracted from on-wafer noise parameter measurements up to 18 GHz. Using this database, the authors have designed and fabricated low-noise V-band two-stage amplifiers, using pseudomorphic MODFETs on a GaAs substrate, which have a performance of 10.5-dB gain and 5.2-dB noise figure at 58.5 GHz. Very good agreement between simulated and measured MMIC gain and noise performance is achieved up to V-band. >

Double heterojunction AIGaAs/InGaAs/GaAs modulation-doped field effect transistors (MODFET's) using lattice-strained AIGaAs/InGaAs/GaAs layer structure have been fabricated and evaluated at microwave frequencies for various bias conditions. MODFET's with a 1-µm gate length show a room-temperature peak extrinsic dc transconductance (g/sub m/) of 400 mS/mm with a full channel current of 610 mA/mm. For 0.3-µm-gate MODFET's an extrinsic dc g/sub m/ of 505 mS/mm and a full channel current of 720 mA\mm were obtained. Devices having a 1-µm gate length show a maximum available gain cutoff frequency (f/sub max/) of 85 GHz and a current-gain cutoff frequency (f/sub T/) of 22 GHz from S-parameter measurements. The 0.3-µm devices show an f/sub T/ of 45 GHz and an f/sub max/ of 120 GHz. Bias-dependent equivalent circuit models are also discussed.