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Convolutional neural networks (CNNs) are quickly becoming an attractive solution for autonomous vehicles, military weapons, and space exploration. Thanks to their reconfiguration ability, design flexibility, and low power consumption, field-programmable gate arrays (FPGAs) have become a promising candidate for CNN accelerators. However, FPGAs have been proven to be susceptible to radiation-induced single-event upsets (SEUs). One goal of this article is to analyze the impact of quantization on the reliability of CNNs in FPGAs. Therefore, we performed quantization on ZynqNet without affecting its classification accuracy. Meanwhile, we implemented the triple modular redundancy (TMR) version of ZynqNet and we also evaluated the effects of SEUs on these CNNs through both fault injections and neutron exposures. Fault injection results show that TMRed ZynqNet reduces the soft error rate (SER) by 33.59% with a circuit area increase of 111.92% when compared with the standard ZynqNet. The experimental results demonstrate that the quantized ZynqNet reduces the SER by 71.36% with a circuit area reduction of 44.76% when compared with the standard ZynqNet. These results confirm that quantization does contribute to SER reduction of the neural networks. In addition, the operating system on the processing system (PS) side was also found to be highly sensitive to SEUs, and, thus, mitigation techniques should be applied. [ABSTRACT FROM AUTHOR]

For area and power constraint applications in mission critical systems, the traditional fast Fourier transform (FFT) design requires huge hardware resources for data processing. In this article, we, therefore, present a low-overhead radix-2 FFT design that reduces hardware resources by simplifying the first two stages of the butterfly computations. Both the proposed design and the traditional design have been implemented in the MicroZus-20 (XC7Z020) platform. Their single-event performances have been compared through both fault injections and neutron exposure, and the experimental results demonstrate that the proposed design reduces the soft error rate by 53.8%. Also, the proposed FFT reduces the hardware resource consumption and circuit area by 64.8% when compared with the traditional design. [ABSTRACT FROM AUTHOR]

This paper investigates total ionization dose (TID) effects on the electrical characteristics of Al2O3-/HfO2-/Al2O3-based charge trapping memory (CTM) devices by 10-keV X-ray. The Al2O3 layers serve as tunnel and blocking oxides, respectively, while HfO2 layer acts as charge-trapping layer. The C–V curves in pristine state shifted toward negative direction, but dc memory window almost kept the same after irradiation. Storage electrons decreased significantly with accumulated dose and reached approximately the same final value regardless of initial values. The impact of TID irradiation on program and erase conditions is also investigated. The program ability still worked well, but the erase ability disappeared gradually after irradiation. The physical mechanisms triggered by TID irradiation on Al2O3-/HfO2-/Al2O3-based CTM structure are discussed in detail with energy band diagrams. [ABSTRACT FROM PUBLISHER]

A flip-flop circuit hardened against soft errors is presented in this paper. This design is an improved version of Quatro for further enhanced soft-error resilience by integrating the guard-gate technique. The proposed design, as well as reference Quatro and regular flip-flops, was implemented and manufactured in a 65-nm CMOS bulk technology. Experimental characterization results of their alpha and heavy ions soft-error rates verified the superior hardening performance of the proposed design over the other two circuits. [ABSTRACT FROM AUTHOR]

In this paper, a variety of flip-flop (FF) designs fabricated in a commercial 28-nm Fully-Depleted Silicon on Insulator (FDSOI) technology are evaluated for their single-event upset performance with ions and pulsed laser experiments. These FF designs consist of unhardened DFF, hardened DFF with stacked transistors in the inverters, and the layout-optimized DFFs. These DFFs were exposed to alpha particles and heavy ions (HIs). None of the hardened DFFs exhibit any errors up to a Linear Energy Transfer (LET) of 50 MeV*cm2/mg under normal irradiation, and a layout-based hardened DFF started to see errors at a LET of 50 MeV*cm2/mg with the tilt angle of 600. The testing data substantiates effective SEU reduction of these hardened designs. Two-photon absorption (TPA) laser experiments were carried to test these DFF designs, and the results showed that pulsed laser may not be a valid tool to evaluate the FFs designed with nano-scale SOI stacked structures. This brings new challenges in laser hardness assurance for RHBD designs. [ABSTRACT FROM PUBLISHER]

In this paper, we present D flip-flop, Quatro, and stacked Quarto flip-flop designs fabricated in a commercial 28-nm CMOS FDSOI technology. Stacked-transistor structures are introduced in the stacked Quatro design to protect the sensitive devices of the original structure. Striking either of the stacked devices will not upset the latch because the conduction path to the supply rail is still cut off by the other off-state device. The irradiation experimental results substantiate that the stacked Quatro design has significantly better SEU tolerance (e.g., higher heavy ion upset Linear Energy Transfer threshold and smaller cross-section data) than the reference designs. It introduces power and area penalties because the proposed design duplicates and stacks two sensitive PMOS devices. Additionally, the impact of technology scaling on Quatro in various technology nodes (130-nm, 65-nm, and 40-nm) has been studied suggesting decreasing upset threshold and decreasing cross-section data. [ABSTRACT FROM AUTHOR]

A guard-gate based flip-flop circuit temporally hardened against single-event effects is presented in this paper. Compared to several existed techniques, the organization of components inside the proposed design allows the improved performance– only one $\tau $ (the maximum width of a single-event transient (SET) to tolerate) is added into the setup time. A previously reported low-power delay element is applied, which helps make the proposed design power-efficient. The proposed design was implemented in a 65 nm CMOS bulk technology. Alpha and heavy-ions radiation experiments were performed to characterize its soft-error rates. Experimental results show that the proposed design presents no error with LETs up to 37.3 MeV-cm2/mg. Simulation results from the TFIT further validate the experimental results. [ABSTRACT FROM AUTHOR]

Two types of clock networks including clock mesh and a buffered clock tree in a daisy-chain style were utilized to synchronize 5 DFF chains and fabricated in a 28 nm bulk CMOS technology. Alpha and proton particles did not trigger any errors indicating the significant single event tolerance of these clock networks. Heavy ion results for the data input pattern of checkerboard (alternate 1 and 0) are presented showing few occurrences of burst errors induced by single event transients (SETs) in the buffered clock tree at relatively high LET values. The same phenomena were observed in laser tests. Clock mesh is therefore proven to be less sensitive to SETs, if pre-mesh drivers do not generate transients. Otherwise, clock mesh possesses lower tolerance, as demonstrated in previous work. Moreover, these burst errors occurred (1) simultaneously in a DFF chain and its subsequent chains, or (2) in a single chain with subsequent chains unaffected. The distinct mechanisms of these burst errors were found to be the electrical masking effect of the daisy-chain clock buffers. [ABSTRACT FROM AUTHOR]

This paper presents an SEU-tolerant Dual Interlocked Storage Cell (DICE) latch design with both PMOS and NMOS transistors in the feedback paths. The feedback transistors improve the SEU tolerance by increasing the feedback loop delay during the hold mode. The latch design was implemented in a shift register fashion at a 130-nm bulk CMOS process node. Exposures to heavy-ions exhibited a significantly higher upset LET threshold and lower cross-section compared with the traditional DICE latch design. Performance penalties in terms of write delay, power, and area are non-significant compared to traditional DICE design. [ABSTRACT FROM PUBLISHER]

This paper presents a new SEU-tolerant latch design based on Quatro and NMOS feedback transistors. By using these feedback transistors, the SEU susceptibility is decreased because of the cutoff feedback loop. Simulation results demonstrate that the proposed design is immune to static single node upsets. The proposed latch and the reference Quatro were designed and fabricated on a 130 nm process. The test chip was exposed to heavy ions at the TAMU Cyclotron facility. The testing results show that the proposed design has a higher upset LET threshold and lower cross-section when compared to the reference latch. Its lower SEU vulnerability comes with small area penalty. [ABSTRACT FROM PUBLISHER]