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Heavy-ion-induced soft and hard breakdown are investigated in thin gate oxides as a function of linear energy transfer, fluence, and voltage applied during irradiation. It is found that postirradiation oxide conduction is well described by the Sune quantum point contact model.

Proton damage is investigated for several types of modern light-emitting diodes (LEDs), examining the damage from the standpoint of older models based on lifetime degradation as well as the simpler method of normalized degradation. An empirical model is developed to describe injection-enhanced annealing in amphoterically doped LEDs. Experimental results on "aged" devices show that wearout degradation does not decrease the sensitivity of devices to radiation damage.

Fundamental differences in design influence the way that linear and digital optocouplers are degraded by radiation. Linear optocouplers are more affected by current drive conditions because the detector operates in a high-injection region when the LED produces normal light output, and do not have the extra operating margin that is inherent in digital optocouplers. Although LED degradation is often the dominant degradation mechanism in space environments, degradation of optocouplers with improved LEDs is limited by photoresponse degradation. Phototransistor gain has a relatively minor effect except at very high radiation levels.

Proton tests of linear integrated circuits have identified devices where significantly more damage occurs at equivalent total dose levels with protons than with gamma rays. The difference is attributed to displacement damage, and it can be important for hardened devices as well as for unhardened technologies. Proton testing may be required for applications of circuits that use substrate and lateral pnp transistors in critical circuit functions where protons comprise a significant fraction of the space environment.

Single-event upset is investigated for optocouplers using heavy ions. The threshold LET for optocouplers with internal high-gain amplifiers is very low, causing output transients to occur even when the optocouplers are irradiated with short-range alpha particles. Although previous work with high-energy protons showed that transients were caused by charge collected in the large-area photodetector, transients generated in the high-gain amplifier make a significant contribution to the total cross section when optocouplers are irradiated with heavy ions. The transient pulse width increases with LET, exceeding 400 ns for long-range particles above 7 MeV-cm/sup 2//mg. This is about an order of magnitude greater than the pulse width that occurs when they are irradiated with protons. The ion range must exceed 50 /spl mu/m to characterize the cross section and pulse width in these devices.

Spacecraft performance requirements drive the utilization of commercial-off-the-shelf (COTS) components and emerging technologies in systems. The response of these technologies to radiation is often complex. This engenders a set of emerging radiation hardness assurance (RHA) issues which include displacement damage in optocouplers, high-precision and hybrid devices, enhanced low dose rate (ELDR) and proton damage enhancement (PDE) in linear circuits, linear transients, and catastrophic single event effects (SEEs) phenomena. NASA has developed an approach to designing reliable space systems which address these emerging RHA issues. This programmatic methodology includes hazard definition, hazard evaluation, requirements definition, evaluation of device usage, and application of radiation engineering techniques with the active involvement of designers. Risk assessment is an integral constituent in the approach as is an established program to assess future technology needs for programs.

A hardness assurance test approach has been developed for bipolar linear circuits and devices in space. It consists of an initial test for dose rate sensitivity and a characterization test method to develop the conditions for a lot acceptance test at high dose rate. For parts with adequate design margin and/or well behaved parts a generic elevated temperature irradiation test is proposed.

Dose-rate effects are studied in shallow trench isolation regions. Increased damage is observed at low dose rate, with a different dose dependence compared to tests done at high dose rate. A three-dimensional modeling program was used to show that charge trapping occurs much deeper in the trench region when sufficient charge is present to reduce the field in the trench.

The authors examine laser simulation of single-particle effects in some detail, investigating the effects of doping density and charge collection depth on funneling and charge collection, and accounting for the spreading of the focused laser beam within the silicon material. Calculations using the device simulation code PISCES are compared for heavy ions and lasers to investigate the accuracy of laser simulation of single-particle effects. Experimental charge collection measurements with heavy ions are used to establish the accuracy of the PISCES simulations. >

The ion-induced gate edge effect and excess charge collection effect present in GaAs MESFETs are not present in InP and GaAs HFETs. An SEU (single event upset) characterization study shows that these devices can provide an SEU rate which is lower than that of unhardened CMOS. >

An ion induced charge collection study, using an array of GaAs enhancement-mode MESFET geometries, has identified two primary excess charge collection effects, a fringe field effect and a gated channel effect. The introduction of a buried p-layer was found to suppress the fringe field effect, which resulted in a reduction in the maximum excess charge collected. The LET threshold for SEU was similar for both processes. For the devices used in this study, the results suggest that the gated channel effect is primarily responsible for the low SEU LET threshold. >

Special test structures fabricated with three different CMOS processes were used to investigate the effect of elevated temperature on single-particle latchup. The latchup threshold was strongly affected by contact geometry, and its temperature dependence is consistent with a model based on triggering of the vertical parasitic transistor. Threshold LET values decreased by about a factor of 2.5 at 125 degrees C relative to room temperature values for all three processes. Saturation cross sections exceeded the isolation well area for the two bulk processes because of diffused charge. Laser studies showed that latchup could be triggered by strikes outside the isolation well, consistent with the diffused charge mechanism. These same mechanisms were consistent with measurements of the latchup cross section of a static CMOS RAM. >

Single-particle latchup in bulk CMOS was examined using heavy ions, a californium fission source, and a pulsed laser. Experiments with the laser demonstrated that latchup triggering was caused by secondary photocurrent in either the vertical or lateral parasitic transistor. Charge diffusion is shown to be important for bipolar transistor responses in latchup, which in turn makes it important to have uniform charge deposition for depths of 10 mu m or more. Californium sources have insufficient range, which causes cross sections measured with californium to be much lower than cross sections from heavy ion experiments. >

The single-event upset (SEU) characterization of GaAs enhancement/depletion (E/D) MESFET logic circuits was experimentally performed for five different logic families. The results indicate a large charge collection volume, independent of the logic family. These results can be attributed to a gate edge effect and an enhanced source-drain charge collection mechanism. The consequence of these effects is to increase the upset rate in space by more than two orders of magnitude. Soft-error rates were estimated for each logic family and spanned the range from 2.3*10/sup -3/ to 4.7*10/sup -4/ errors/bit-day. >

Low- and high-dose-rate testing results are compared for CMOS technologies. The long-term experiments extend over time periods of more than one year so that comparisons could be made over time frames more nearly like those in the space environment. High-temperature annealing is evaluated as a means of accelerating the annealing time and predicting low-dose-rate results. The data on hardened CMOS and CMOS/SOS devices show that for these particular processes, annealing at 100 degrees C did not accelerate trapped hole annealing. Differences between expected and actual results are identified, and recommendations are made for improving test procedures. >

Topological factors that affect latchup were investigated using test structures fabricated in two different CMOS foundries. The geometry of isolation well contacts was found to have a large effect on photocurrent responses because of the effect of the lateral resistance of the well. Experiments that delayed the application of bias until time periods long after the radiation pulse subsided showed that latchup would still occur, with relatively small increases in the radiation intensity required to induce latchup until the delays exceeded several microseconds. This shows that the fast transition of the radiation pulse is not required to trigger latchup, and it also shows how latchup can occur at high intensities after internal voltages collapse to near zero at short times. Latchup tests of a 64K SRAM (static random-access memory) revealed a latchup window that was caused by the presence of two different internal latchup paths with different radiation triggering levels and holding voltages. Data on this device and several MSI devices show how the power-supply current-surge characteristics can be used to select radiation test levels to minimize interference from latchup windows. >

A simple model for interpreting and extrapolating time-dependent effects in the irradiation of microelectronic devices is tested by fitting its predictions to published and previously unpublished experimental data. The goal is to evaluate the applicability of such a model to hardness assurance testing in cases where defect growth and annealing processes (time-dependent effects) are significant. Data are presented indicating hole annealing times varying by more than six orders of magnitude. The implications of the large variation in hole annealing times for hardness assurance testing are explored. >

A lumped-model approach is used to determine three-dimensional effects that often dominate latchup behavior in complex integrated circuits. A preprocessor is used that automatically generates a SPICE-compatible file of up to several thousand elements from a basic description of the topology and physics of local structures. The results show that internal potential drops in the substrate and isolation wells are much larger than the metallization resistance contribution for devices with asymmetrical topology. The work also shows that alterations in the back contact, such as partial removal of the central portion for backside laser simulation, increase lateral voltage drops in the substrate by more than one order of magnitude, substantially changing the latchup characteristics. The model can be used to calculate distributed potentials that are important for latchup and the latchup window effect and to determine the effect of metal shadowing or nonuniform carrier generation when laser simulation is used. >