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Single-event transient (SET) glitches can be modified by body-biasing controlling techniques. In this paper, a body-biasing configuration is proposed in combinational circuits, which plays no role during devices’ normal operation, but significantly mitigates SET disturbance as ion strike happens. NOR cell chains and NAND cell chains are served as cases to investigate the impact of the proposed configuration on SET vulnerabilities under two groups of heavy-ion experiments. Experimental data illustrate that transistors with body tied to source (BTS) significantly reduce the SET cross-section compared to the normal designs. The physical mechanism of the proposed technique is quantitatively analyzed in detail.

In this article, five different cell placement structures of a vertical inverter chain were designed in a commercial bulk FinFET technology to investigate the effect of cell placement on a single-event transient (SET) pulse. 3-D TCAD mixed-mode simulation indicated that the cell placement has a significant effect on SET pulsewidths. Heavy-ion experiments at Cyclotron in the China Institute of Modern Physics in Lanzhou also indicated that the effect of cell placement on the SET pulse is obvious. The experiment also indicated that the effect of cell placement on P-hit SET is larger than that on N-hit SET, and charge sharing in vertical was becoming as important as that in horizontal.

In this paper, an “S-like” inverter chains (SLIC) test structure is designed for the separation measurement of $N$ -hit and $P$ -hit charge sharing. The heavy-ion experiments were performed in 65-nm bulk dual-well and triple-well technology, and the $N$ -hit and $P$ -hit pulse quenching (PQ) span is attained. The results has verified the ability of the “SLIC” test structure to characterize $P$ -hit and $N$ -hit PQ, and the results also indicate that the N+ deep well can enhance the action extent of $N$ -hit charge sharing greatly though it will reduce the action extent $P$ -hit charge sharing.

In this paper, a novel uniform vertical inverter chains (UniVIC) single event multiple transient (SEMT) test structure is proposed for the first time. Charge sharing between standard inverters is measured for the first time experimentally. The heavy-ion experiment results in 65 nm bulk CMOS process indicate that charge sharing can impact three transistors at most. At the same time, the occurring probability of charge sharing is attained for the first time experimentally. 3D TCAD simulations have also verified them. In total, the conclusions are helpful for researchers to have a direct knowledge of charge sharing in concrete circuits, and then to improve the precise of soft error evaluation.

In this paper, a novel layout technique for N-hit single-event transient (SET) mitigation that is based on source-extension is proposed. Based on 65 nm bulk CMOS technology, both mixed-mode numerical simulations with technology computer-aided design (TCAD), as well as heavy-ion experiments show SET pulse widths are efficiently reduced with source extension. As opposed to what is found in the P-hit SET production process, where the source plays a detrimental role in SET mitigation due to the well-known bipolar effect, in the N-hit SET production process the source plays a beneficial role in reducing SET pulse widths, attributable to a parasitic reversed bipolar effect. This effect will be discussed in depth in this paper, and the proposed 'radiation hardened by design' (RHBD) layout technique will be extended to common combinational standard cells. The area penalty will also be discussed for the proposed layout technique. Meanwhile, both the P-hit and N-hit SET mitigation layout techniques will be introduced into the standard inverter layout, and the final improvement in SET pulse width will be discussed.

This paper investigates the temperature dependency of charge sharing in 130-nm CMOS technology over a temperature range of 200 to 420 K. TCAD simulation results show the charge sharing collection increases significantly with temperature rising, which is 65% ~ 317%. The LETth of MBU in two SRAM cells is also quantified. The result reveals that the upset LETth of the passive cell decreases in the whole temperature range, which is different from the parabolic relationship of single-event upset's temperature dependency.