Search

A pulsed picosecond laser was used to measure the time during which gates in a GaAs logic circuit were sensitive to single event upset (SEU). Circuit analysis showed that those gates would be most sensitive if the laser light arrived just prior to the clock signal going from low to high voltage. By delaying the clock signal with respect to the arrival time of the laser pulse, it was possible to measure a window of vulnerability, which is the time interval prior to the arrival of the clock signal during which the gate is sensitive to upsets. The width of that window was found to depend on the energy of the light pulse. Similar behavior is expected when the circuit is exposed to ions. These results suggest that, at high frequencies and in the presence of ions and with large LETs (linear energy transfers) gates in logic circuits may be sensitive to upsets during a large fraction of their duty cycle. The technique described provides an in situ way of measuring charge collection times at individual transistors and signal propagation times between logic gates using the circuit itself as the detector.<>

A pulsed picosecond laser was used to measure the threshold for single event upset (SEU) and single event latchup (SEL) for a detailed study of a CMOS SRAM and a bipolar flip-flop. Comparing the ion and laser upset data for two such vastly different technologies gives a good measure of how versatile the technique is. The technique provided both consistent and repeatable results that agreed with published ion upset data for both types of circuits. However, measurements of the absolute threshold linear energy transfer (LET) using infrared laser light do not agree with those of the ions, being about 50% too high for the SRAMs, and about 20% too high for the bipolar flip-flops. The consistency of the results, together with the advantages of using a laser system, suggests that the pulsed laser can be used for SEU/SEL hardness assurance of integrated circuits.<>

Single event upset cross sections exhibit a clock frequency dependence, the origins of which have been investigated in a CMOS SRAM, both with a pulsed laser synchronized to the operation of the circuit and with a circuit simulator modeling program.

The charge-collection characteristics of GaAs heterojunction-insulated-gate FETs fabricated with a low-temperature grown GaAs (LT GaAs) buffer layer are investigated as a function of device bias conditions for laser and ion irradiation. In accordance with earlier measurements, the LT GaAs FETs of this study exhibit a significant reduction in charge-collection efficiencies when compared to those of conventional FETs. This reduction in collected charge is associated with the efficient reduction of charge-enhancement mechanisms in the LT GaAs devices. It is revealed that charge-enhancement processes do occur in the LT devices under certain bias conditions, although at significantly reduced levels when compared to conventional FETs.

The single-event upset (SEU) characteristics of GaAs devices and circuits are reviewed. GaAs FET-based integrated circuits (ICs) are susceptible to upsets from both cosmic-ray heavy ions and protons trapped in the Earth's radiation belts. The origin of the SEU sensitivity of GaAs ICs is discussed in terms of both device-level and circuit-level considerations. At the device level, efficient charge-enhancement mechanisms through which more charge can be collected than is deposited by the ion have a significant negative impact on the SEU characteristics of GaAs ICs. At the circuit level, different GaAs digital logic topologies exhibit different levels of sensitivity to SEU because of variations in parameters, including logic levels, capacitances, and the degree of gate or peripheral isolation. The operational and SEU characteristics of several different GaAs logic families are discussed. Recent advances in materials and processing that provide possible solutions to the SEU problem are addressed.

Integrated circuits are currently tested at accelerators for their susceptibility to single-event effects (SEE's). However, because of the cost and limited accessibility associated with accelerator testing, there is considerable interest in developing alternate testing methods. Two laboratory techniques for measuring SEE, one involving a pulsed laser and the other /sup 252/Cf, are described in detail in this paper. The pulsed laser provides information on the spatial and temporal dependence of SEE, information that has proven invaluable in understanding and mitigating SEE in spite of the differences in the physical mechanisms responsible for SEE induced by light and by ions. Considerable effort has been expended on developing /sup 252/Cf as a laboratory test for SEE, but the technique has not found wide use because it is severely limited by the low energy and short range of the emitted ions that are unable to reach junctions either covered with dielectric layers or deep below the surface. In fact, there are documented cases where single-event latchup (SEL) testing with /sup 252/Cf gave significantly different results from accelerator testing. A detailed comparison of laboratory and accelerator SEE data is presented in this review in order to establish the limits of each technique.

Pulsed picosecond lasers with variable wavelength were used to investigate the details of charge collection in GaAs MESFETs. In short gate-length devices, charge collection at the drain may be much larger than at the gate and greater than the charge produced by the laser pulses. The results show that a pulsed laser is very useful in studies of charge collection. Two particularly useful features are the absence of the radiation damage which accompanies ion measurements and the ability to observe visually the point at which charge is being produced in the device.<>

Charge-collection measurements on GaAs MESFET test structures demonstrate that more charge can be collected at the gate than is deposited in the active layer and more charge can be collected at the drain than the total amount of charge produced by the ion. Enhanced charge collection at the gate edge has also been observed. The current transients produced by the energetic ions have been measured directly with about 20-ps resolution. The significance of this work is that it shows charge-collection phenomena in GaAs MESFETs to be very complex with important implications for modeling SEU (single-event upset) phenomena and developing techniques to mitigate SEU effects.<>

A comparison of the amount of charge collected at the drains of GaAs MESFETs irradiated with pulsed laser light and ions and having different gate lengths shows orders of magnitude more charge collected for 0.1 mu m MESFETs than for 1.2 mu m MESFETs manufactured using different processes. Analyses of the dependence of the photocurrent pulses on gate and drain voltages, temperature, and light intensity suggest that the enhanced charge collection is primarily due to modulation of the channel width by positive charge trapped in the vicinity of the channel. Enhanced charge collection via channel modulation also occurs in pseudomorphic MODFETs. Pulses with characteristics similar to those produced by laser light, i.e. large amplitudes and long decay times, were obtained when 0.1 mu m MESFETs were irradiated with He and Si ions. These results reveal the important role played by traps in determining SEU sensitivity in GaAs MESFETs with short gate lengths.<>

A laser illumination method was used to simulate single-event upset (SEU) in a p-well complementary metal-oxide-semiconductor (CMOS) logic circuit. It was found that, unlike the case of the static random access memory (RAM), the sensitivity of a logic circuit to SEU is not necessarily linearly dependent on the supply voltage and that its maximum hardness is achieved at the lower end of the voltage operating range. It is concluded that even though its greatest potential lies in the area of wafer-level hardness assurance the pulsed laser technique can also be used to assess changes in circuit design that have been implemented to increase SEU hardness.<>