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Integrated circuits (ICs) are a keystone for most critical applications operating in high-level radiation environments, spanning from high-energy nuclear applications up to space applications. The long-term reliability of these applications is essential for safe operation. However, the radiation effects for ICs are commonly investigated using fresh circuits, leaving the coupled effect of radiation and aging degradation unknown. This article investigates the impact of negative bias temperature instability (NBTI) aging degradation mechanism on the heavy-ion single event upset (SEU) radiation susceptibility of 28-nm ultra-thin body and buried oxide (UTBB) fully depleted silicon on insulator (FD-SOI) technology using a custom-designed test vehicle. NBTI aging degradation mechanism has been experimentally proven to increase the SEU sensitivity up to $2\times $ for 28-nm UTBB FD-SOI flip-flops. A comprehensive framework is presented to analyze the underlying mechanisms for the impact of NBTI, which includes NBTI aging mechanism modeling, SEU SPICE simulation, TCAD irradiation simulation, and Monte-Carlo simulation of radiation effects. The framework offered a quantitative prediction of the effect of NBTI degradation mechanism on the heavy-ion SEU radiation sensitivity. [ABSTRACT FROM AUTHOR]

With a software-based approach using commercial off-the-shelf CMOS imaging sensors to detect ionizing particles, a low-cost radiation monitor is published to improve fault tolerance of nanosatellites with commodity hardware. We achieve this by segmenting image artifacts caused by radiation effects simultaneously within the original capturing images. For this purpose, a two-step segmentation method was developed using already acquired images from a miniaturized limb sounding spectrometer that derives atmospheric temperature profiles. The method covers bad pixel elimination and particle flux determination by a minimalized amount of additional computational costs. This allows the determination of the radiation environment close to the imaging instruments inside the satellite. We present the segmented results and compare it with simulated as well as measured data from a reference radiation monitor experiment. The detected particle flux is up to a factor of five lower than the simulated flux. These effective particle flux values will be used to improve measurement time by triggering mitigation measures on demand and expand their life time. [ABSTRACT FROM AUTHOR]

We conducted a real-time soft-error rate characterization of CMOS bulk 65-nm static random access memories (SRAMs) subjected to fusion neutrons during deuterium–deuterium (D-D) plasma operation at W–tungsten–Environment in Steady-state Tokamak (WEST). The test equipment, installed in the experimental hall at several locations of the tokamak, was irradiated during machine shots by a flux of particles dominated by primary 2.45-MeV neutrons. Real-time neutron metrology, neutron spectrometry, complementary characterization with monoenergetic neutrons, and Monte Carlo numerical simulations at both material and circuit levels have also been performed to analyze the experimental data. Our results suggest that higher energy neutrons, simultaneously produced by deuterium–tritium (D-T) reactions due to triton burn-up in the D-D plasma, play a significant role in the radiation response of SRAMs for which multiple cell upsets are detected and cannot be attributed to D-D neutrons. [ABSTRACT FROM AUTHOR]

This work is focused on the design and the experimental characterization of an analog channel developed for the readout of lithium-drifted silicon detectors of the General AntiParticle Spectrometer (GAPS) experiment aimed at the search for dark matter. The instrument is designed for the identification of antideuteron particles from cosmic rays during an Antarctic balloon mission scheduled for late 2022. A low-noise analog front-end, featuring a dynamic signal compression to comply with the wide input range, has been designed in commercial 180-nm CMOS technology. The channel was fabricated in 2018 and is the first building block toward the development of a multichannel readout ASIC. The article will provide a description of the design criteria, the architecture of the channel, and a summary of the results of the experimental characterization. [ABSTRACT FROM AUTHOR]

This article presents the design of an LC-Tank voltage-controlled oscillator (VCO) for space and high-energy physics (HEP) applications. The main goal of this work is to design a radiation-hard oscillator to be integrated into a phase-locked loop (PLL), compliant with (but not limited to) SpaceFibre protocol requirements, which is able to support the 6.25 GHz frequency. The full custom schematic and layout of the LC-VCO are reported in this work. The LC-VCO is implemented in a commercial 65 nm CMOS technology, and its electrical characterization highlights a tuning range (TR) from 5.4 to 6.8 GHz. An experimental chip was fabricated and irradiated with X-rays up to 1 Grad (SiO2) total ionizing dose (TID) level at CERN facility. The TID experiment and measurement results are analyzed and discussed. The LC-VCO shows a frequency degradation of 2.54% and a 3.34% increment in phase noise at 1 Grad TID. The results achieved are of interest for both space and HEP applications. [ABSTRACT FROM AUTHOR]

Negative and positive muon-induced single-event upsets (SEUs) are studied in 20-nm bulk planar SRAMs. Muon irradiation is performed using a mono-energetic source with varying the muon energy. The energy dependence of the cross sections (CSs) of SEUs and multiple-cell upsets (MCUs) shows the significant contribution of muon capture reactions for the negative muon, as reported in previous studies. Interestingly, MCU events are found for the positive muon, in contrast to the previous studies. The CSs for the negative and positive muons are compared with that for the other terrestrial radiations: high-energy neutrons, thermal neutrons, and alpha particles. The voltage dependence of the SEU CS, together with the empirical model for charge collection, demonstrates the difference in the contributing secondary ions among the negative muon, the high-energy neutron, and the thermal neutron. The MCU events are thoroughly analyzed in terms of their ratio to the total events and their fail bit patterns. The results reveal that the MCU characteristics for the negative muon are different from that for the other terrestrial radiations due to the muon capture reactions, where parasitic bipolar effects and the isotropic emission of secondary ions are important factors. [ABSTRACT FROM AUTHOR]

Total ionizing dose (TID) effects induced by different photon sources are studied in MOS devices. The dose factor (DF), defined as the ratio between dose deposition in dosimeter and actual dose deposition in MOS-sensitive oxides (SOs), is estimated using Monte-Carlo simulations of energetic photons striking simple device structures. An effective TID approach is proposed to account for both the real ionizing dose depositions in small volumes and the charge yield. This method is applied to a silicon-on-insulator (SOI) technology using three photon sources: the usual ARACOR and 60Co sources, which deliver several tens of kiloelectron volt photons and ~1.25-MeV photons, respectively, and a third facility named ORIATRON, a 6-MeV electron linear accelerator that produces photons on a wide energy spectrum. This topic, investigated intensively in the literature a few decades ago, is revisited in the context of several evolutions including: new radiation sources, novel simulation tools, and device scaling, which all impact ionizing dose deposition in microsensitive volumes of current electronic technologies. Dedicated numerical simulations demonstrate the importance of taking into account the entire stack of materials in order to get the most accurate estimations of TID in the SO. Descriptions of the back-end-of-line (BEOL) layers (especially when the technology uses copper), the polysilicon gate, the Buried OXide (BOX) (for SOI devices), but also of the substrate and package are mandatory in these simulations, since dose enhancement and/or backscattered photons can be a significant source of TID variation in the gate oxide. Also the package lid composition and its thickness can be major TID contributors. The results show that the use of a prefilter with lead and aluminum can optimize ionizing dose deposition [ABSTRACT FROM AUTHOR]

The total ionizing dose (TID) sensitivity of mature and innovative technologies is investigated using both ionizing radiation experiments and Monte-Carlo simulations to discuss the potential of spectral photon radiation sources as an alternative for radiation effects studies. The impact of both technological and radiation test parameters on effective TID deposition is also discussed. All the layers struck by the incident radiation flux before reaching the targeted sensitive oxide are the major contributors of final ionizing dose deposits, rather than the actual sensitive oxide itself. Index Terms—ARACOR, back-end-of-line (BEOL), backside irradiation, Bremsstrahlung, bulk, CMOS, device packaging, dosimeters, front-end-of-line (FEOL), frontside irradiation, gamma, GAMRAY, LINAC, linear accelerator, metal–oxide–semiconductor field effect transistor (MOSFET), ORIATRON, radiation laboratory sources, silicon, silicon-on-insulator (SOI), SiO2, total ionizing dose (TID), X-rays. [ABSTRACT FROM AUTHOR]

This article presents a static random access memory (SRAM)-based flexible radiation monitor. The monitor was fabricated in a 65-nm CMOS technology and it is designed as an application-specific integrated circuit, which comprises 768k bits SRAM cell matrix with individual power supply and a digital control core with a serial peripheral interface (SPI). By adjusting the core voltage of the SRAM matrix, the radiation sensitivity was made flexible. Also, SRAM cells with different threshold voltages were implemented to get further extension on tunable sensitivity range. The monitor has been tested under heavy ions with a linear energy transfer (LET) from 1.5 to 48.5 $\text {MeV}\cdot \text {cm}^{2}$ /mg, high-energy (50–186 MeV) and low-energy (0.7–5 MeV) protons, and 14-MeV and thermal neutrons. An analysis was performed on how single-event upset sensitivity changes while tuning the supply voltage under different radiation environments. The results show that the monitor has the potential for space and facility applications. [ABSTRACT FROM AUTHOR]

A fully integrated pulsed reset charge-sensitive amplifier (CSA) optimized for low-capacitance (< 100 fF) radiation detectors was developed on a 0.35- $\mu \text{m}$ low-noise CMOS technology. The CSA was successfully tested with a collimated 10-mm2 silicon drift detector (SDD) and extensively characterized. The experimental setup and the achieved spectrometry results with SDD are described for triangular and trapezoidal shaping filters with peaking times ranging from ${t_{\mathrm {peak}}=0.1\!-\!12.8\,\,\mu \text {s}}$ at an operating temperature of −35 °C. With a minimum equivalent noise charge (ENC) of 3.4 electrons rms measured at $t_{\mathrm {peak}} = 5.6\,\,\mu \text{s}$ with the SDD connected, corresponding to a pulser linewidth of 29.9 eV full-width at half-maximum (FWHM), the presented results are among the best recorded for integrated CSA designs. The measured ENC at $t_{\mathrm {peak}} = 0.1\,\,\mu \text{s}$ is of 8.1 e− rms (70.7 eV FWHM) corresponding to 138.4 eV FWHM on the 5.9 keV 55Fe line. The open-input rise time is below 10 ns and the pulsed reset speed of 4 keV/ns allows a full recovery from a saturated output voltage in 63 ns. These latter results, together with the low-noise performance at short peaking times, make this preamplifier best suited for high-count rate spectroscopy applications that require a research-grade performance, such as in instrumentation for X and gamma spectroscopy and imaging for synchrotron radiation facilities, as well as other scientific or industrial applications. [ABSTRACT FROM AUTHOR]

ALTAIR is an application-specific integrated circuit (ASIC) developed for the readout of CdTe/CdZnTe detectors for X-γ-ray spectroscopic imaging. ALTAIR is composed of 16 channels with analog and mixed-signal sections specifically designed for high energy resolution and high-rate applications with the constraints of a low power consumption and operation at room temperature. The ASIC has three selectable ranges for input charge signals covering photon energies up to 90, 160, or 300 keV, which allow to optimize the signal-to-noise ratio under different experimental conditions. Eight peaking times of the pulse shaper are selectable from 200 up to 2.3 μs. ALTAIR includes a 180 bits register and an integrated serial peripheral interface (SPI) interface to configure the signal-processing parameters globally or independently for each channel. The power consumption is 950 μW/channel or 1.35 mW/channel for single-ended or differential output versions, respectively. A minimum equivalent noise charge (ENC) of 37 electrons rms [386 eV full-width at half-maximum (FWHM) in CdTe] has been measured at 500 ns peaking time and 90-keV energy range. With a CdTe pixel detector connected to ALTAIR and operated at +24 °C, a pulser FWHM of 1.7 keV (160 el. rms) and 1.9-keV FWHM on 59.54 keV line of 241 Am have been achieved at a peaking time of 500 ns. [ABSTRACT FROM AUTHOR]

This article presents the development of a cryogenic bandgap reference (BGR) circuit in a standard 0.18- $\mu \text{m}$ CMOS process for high-purity germanium (HPGe) detectors for low-background physics experiments. It provides a temperature-independent reference for mixed-signal circuits such as a ramp generator. A reliable cryogenic model is essential for the circuit design. The parameters of metal–oxide–semiconductor field-effect transistors (MOSFETs) and bipolar junction transistors (BJTs) were characterized and extracted at cryogenic temperatures from dc measurements on various geometries. MOSFETs had a general increase in threshold voltage and carrier mobility, a decrease in subthreshold slope at 77 K, with respect to 300 K. A new set of compact model parameters for MOSFETs and BJTs under cryogenic temperatures have been extracted. The relative errors between simulation and measurement were below 10% in almost all the bias regions for various device dimensions at 77 K. Two different BGR circuits were designed with the modified compact model parameters and evaluated from 77 K to 300 K. Temperature coefficient of less than 0.2 mV/K has been achieved over the whole range from 300 K to 77 K. [ABSTRACT FROM AUTHOR]

A new silicon-strip readout chip named “SliT” has been developed for the measurement of the muon anomalous magnetic moment and electric dipole moment (EDM) of the muon at Japan Proton Accelerator Research Complex (J-PARC). The SliT chip is designed in the Silterra 180-nm CMOS technology with mixed-signal integrated circuits. An analog circuit incorporates a conventional charge-sensitive amplifier, shaping amplifiers, and two distinct discriminators for each of the 128 identical channels. A digital part includes storage memories, an event building block, a serializer, and low voltage differential signaling (LVDS) drivers. A distinct feature of the SliT is utilization of the zero-crossing architecture, which consists of a CR– RC filter followed by a CR circuit as a voltage differentiator. This architecture allows generating hit signals with subnanosecond amplitude-independent time walk, which is the primary requirement for the experiment. The test results show a time walk of 0.38 ± 0.16 ns between 0.5 and 3 MIP signals. The equivalent noise charge is 1547 ± 75 e− (rms) at Cdet =33 pF as a strip-sensor capacitance. SliT128C satisfies all requirements of the J-PARC muon g−2/EDM experiment. [ABSTRACT FROM AUTHOR]

The angular sensitivity of neutron-induced single-event upsets (SEUs) is studied in 12-nm FinFET SRAMs. Irradiation experiments are performed using a terrestrial environment-compatible source with varying incidence angles. The analyses of the occurrence rates of SEUs and multiple-bit upsets (MBUs) demonstrate that although the SEU rate decreases at grazing incidence, the MBU rate increases when the incidence direction is parallel to the word lines (WLs) of the SRAM array, as similarly observed in our previous experiments for 20-nm planar SRAMs. It is found that the angular response of multiple-cell upsets (MCUs) is different between the 12-nm FinFET and 20-nm planar SRAMs. The comparative analysis of the voltage dependence of the MCU ratio reveals that this difference is due to the different contribution of parasitic bipolar effects (PBEs), which are more significant in the 20-nm planar SRAMs. It is also indicated that in the 12-nm FinFET SRAMs, the contribution of PBEs is relatively large when the incidence angle is parallel to the WLs. Through the characterization of the MCU events, the validity of this picture is confirmed based on the voltage dependence of the pattern-wise MCU ratio with the consideration of the impact of PBEs on fail bit patterns. [ABSTRACT FROM AUTHOR]

Neutron-induced multiple-cell upsets (MCUs) are studied in a 20-nm bulk SRAM by irradiation experiments using atmospheric-like neutrons at several angles of incidence. The evaluation of soft error rates reveals that the multiple-bit upset rate significantly increases at grazing incidence, indicating the possibility that the efficiency of error-correction codes is reduced depending on the device orientation in the terrestrial environment. The analyses of the characteristics of the MCU events confirm that the forward emission of secondary ions, the geometry of SRAM cells, and the parasitic bipolar effects are the key factors in determining the angular sensitivity of MCUs. Our analysis unveils the unique data pattern dependence in the occurrence probability of gap structures in fail bit patterns. Based on the consideration of potential perturbations in multiple p-wells, multi-well coupled potential unbalancing is found to be the plausible mechanism underlying this observation. The detailed analyses of fail bit maps with internal node voltages demonstrate that observed gap structures are consistent with the configuration induced by this mechanism. [ABSTRACT FROM AUTHOR]

This paper presents a study of the noise behavior of MOSFET devices belonging to a 110-nm CMOS technology in view of applications to the design of low-noise, low-power analog circuits in X-ray detection at free electron lasers (FELs) and the next generation of synchrotrons. The goal of this paper is to provide a valuable and cost-effective option, with respect to more scaled and expensive technology nodes, to designers of the detection systems of FELs and next-generation synchrotron sources. The white component of the noise voltage spectrum and the 1/ $f$ noise contribution is experimentally characterized by noise measurements in a wide frequency range. Data extracted from the characterization have been studied as a function of the bias condition and the gate dimensions (length and width). A comparison of the main parameters with less and more scaled CMOS generations is also provided. [ABSTRACT FROM AUTHOR]

This paper presents a novel radiation monitor that is based on a custom static random access memory (SRAM) application-specified integrated circuit. Its sensitivity is adjustable through its core supply voltage and the radiation monitoring is based on the upset rate that is measured during a measurement interval in the memory. The sensor has different supply voltages for the SRAM core and the interface logic to prevent incorrect digital signals during the measurement cycle. The memory was processed in a 0.18- $\mu \text{m}$ CMOS technology and was tested with heavy ions with an linear energy transfer from 1.8–60 MeV $\cdot $ cm2/mg, 24-GeV protons, and a mixed radiation field. The memory cells were also verified with a two-photon absorption laser. Furthermore, an analysis was made on single-event upsets and multibit upsets. [ABSTRACT FROM AUTHOR]

$3 \times 10^{13}/\text{cm}^{2}$ 1.2-MeV proton radiation will significantly increase heavy ion single-event transient (SET) cross sections and pulsewidths in 65-nm bulk CMOS technology. After proton radiation, heavy ion SET sensitivity increase in N-hit blocks is more than that in P-hit blocks. The analysis suggests that pMOS transistor on current ($I_{\mathrm{\scriptscriptstyle ON}}$) reduction due to total ionizing dose effects is the main reason for this effect. It is suggested that alternate heavy ion and proton experiments should be performed for radiation hardness assurance of candidate electronic devices used in deep space missions. [ABSTRACT FROM AUTHOR]

Single-event upsets induced by multiple-cell charge generation are studied in a 20-nm bulk SRAM by performing laser irradiation tests. The single-pulse two-photon absorption is utilized to simulate charge generation over multiple SRAM cells. The analysis of fail bit maps reveals that the physical topology of fail bits strongly depends on data patterns stored in SRAM cells. Our results indicate that potential perturbations in multiple p-wells play a key role in determining fail bit patterns. A novel multiple-cell upset mechanism, named multi-well coupled potential unbalancing, is proposed based on the consideration of the unbalanced activation of parasitic bipolar effects. The dominance of this mechanism is confirmed through multiple-pulse irradiation tests. [ABSTRACT FROM AUTHOR]

Full waveforms of single-event transients (SETs) in inverter chains were measured under focused heavy-ion microbeam irradiation. Inverter chains of varying spacings were irradiated with 48Ca and 197Au ions. The influence of changing the supply voltage from subthreshold to nominal level on SET forming and propagation was investigated, and the role of charge sharing is discussed. Key factors that influence SET widths and cross sections are identified across the applied range of supply voltages. A simple method is presented for estimating average SET widths at decreased supply voltages, and is based on the SET width measurements at nominal supply voltage, transistor-level simulations, and extracted circuit parameters. The proposed method matches well with the measured data. [ABSTRACT FROM AUTHOR]

We present a convenient layout-aware circuit-level modeling technique based on two modeling approaches: single spot and distributed circuit representing the diffusion- and circuit-driven charge collection processes correspondingly. The calibration is based on a joint comprehensive analysis of experimental data for 6T SRAM cells: cross-section dependences, error maps, and single-event upset multiplicity. This paper presents the results of both calibration and simulation for the devices manufactured by the TSMC 65-nm technology. [ABSTRACT FROM AUTHOR]

Silicon photomultiplier timing chip (STiC) is a 64-channel mixed-mode application-specific integrated circuit in the 0.18-\mu \textm CMOS technology from Univited Microelectronics Corporation (UMC) for silicon photomultiplier (SiPM) readout with very high timing resolution. It is designed for time-of-flight measurements in positron emission tomography and high-energy physics experiments. In order to achieve the best timing performance without compromising the charge/energy measurement, a novel time-based signal processing technique called “time-of-recovery (ToR)” method has been developed and implemented in the analog front end of the chip. This technique converts the incoming charge into a digital pulse with a linearized time-over-threshold width. Measurements have shown a time jitter smaller than 20 ps for the analog front end and smaller than 40 ps for the time-to-digital converter and the digital part. A coincidence time resolution of 214-ps full-width at half-maximum (FWHM) has been obtained with STiC using 3.1\times 3.1\times 15 mm3 LYSO:Ce crystals and Hamamatsu multi pixel photon counters (S12643-050CN(X)). The measured energy resolution for a 511-keV photon is 11.2% FWHM after correcting for SiPM saturation effects. In this paper, we report on the details of the ToR method and how it is embedded within the STiC design; results of performance measurements as well as the 128-channel front-end module used for the EndoTOFPET-US project are also presented. [ABSTRACT FROM PUBLISHER]

The MOnitor for Neutron Dose in hadrOntherapy (MONDO) project addresses the technical challenges posed by a neutron tracker detector aiming for a high detection efficiency and a good backtracking precision. The project aims to develop a tracking device capable of fully reconstructing the four momentum of fast and ultrafast secondary neutrons produced, e.g., in particle therapy (PT) treatments or in other physical processes. The MONDO tracker uses, as active material, squared scintillating fibers readout by dedicated CMOS-based digital single-photon avalanche diode (SPAD) array sensors. The expected light output, when operating in neutron monitoring applications, was experimentally evaluated in order to optimize the design of the MONDO detector readout. A small detector prototype ( $4 \times 4 \times 4.8$ cm) has been built and tested at a test beam facility. The detection capabilities have been measured using a traditional photomultiplier (PMT) and a particle beam of 450-MeV electrons crossing a single layer of fibers. The observed number of photoelectrons in this case is (7.2 ± 1.4). A detector prototype was also tested with an SPAD-based SBAM (SPAD-Based Acquisition readout for MONDO experiment) sensor (SPADnet-I) to study the tracking performances. SBAM is a novel sensor developed to match the need of high single-photon detection efficiency and high spatial resolution and compactness. The sensor expected performance is discussed in view of an operation tailored for PT applications. In this contribution, we also report the results of a simulation performed to optimize the full MONDO detector layout. [ABSTRACT FROM PUBLISHER]

Total ionizing dose effects are studied on a radiation hardened by design (RHBD) $256\times 256$ -pixel CMOS image sensor (CIS) demonstrator developed for ITER remote handling by using X- and $\gamma $ -ray irradiations. The (color) imaging capabilities of the RHBD CIS are demonstrated up to 10 MGy (SiO2), 1 Grad (SiO2), validating the radiation hardness of most of the designed integrated circuit. No significant sensitivity (i.e., responsivity and color filter transmittance) or readout noise degradation is observed. The proposed readout chain architecture allows achieving a maximum output voltage swing larger than 1 V at 10 MGy (SiO2). The influence of several pixel layout (the gate oxide thickness, the gate overlap distance, and the use of an in-pixel P+ ring) and manufacturing process parameters (photodiode doping profile and process variation) on the radiation-induced dark current increase is studied. The nature of the dark current draining mechanism used to cancel most of the radiation-induced degradation is also discussed and clarified. [ABSTRACT FROM PUBLISHER]

This paper presents a radiation tolerant phase-locked loop CMOS application-specified integrated circuit with an optimized voltage controlled oscillator (VCO) for single-event upsets (SEUs). The circuit is designed for high-energy particle physics experiments for low-jitter clock generation and clock recovery. An optimal tuning strategy of the VCO is presented that minimizes the cross section and the SEU sensitivity of the oscillator. The circuit is processed in a 65-nm CMOS technology and has been irradiated with heavy ions with a linear energy transfer between 10 to 69.2 MeV.cm2/mg. A comparison has been made with a conventional oscillator which proves a significant improvement in SEU sensitivity. [ABSTRACT FROM PUBLISHER]

We present experimental results obtained from full-waveform measurements of single-event transients (SETs) occurring in the conventional two-input AND and OR gates under focused heavy-ion radiation. Chips with test circuits were fabricated in a 65-nm bulk CMOS technology, and were irradiated in a microbeam facility using 197Au and 48Ca species. The resulting SETs were sensed using a dedicated on-chip analog multiplexer circuit. The obtained position-dependent ion hit responses were analyzed, and the strong evidence of charge-sharing-induced pulse quenching was observed. For SETs that propagated through the inverting stage of AND and OR circuits, a significant degradation of measured SET pulse widths and heights was seen. These observations are in good accordance with earlier published simulation and experimental results based on inverter chains. Test circuits also exhibited distinct SET responses depending on their logic state, making the AND gate a better candidate for exploiting the pulse quenching effect when circuits are placed in a triple well. [ABSTRACT FROM PUBLISHER]

This paper reports on the development and commissioning of the GP2 detector. GP2 was developed to address the requirement for a high-resolution event-mode imaging detector, for application in energy-resolved neutron radiography. The name GP2 derives from the use of gadolinium as a neutron conversion material, combined with a second-generation mass spectrometry sensor known as PImMS2. Theoretical and measured characteristics of GP2 are compared, with emphasis on the usability and functionality of the detector. The development of the detector has been steered by a design philosophy which was established to ensure that the detector has unique and novel impact. The motivation and consequences of the design philosophy are discussed. The key parameters reported are the neutron detection efficiency (7.5% at 2.5 Å), gamma sensitivity ( 1.5 \times 10^-3) , and a spatial resolution (modulation transfer function at 10%) of 6.4 lp/mm for a 4- \mu \textm -thick natural gadolinium neutron converter film. [ABSTRACT FROM AUTHOR]

This paper investigates the total ionizing dose (TID) response of nanoscaled field-effect transistors (FET) made of silicon multiple-gate nanowire (NW). The NWFET architecture relies on its remarkable electrostatic properties to push “silicon”-based technologies much deeper into device scaling than present FinFETs. However, as commonly observed when a new device or technology concept is proposed, such as shallow trench isolation and silicon-on-insulator or FinFET, TID effects reveal unexpected behaviors that can permanently modify pristine device electrical characteristics. This is why this paper discusses the impact of several parameters including the NWFET design and the transistor’s type to get thorough insights into the NWFET TID behavior. [ABSTRACT FROM PUBLISHER]

Single-event cross sections of four inverter chains, with uniform inverter spacing ranging from 120 nm to 4~\mu \textm , were experimentally measured and compared. These inverter chains were irradiated using a focused ion beam. Full analog waveforms of responses were sensed using on-chip wide-bandwidth analog multiplexers. Cross sections are examined with respect to pulse heights and pulse widths, for direct-hit waveforms as well as for waveforms propagated through the chain. The influence of ion hit position and charge sharing effects on the initial shape and propagation of the single-event transients (SETs) was analyzed. We have observed a considerable reduction of cross section for tightly spaced inverters, for both direct hits and propagated SETs. [ABSTRACT FROM PUBLISHER]

Simplified analytic expressions are presented for calculating pulsed-laser induced charge generation in devices with collection volumes of any size. The expressions for charge generation by single-photon absorption for various limiting cases are applied to charge-collection measurements for a bulk Si photodiode, and single-event upsets in a 90-nm CMOS, silicon on insulator (SOI), static random-access memory (SRAM). Strong quantitative agreement between the simplified expressions, the full numerical calculations, and the experimental data serves to validate the analytical expressions. Furthermore, despite the complexity of determining charge deposited via two-photon absorption, the analytic expressions exhibit excellent agreement with full charge-generation simulations utilizing nonlinear-optical beam propagation software. These expressions therefore, represent a convenient and accurate method for estimating pulsed-laser induced charge generation in specified volumes, and are particularly relevant for two-photon absorption, which previously has required the use of complex numerical approaches. [ABSTRACT FROM AUTHOR]

A 20.4 GHz VCO with a tuning range of 610 MHz (3%) was designed and fabricated in a 32 nm CMOS silicon-on-insulator technology. At 36 °C, the VCO achieves an output power of 0.1 dBm and a phase noise of −99 dBc/Hz at 1 MHz offset from the center frequency. TID experiments on the VCO operating at 36 °C, 75 °C, and 100 °C show degradation in frequency, output power, and phase noise. At 100 °C and 500 krad(SiO2), the VCO shows a worst-case degradation of 630 MHz, 4.3 dBm, and 6.1 dBc/Hz in center frequency, output power, and phase noise, respectively. At 36 °C and up to 500 krad(SiO2), the VCO can be retuned to operate at the required center frequency of 20.4 GHz. However, at 100 °C, the combined effects of temperature and TID result in specification failure. The system-level impact of TID-induced degradation on VCO performance is discussed using a phase-locked loop (PLL) as an example application. Measured performance corroborates previous predictions and highlights the importance of combined effects testing for advanced RF design characterization and qualification. [ABSTRACT FROM PUBLISHER]

The Total Ionizing Dose (TID) hardness of digital color Camera-on-a-Chip (CoC) building blocks is explored in the Multi-MGy range using 60Co gamma-ray irradiations. The performances of the following CoC subcomponents are studied: radiation hardened (RH) pixel and photodiode designs, RH readout chain, Color Filter Arrays (CFA) and column RH Analog-to-Digital Converters (ADC). Several radiation hardness improvements are reported (on the readout chain and on dark current). CFAs and ADCs degradations appear to be very weak at the maximum TID of 6 MGy(SiO2), 600 Mrad. In the end, this study demonstrates the feasibility of a MGy rad-hard CMOS color digital camera-on-a-chip, illustrated by a color image captured after 6 MGy(SiO2) with no obvious degradation. An original dark current reduction mechanism in irradiated CMOS Image Sensors is also reported and discussed. [ABSTRACT FROM PUBLISHER]

In this work, a comparison has been made between a low noise ring-oscillator and an LC-oscillator Phase Locked Loop (PLL). An ASIC has been developed to conduct irradiation experiments targeting high-energy physics applications. Two different samples were irradiated up to a total ionizing dose (TID) in SiO2 of 200 Mrad and 600 Mrad with a 100°C thermal annealing step. Single-Event Upset (SEU) tests were performed with heavy ions with LETs (Linear Energy Transfer) between 3.2 and 69.2 MeV.cm2/mg. A Two-photon absorption (TPA) laser facility has been used to provide detailed results on the SEU sensitivity. Both independent PLLs have identical loop dynamics to allow a fair comparison including a Triple-Modular Redundant (TMR) divider and TMR phase detector. Furthermore these circuits consume the same amount of power. The PLLs were processed in a commercial 65 nm CMOS technology. [ABSTRACT FROM PUBLISHER]