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The Xilinx Virtex family of static random access memory (SRAM) based field programmable gate array (FPGA) devices have made inroads into space-based computational platforms over the past decade. These devices are well-suited for digital signal processing (DSP) algorithms that are often used on orbit, providing the speedup of custom hardware without the cost of fabricating an application-specific integrated circuit (ASIC). SRAM FPGAs store the circuit in radiation-tolerant SRAM and SEUs can affect both the circuit functionality and the circuit state. Triple-modular redundancy (TMR) can be used to mask SEUs so that malfunctioning circuitry will not affect the output data. Unfortunately, applying TMR to a user circuit is difficult and unprotected cross-section is possible due to problems with the circuit design, device constraints, or the implementation of the user circuit on the FPGA. Given the complexity of these designs, estimating hardness assurance issues is not simple. This paper will present a tool, called the Scalable Tool for the Analysis of Reliable Circuits (STARC), that can automatically estimate unprotected cross-section and other hardness assurance issues for TMR-protected circuits. Index Terms--Fault identification, reliability analysis.

The mitigation of single-event upsets (SEUs) in field-programmable gate arrays (FPGAs) is an increasingly important subject as FPGAs are used in radiation environments such as space. Triple modular redundancy (TMR) is the most frequently used SEU mitigation technique but is very expensive in terms of area and power costs. These costs can be reduced by sacrificing some reliability and applying TMR to only part of the FPGA design. Our partial TMR method focuses on the most critical sections of the design and increases reliability by applying TMR to continuous sections of the circuit. We introduce an automated software tool that uses the Partial TMR method to apply TMR incrementally at a very fine level until the available resources are utilized. Thus the tool aims to gives the maximum reliability gain for the specified area cost. Index Terms--Aerospace industry, fault injection, fault tolerance, field programmable gate arrays (FPGAs), proton accelerator, radiation effects, reliability, single-event upset (SEU), triple modular redundancy (TMR).

This paper discusses the limitations of single-FPGA triple-modular redundancy in the presence of multiple-bit upsets on Xilinx Virtex-II devices. This paper presents results from both fault injection and accelerated testing. From this study we have found that the configurable logic block's routing network is vulnerable to domain crossing errors, or TMR defeats, by even 2-bit multiple-bit upsets. Index Terms--Fault tolerance, field programmable gate arrays, hardness measurement, proton radiation effects, radiation hardening, redundant systems.

This paper provides a methodology for estimating the proton and heavy ion static saturation cross-sections for multi-bit upsets (MBUs) in Xilinx field-programmable gate arrays and describes a methodology for determining MBUs' effects on triple-modular redundancy protected circuits. Experimental results are provided. Index Terms--Heavy ions, field programmable gate arrays, proton radiation effects.

This paper introduces a new way to characterize the dynamic single-event upset (SEU) cross section of an FPGA design in terms of its persistent and nonpersistent components. An SEU in the persistent cross section results in a permanent interruption of service until reset. An SEU in the nonpersistent cross section causes a temporary interruption of service. These cross sections have been measured for several designs using fault-injection and proton testing. Some FPGA applications may realize increased reliability at lower costs by focusing SEU mitigation on just the persistent cross section. Index Terms--Dynamic testing, error propagation, FPGA, persistence, proton accelerator, radiation, simulator, single-event upset (SEU).

The performance, in-system reprogrammability, flexibility, and reduced costs of SRAM-based field programmable gate arrays (FPGAs) make them very interesting for high-speed on-orbit data processing, but the current generation of radiation-tolerant SRAM-based FPGAs are based on commercial-off-the-shelf technologies and, consequently, are susceptible to single-event upset effects. In this paper, we discuss in detail the consequences of radiation-induced single-event upsets (SEUs) in the state of half-latch structures found in Xilinx Virtex FPGAs and describe methods for mitigating the effects of half-latch SEUs. One mitigation method's effectiveness is then illustrated through experimental data gathered through proton accelerator testing at Crocker Nuclear Laboratory, University of California-Davis. For the specific design and mitigation methodology tested, the mitigated design demonstrated more than an order of magnitude improvement in reliability over the unmitigated version of the design in regards to average proton fluence until circuit failure. Index Terms--Field programmable gate arrays (FPGAs), half-latches, proton accelerator, radiation effects, single-event upsets (SEUs).

An accelerator test was used to validate the performance of an FPGA single event upset (SEU) simulator. The Crocker Nuclear Laboratory cyclotron proton accelerator was used to irradiate the SLAAC1-V, a Xilinx Virtex FPGA board. We also used the SLAAC1-V as the platform for a configuration bitstream SEU simulator. The simulator was used to probe the 'sensitive bits' in various logic designs. The objective of the accelerator experiment was to characterize the simulator's ability to predict the behavior of a test design in the proton beam during a dynamic test. The test utilized protons at 63.3 MeV, well above the saturation cross-section for the Virtex part. Protons were chosen because, due to their lower interaction rate, we can achieve the desired upset rate of about one configuration bitstream upset per second. The design output errors and configuration upsets were recorded during the experiment and compared to results from the simulator. In summary, for an extensively tested design, the simulator predicted 97% of the output errors observed during radiation testing. The SEU simulator can now be used with confidence to quickly and affordably examine logic designs to 'map' sensitive bits, to provide assurance that incorporated mitigation techniques perform correctly, and to evaluate the costs and benefits of various mitigation strategies. The simulator provides an excellent test environment that accurately represents radiation induced configuration bitstream upsets. Index Terms--Dynamic testing, field programmable gate array (FPGA), proton accelerator, radiation, simulator, single event upset (SEU).