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Radiation effects of 3-MeV protons on 4H-SiC bipolar devices and integrated OR-NOR gates have been investigated. The chips were irradiated from a fluence of 1 x 10(8) cm(-2) until 1 x 10(13) cm(-2). Up until a fluence of 1 x 10(11) cm-2, both the bipolar devices and the logic gates were found to be stable, but for higher fluence, they begin to degrade as a function of irradiation fluence. Using TCAD simulations, degradation of the transistor current gain has been found to be more dominated by surface states than bulk defects generated by the proton irradiation. Simulations of logic circuits using SPICE show that the gain degradation is the key contribution to the unstable performance of the circuits from the fluence of 1 x 10(12) cm(-2) and above. QC 20141201

The objective of this paper is to describe a Switcher ASIC with 64 high voltage output channels. Each channel provides two high voltage control pulses with maximum amplitudes of 32 V. The high voltage level shifter was designed with a current mirror switching circuit that has a readily adjustable switching speed, unlike conventional switching circuits. The logic control circuit uses a forward and reverse chain of Flip-Flops along with other combinational logic gates to generate bidirection sequential control pulses with adjustable pulsewidth and polarity. The layout was carefully designed to achieve a 14 μ m width for the last stage transistors' drain path based on the 50 μm output channel pitch set up. At least a 200 mA current driving capability was obtained for each channel. The design was fabricated using TSMC's 180 nm CMOS HV technology. The paper further discusses the critical design steps including chip architecture, layout, simulation and bench test. The final experimental results demonstrate that the Switcher ASIC meets requirements and the rising time could reach 480 ns with a 1 nF capacitive load at 15 V pulse amplitude. With this load, the total power consumption of the chip was measured to be approximately 4 mW when the input clock period was 42.2 μs. In addition to use in a charge-pump detector, the ASIC can be used to control the charge accumulation and readout in other detectors, such as X-ray pump probe detectors (XPP).

High-speed communication systems typically employ a mix of signal types and circuit topologies in order to optimize efficient data propagation. Current-mode logic is the industry standard for high-speed CMOS circuit design due to the inherent speed of current steering. However, current-mode output voltages are not rail-to-rail and therefore require a conversion to a full-swing signal for downstream CMOS logic. This interface between current-mode and CMOS logic is found to be vulnerable to single-event effects. A radiation-hardened-by-design solution is proposed for such interfaces.

Low-power radiation-hardened sequential digital circuits supporting multiple supply voltages, integrated logic, and a low standby power state are presented. By basing the design on proven radiation hard circuits, single event effects hardness is guaranteed. The circuit is based on differential cascode voltage switch logic, which provides an integral level shift and allows storage at the full supply voltage supported by the process, while allowing the combinatorial logic supply voltage to scale for power savings. When compared to a conventional master-slave flip-flop design, the proposed flip-flop design provides up to 80% energy reduction with logic operating at reduced voltage and speed. Fifty-percent energy reduction is obtained without compromising speed when operating with all circuits at maximum voltage.

Single-event destructive failure has been observed in Maxim C-Pi process bipolar application-specific integrated circuits (ASICs) for both heavy ions and protons. We discuss the observed failures, proposed mechanism of failure, and significance for space applications.

Results are presented on technique using displacement damage from energetic ions to suppress single event latchup in commercial off-the-shelf (COTS) CMOS integrated circuits. Ions implanted through the back of a thinned chip degrade the parasitic bipolar transistors causing latchup without degrading chip functionality or the parametrics of the chip.

A device/circuit simulation is used to analyze a gigahertz clocked emitter-coupled logic circuit being perturbed by a single event. Results provide an understanding of charge collection in the heterojunction bipolar transistor. A technique for single-event hardening is demonstrated by simulation.

A new cell design technique is described which may be used to create SEU hardened circuits. The technique uses actively biased, isolated well transistors to prevent transients in combinational logic from reaching the output node.

The /sup 60/Co gamma ray total dose performance of unhardened bipolar 54F10 TTL (transistor transistor logic) integrated circuits was measured over dose rates from 0.0088 rad(SiO/sub 2/)/s to 28 rad(SiO/sub 2/)/s. Contrary to what others have reported on the 54F logic family, failure was independent of dose rate. This result implies that these parts are undesirable for use in a space environment. One manufacturer's part failed due to excessive input high current at total doses from 20 to 30 krad(SiO/sub 2/) and the other failed at total doses from 7 to 9.5 krad(SiO/sub 2/). Thus, when considering a family of bipolar devices for application at space dose rates, each member of the family must be examined. It is pointed out that extrapolating total dose radiation measurements made at laboratory dose rates to sweeping conclusions about the performance of an unhardened process or device family at space dose rates can be misleading. >

A design consideration for digital CMOS circuits that are almost insensitive to radiation is proposed. By adding three n-MOSFETs to the conventional digital CMOS circuits, good radiation-hard behavior is observed in the inverter, NOR, and NAND gates under SPICE simulation. Detailed circuit design consideration and the simulation results are given. >

Total dose failure levels in digital bipolar microcircuits utilizing recessed oxides were measured at levels as low as 5 Krad(Si). Typical failure levels are in the 10-100 Krad(Si) range. Failure was found to be a strong function of irradiation bias and annealing time after irradiation. In addition, total dose "windows" below 100 Krad(Si) were observed. The radiation failure mechanism is predominantly inversion of p type silicon either at the bottom of the recessed field oxide, causing buried layer to buried layer channeling, or on the oxide sidewall causing collector to emitter leakage. In addition, a failure mode due to increased sidewall current was observed in a nonisolated form of integrated injection logic. Hardening approaches have been identified and investigated at several manufacturers. Device failure levels were found to vary by several orders of magnitude depending on process lot and layout revision.

Large scale integrated (LSI) devices fabricated with integrated injection logic (I2L) were studied by both heavy ion experiments asd device analysis to determine the upset threshold, the charge collection volumes and ultimately the probability for upset in the galactic cosmic ray spectrum. The devices studied, the SEP9900A, the SBP9989 and the P-Code generator were fabricated by Texas Instruments, Inc.

Radiation effects on integrated injection logic arrays are presented in terms of available data on "conventional" structures and new test data on advanced structures. The advanced structures were developed for improved electrical performance, independent of radiation hardness. These results are used as a basis of reviewing the considerations in hardened I2L development as an LSI technology in comparison to other contemporary LSI technologies.

Radiation-tolerant high-performance CMOS VLSI circuit design has been investigated, using ?-ray irradiation on scaled clocked CMOS/ SOS shift registers and bulk CMOS basic logic circuits. By utilizing 16-bit and 64-bit clocked CMOS shift register circuits, the usefulness of circuit design parameter optimization has been confirmed experimentally, showing the possibility of > 10 MHz operation VLSI circuits at 5 V after radiation doses in excess of 105 rads (Si). Functionality after 105 rads (Si) irradiation for shift registers with on-chip clock driver circuits has also been shown. Furthermore, radiation test results on bulk CMOS NAND and NOR circuits, into which radiatiop-hard structure NMOS transistors have been introduced, and effectiveness of this radiation-hard structure in bulk CMOS circuit designs are described. Based on the above results, radiation-tolerant high-performance CMOS VLSI circuit designs for space and nuclear plant applications are discussed.

Requirements of integrated circuits for space applications are high speed, small size and great reliability. The CMOS/SOS process technology inherently fulfills these requirements. Recently discovered problems of reliability are soft errors or "bit-flips" induced by galactic cosmic rays or terrestrial ?-particles. This paper discusses CMOS/SOS circuit design which minimizes these errors. A design example is given for D flip-flop as a typical storage element, and a comparison is made between 4 ?m, 2 ?m, and 1 ?m channel lengths. Results obtained for short channel lengths indicate that the design of VLSI circuits for space applications with CMOS/SOS technology is feasible and realistic.

The radiation response of Integrated Schottky Logic (ISL) circuits is described. An 8-bit ALU, 4-bit shift register, and 4-bit adder implemented on the Signetics 8A1200 ISL Configurable Gate Array were studied in flash x-ray, neutron, and total dose environments. Experimental data are provided describing the variation of ALU propagation delays and output I-V characteristics with neutron and total dose exposure. Transient gamma upset levels are given for the three circuits studied, and their dependence on ISL logic configuration and bias conditions is described. Mechanisms are proposed to explain the trends exhibited in the experimental results.

This paper reports on an Integrated Injection Logic (I2L) radiation effects model which includes radiation effects phenomena. Twenty-five individual current components were identified for an 12L logic gate by assuming wholly vertical or wholly horizontal current flow. Equations were developed for each component in terms of basic parameters such as doping profiles, distances, and diffusion lengths, and set up on a computer for specific logic cell configurations. For neutron damage, the model shows excellent agreement with experimental data. Reactor test results on GE I2L samples showed a neutron hardness level in the range of 6 x 1012 to 3 x 1013 n/cm2 (1 MeV Eq), and Cobalt-60 tests showed a total dose hardness of 6 x 104 to greater than 1 x 106 Rads(Si) (all device types at an injection current of 50 microamps per gate). It was found that significant hardness improvements could be achieved by: a) diffusion profile variation, b) utilizing a tight N+ collar around the cell, and c) locating the collector close to the injector. Flash X-ray tests showed a transient logic upset threshold of 1 x 109 Rads(Si)/sec for a 28 ns pulse, and a survival level greater than 2 x 1012 Rads(Si)/sec.

Integrated Injection Logic (I2 L) is a new highdensity, low power bipolar LSI technology that offers major performance advantages over other bipolar and MOS/LSI technologies. Results are presented on the experimentally-determined radiation sus ceptibility of developmental unhardened I2L LSI logic cells in terms of neutron-induced displacement damage, ionizing - dose-induced surface effects and transient photoresponse.

An analytical technique is presented for investigating the neutron induced degradation of integrated injection logic (I2L) inverter cells as a function of basic processing variables. The technique combines a one-dimensional semiconductor device code, the PN code, with the circuit analysis code SPICE. Predictions of neutron induced degradation as a function of npn transistor base doping, epitaxial thickness and resistivity and pnp transistor base width are presented for a second generation I2L technology. A comparison of predicted response to experimental data is given for inverter cells fabricated with different npn base doping and epitaxial thickness.

Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre-and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented.

An experimental evaluation of the radiation tolerance of silicon MESFET devices and simple digital integrated circuits is presented. Circuit performance in both total dose and transient radiation environments have been determined. Test circuits employing both enhancement and depletion logic elements of various geometries are described and the radiation response compared.

The effects of neutron and total dose gamma irradiations on the electrical characteristics of an integrated injection logic (I2L) cell and an I2L multiple inverter circuit were investigated. These units were designed and fabricated to obtain circuit development information and did not have radiation hardness as a goal. The following parameters of the test structures were measured as a function of total dose and neutron fluence: the dc common-base current gain of the lateral pnp transistor; the dc common-emitter current gain of the vertical npn transistor; the forward current-voltage characteristics of the injector-substrate junction, and the propagation delay versus power dissipation per gate for the multiple inverter circuit. The limitations of the present test structures in a radiation environment and possible hardening techniques are discussed.

Additional process controls which have been implemented by semiconductor manufacturers in order to produce low threshold voltage CMOS integrated circuits are shown to significantly improve the radiation hardness of such devices. In particular, this improvement is directly correlated with reduced concentrations of the sodium impurity which results in smaller threshold voltage shifts for the p-channel (negatively biased) transistors. Further, it has been shown that n-channel devices can be hardened by the technique of ion implantation on production line integrated circuits. Thus, digital CMOS devices hard to greater than a Mrad(Si) have been realized.

An up-diffused form of symmetrical cell Integrated Injection Logic (I2L) has been designed, modeled, fabricated, and demonstrated to be fully operating after 6 × 1014 neutrons/cm2. This technology is expected also to be capable of full operation after > 3 × 106 Rad(Si) ionizing radiation and immune to information upset at levels above 1 × 1010 Rad(Si)/s based on experience with related devices.

The design of three application-specific integrated circuits (ASICs) dedicated to nuclear spectrometry is discussed. APLO1 is a bipolar linear gate that can be used either as a peak-amplitude-to-time converter, or as a 50-ns sample-and-hold circuit CDN 400 is an ECL Wilkinson-type time-to-digital converter operating at a 600-MHz clock frequency, DMI00 is a CMOS direct-memory-increment circuit with four independent channels and histogram capability. A high-performances multichannel analyzer on a single IBM-PC board has been designed for use with these circuits. >

The variation in current density of Integrated Injection Logic (I2L) as a function of neutron or gamma irradiation was evaluated. The results confirm the previous theoretical predictions in all respects. These results can now be used as a tool for improving radiation-hardened I2L cell designs and to verify analytical predictions.

The radiation resistance of a 16-bit microprocessor based on integrated injection logic technology has been investigated. Cumulative fluences of 10 to the 12th power to 10 to the 14th power e/sq cm were used in the radiation-resistance study. Complete failure of the microprocessor was noted at a fluence level of 1.2 times 10 to the 14th power e/sq cm. Though the radiation resistance of the microprocessor makes it suited for space applications, reductions in the power dissipation of the device are needed.