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A new 32-channel pipeline TDC module, which implements custom-developed Time Memory Cell LSIs, has been developed for high-rate wire-chamber applications. The module has achieved a 370 ps time resolution, and records data for a period of 3.2 [micro]sec. To handle the large data size, a digital signal processor (DSP56002) is implemented in the module. Most of the control logic is implemented in two complex PLDs to achieve a density of 32 channels in a single-width, double-height VME module.

A high performance VMEbus interface module for NIM ADC's has been developed. Data pipelining and data suppression speed up the data acquisition. An event synchronization module for coincidence experiments has also been designed.

We describe a 96 bit zero-suppressor and encoder VME board designed for the RPC trigger system of the L3 Forward/Backward Muon detector at CERN. Running at 20 MHz clock frequency, the board processes the elementary 96 bit wide detector pattem in less than one microsecond, storing hit addresses in a FIFO array. Details of the board architecture - based on seven XILINX XC3020 LCAs - are presented and simulation and preliminary test results are briefly reported.