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Modular multilevel converters (MMCs) in high- voltage applications contain large numbers of power switches, which increases the fault probability inside MMCs. This paper proposes a detection method for the faulty arm containing switch open-circuit failures in high-voltage MMCs to improve the reliable operations of MMCs. The proposed method uses the periodicity of the deviation between the maximum and minimum capacitor voltages to provide the detection reference. To yield a reliable reference, the repetitive signal generator is employed. Then, the fault is identified by the difference between the referenced and measured capacitor voltage deviations. An auxiliary criterion is also designated to avoid the false detection caused by the mutations in MMCs. The proposed method can reduce the difficulty in the selection of thresholds. Moreover, the proposed method is robust in high-voltage MMCs with inferior capacitor voltage balancing performance, which ensures detection rapidity and accuracy. Finally, the feasibility of the method is verified by simulation results in Matlab/Simulink. [ABSTRACT FROM AUTHOR]

The missing capability of DC fault current limitation is an inherent disadvantage in the typical half-bridge modular multilevel converter (MMC), which restricts its application in long-distance high voltage direct current (HVDC) systems. The full-bridge submodule (FBSM) and clamped double submodule (CDSM) topologies allow for fault current self-clearing, but also suffer from additional hardware cost and power losses. In this paper, an improved submodule topology utilizing the new reverse-blocking insulated gate bipolar transistor (RB-IGBT) is proposed to improve system economy without compromising its performance. The operating principles and DC fault characteristics of the proposed topology are analyzed in details, including comparison with various topologies in terms of cost, losses, fault current clearing speed and thermal. Compared with the traditional CDSM topology, the proposed RBSM can clear DC faults faster with reduced cost of switching devices. A DC fault protection strategy for MMC-HVDC system is also presented. Simulation results under normal operating, permanent and transient fault conditions are carried out to verify the effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

The integration of overhead lines in future MTDC grids leads to a higher fault rate compared to cables. Most of the faults are considered to be non-permanent, so that the line can be reconnected after dielectric recovery. The auto-reclosing procedure in HVDC systems reveals new challenges since multiple restrikes are possible within a short period of time. This paper proposes an auxiliary circuit for DC Circuit Breakers (DCCB) which enables to use the DCCB internal capacitor for the line pre-energization. A comprehensive description of the switchgear operations during the pre-energization sequence is provided and the fault property identification method is defined. The method is validated by simulations in a MTDC grid and a sensitivity analysis is carried out using EMTP-RV. [ABSTRACT FROM AUTHOR]

DC transformer is an essential equipment for formation of multi-voltage-level DC grid. This paper proposes a novel non-isolated Boost-type alternate arm DC transformer (Boost-AADCT) for medium- and high-voltage level DC grid application. The Boost-AADCT is comprised of three submodule-cascaded arms, two thyristor-cascaded director switches, and two buffer capacitors. Bidirectional power transmission is achieved by alternatively charging and discharging of the intermediate arm following the Boost principle, while the pulsating power component caused by intermittent transmission is actively smoothened by grid-side buffer subcircuits formed by the buffer capacitors and grid-side arms. The active power buffering method increases the tolerance range of voltage ripple of the buffer capacitor, and the required energy storage capacity is resultantly reduced. Circuit configuration, operation principle, and mathematical model are first introduced. Then, the control strategy is proposed, the main circuit parameters are designed, and bidirectional fault-blocking capability is analyzed. Comparison with other DC-DC converters shows that the Boost-AADCT significantly reduces the requirement of semiconductors and has relatively lower synthetic cost. At last, performance of the Boost-AADCT and the proposed control strategies are evaluated by simulation tests conducted in MATLAB/Simulink environment. [ABSTRACT FROM AUTHOR]

Modular multilevel converter based high voltage direct current (MMC-HVDC) transmission is the prospective technology for large-scale wind farms integration. In this paper, a comprehensive coordinated control strategy for DC fault ride-through (FRT) of wind farms connected to the grid through bipolar MMC-HVDC transmission is proposed. To reduce the requirement of breaking speed and capacity of DC breakers, an active current-limiting control method is proposed to limit the rise rate of DC fault current, and the principle of parameter selection is designed. After DC breakers isolate fault, the control mode switching methods of bipolar MMC are designed to make the fault pole MMC operate as a STATCOM to support the AC grid and improve the active power transmission capability of the healthy pole MMC, which can reduce the impact range of unbalanced power between wind farms and converter station. In addition, a coordinated control strategy for wind farms load-shedding considering speed constraints is designed to realize the optimal distribution of load-shedding power among wind turbines, which can regulate unbalanced power together with the healthy pole MMC to realize DC FRT. Finally, the effectiveness and feasibility of the proposed control methods are verified by simulation results. [ABSTRACT FROM AUTHOR]

Pole-to-pole dc short circuit fault blocking capability is a major concern when modular multilevel converters (MMCs) are applied in high voltage direct current (HVDC) transmission systems. Traditional MMCs based on half-bridge submodules (HBSMs) cannot block the fault current, thus needing expensive direct current circuit breakers (DCCBs). There are MMCs based on improved submodule topologies that can block dc faults, but usually with significantly increased device cost. This paper proposes an improved HBSM-based MMC (HB-MMC) which needs fewer extra semiconductor devices. The improved HB-MMC is more competitive than other schemes when it comes to investment cost and loss. An H-bridge circuit composed of two director switches and two diode valves is installed around one arm of the HB-MMC, which will not change the direction of current during the normal operation, whereas it can change the direction of the fault current when a pole-to-pole dc short circuits fault is detected. After two director switches have been turned off, a reverse-biased voltage provided by one arm can block the fault current. The topology can be further improved to provide reactive power during faults. Simulation results are presented to validate the features of the proposed improved HB-MMC. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC) is one of the most attractive topologies for high-voltage and high-power applications. Reliability is an important challenge for MMCs due to large amounts of power switches in the phase leg of the MMC. To enhance the reliable performance of MMCs, an effective and accurate fault detection and localization strategy for MMCs with the nearest level modulation is proposed in this paper. According to the general characteristics of the MMC, the capacitor voltage of the faulty submodule (SM) is higher than the healthy ones’. Based on the sorting algorithm, the faulty SM will have the maximum voltage and it will be identified by the proposed fault detection method. The auxiliary monitoring is supplemented to the detection algorithm for the cases of faults occurring in multiple SMs. The faulty SM localization strategy is based on the differences of capacitor voltages. The faulty switches are located by the distinctions of capacitor voltage in different current intervals. The proposed strategy could be applied under the cases of single or multiple SMs failures and identifies three kinds of the power switches faults in the faulty SM. The validity of the proposed strategy is verified by the simulation results in MATLAB/Simulink. [ABSTRACT FROM AUTHOR]

Transient voltage and current stresses are essential for the design and protection of multi-terminal DC (MTDC) transmission systems, especially under the short-term dynamics after severe grid faults. In this paper, we propose a discrete-time model for the modular multilevel converter based MTDC (MMC-MTDC) system considering the DC-side disturbances in the system. Based on the piecewise linear modeling, the state variables such as the transient voltage on the sub-module (SM), arm current, etc., can be calculated analytically for the critical short term (within 10 ms) after the severe DC fault while the system protection is yet to be activated. Parameter sensitivity analysis is also performed to give a better system design guideline. The estimation results are validated by detailed electromagnetic (EMT) circuit simulations and the scaled-down experimental laboratory prototype. [ABSTRACT FROM AUTHOR]

The standard alternative-arm converters (AAC) with the sweet spot or short overlap operation have faced a challenge of balancing submodule (SM) capacitor voltages, where this issue has not been paid much attention so far. In this paper, a new control strategy for the SM-capacitor voltage balancing of the AAC applied in high-voltage dc transmission systems is proposed. The suggested control technique is composed of three regulators, where a control for the average voltage of all SM capacitors, the voltage balancing among the converter arms, and the voltage balancing of the individual SM capacitor are performed. Based on the operation principle of the standard AAC, which activates only three of six converter arms simultaneously, the energy balancing of the three activated arms is performed every one sixth of the fundamental cycle by the converter common offset voltage. Band-stop filters with the central frequencies at the fundamental, second-, and third-order components of the line frequency are applied to obtain the average values of the SM capacitor voltages for the feedback controllers. The simple proportional and integral controllers are employed for this scheme and the voltages of SM capacitors are mostly balanced during the steady states and kept closely to the rating with overshoot of less than 7% under the transient conditions. The proposed control method is verified by simulation results for a 33-level AAC under both normal and fault conditions. [ABSTRACT FROM AUTHOR]

In this paper, a static synchronous compensator (STATCOM) operation scheme of the modular multilevel converter adopting clamp double submodules (CDSM-MMC) during a pole-to-pole dc fault is proposed. By analyzing the current paths of a CDSM, this paper proposes three new operation states of the CDSM, which allow the CDSM to provide bipolar voltages when the arm current that flows through it is negative. Through control of the CDSMs to operate in these new states along with the blocked state, the arms of the CDSM-MMC can operate alternately in two different modes, that is, the conducting mode and blocked mode even when the dc-link voltage drops to zero. Thus, the CDSM-MMC is capable of working as a STATCOM during a dc fault. Moreover, a control strategy of the dc-fault STATCOM operation mode is designed to control the reactive power provided by the CDSM-MMC, to limit the dc fault current, and to reserve and balance the energies stored in capacitors. Simulation results conducted in PSCAD/EMTDC demonstrate the validity of the proposed STATCOM operation scheme and control strategy of the CDSM-MMC during a pole-to-pole dc fault. [ABSTRACT FROM AUTHOR]

This paper studies the dc fault development stages and analyzes the fault dynamics in a point-to-point multilevel modular converters (MMC)-based dc connection. First, the effect of the dc grid configuration on the normal operation was investigated by comparing an asymmetric monopole with metallic return and a symmetric monopole. Then, the main parameters that affect the dc fault response of a grid, such as the fault type, impedance and converter blocking, were examined. Compared to previous studies, which are based on simulation results, the analysis is performed hereby both in theory, deriving the equations that describe the dc fault stages, as well as using experimental results obtained in the designed laboratory setup. The setup consists of two MMC terminals connected to two ac sources representing independent ac grids. These terminals are connected using a simple dc link based on pi-section equivalent of dc cables. The obtained results, which verified the theoretical analysis, can be used to determine the protection function thresholds of the MMC, as well as to estimate the developed stresses on dc lines during fault conditions and to define the design requirements for dc breakers. [ABSTRACT FROM PUBLISHER]

In this paper, a novel solid-state fault current-limiting circuit breaker (SSFCLCB) based on a series resonance LC tank is proposed. Since the series configuration of the resonance structure (a capacitor and a reactor) of the SSFCLCB is invisible during normal operation mode, it shows negligible impedance in the line. In fault conditions, the SSFCLCB topology changes to a rectifier bridge and feeds the resonance structure with rectified ac voltage. With the rectified voltage, the series capacitor is charged and, as a result, the faulty line is opened and the fault current is seized. Hence, the suggested SSFCLCB cannot only limit the fault current but can also open the faulty line and acts as a circuit breaker. For confirmation of these aspects, simulations are performed using MATLAB software. Also, a prototype structure is designed and built for results confirmation. This experimental setup is established to prove that SSFCLCB has excellent performance in its startup, normal operation, and current-limiting/breaking conditions. The results show that the SSFCLCB has the ability to improve distribution network reliability and it can decrease the network fault current level successfully. [ABSTRACT FROM PUBLISHER]

The modular multilevel converter (MMC) has become one of the most promising converter topologies for medium/high-power applications. Since the MMC is structured based upon stacking up a number of series-connected identical submodules (SMs), to improve its fault tolerance and reliability, SM failure detection and location is of significant importance. In this paper, the impact of open-circuit switch failures of the SMs on the operation of the MMC is analyzed. Based on the analysis under SM failure conditions, two SM failure detection and location methods are proposed, that is, a clustering algorithm (CA)-based method and a calculated capacitance (CC)-based method. In the proposed CA-based method, a pattern-recognition-based fault diagnosis approach, which employs the clustering algorithm to detect and locate the faulty SMs with open-switch failures through identifying the pattern of 2-D trajectories of the SM characteristic variables, is developed. The proposed CC-based method is based on the calculation and comparison of a physical component parameter, that is, the nominal SM capacitance, and is capable of failure detection, location, and classification within one stage. The performance of the proposed failure detection methods for an MMC system is evaluated based on time-domain simulation studies in the PSCAD/EMTDC software environment. The reported study results demonstrate the capabilities of the two proposed methods in detecting and locating any SM failure under various conditions accurately and efficiently. [ABSTRACT FROM PUBLISHER]

This paper presents a novel mitigation technique to reduce the effects of geomagnetically induced currents (GICs) on high-voltage power systems. The method consists of connecting switching devices at the neutral grounding connection point of transformer banks. Only one transformer bank needs to be grounded through a switch to reduce GIC in a two-terminal system. For multiterminal systems, n-1 switches are necessary and the operation is independent from each other. The switching frequency and the duty cycle are selected from a tradeoff between the effectiveness of the method and the detection of fault currents. Transient simulations on a two-bus 230/500 kV system show that the proposed switching at the neutral successfully mitigates the GIC. This proposed technique opens the door to a new family of GIC mitigation methods. [ABSTRACT FROM AUTHOR]

The high voltage direct current transmission system based on modular multilevel converter (MMC-HVDC) technology is now studied and used widely. But traditional half bridge topology of sub module (HBSM) of MMC can't block dc link fault current because of the freewheeling effect of diodes. In order to solve this problem, firstly, this paper improves HBSM topology, a series connected double sub module (SDSM) is designed and dc link fault current blocking capability is realized without tripping ac circuit breaker, so MMC-HVDC with this improved topology can immediately rebuild dc link voltage and resume power transmission. Secondly, the self starting and fault disposing procedure are also designed. At last, simulations in the software PSCAD/EMTDC are carried out to verify its effectiveness and feasibility. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC) has become the most promising converter technology for high-voltage direct current (HVDC) transmission systems. However, similar to any other voltage-sourced converter-based HVDC system, MMC-HVDC systems with the half-bridge submodules (SMs) lack the capability of handling dc-side short-circuit faults, which are of severe concern for overhead transmission lines. In this paper, two new SM circuit configurations as well as a hybrid design methodology to embed the dc-fault-handling capability in the MMC-HVDC systems are proposed. By combining the features of various SM configurations, the dc-fault current path through the freewheeling diodes is eliminated and the dc-fault current is enforced to zero. Several MMC configurations based on the proposed hybrid design method and various SM circuits, that is, the half-bridge, the full-bridge, the clamp-double, and the five-level cross-connected SMs, as well as the newly proposed unipolar-voltage full-bridge and three-level cross-connected SMs, are investigated and compared in terms of the dc-fault-handing capability, semiconductor power losses, and component requirements. The studies are carried out based on time-domain simulation in the PSCAD/EMTDC software environment for various SM configurations and dc-fault conditions. The reported study results demonstrate the proposed hybrid-designed MMC-HVDC system based on the combination of the half-bridge and the proposed SM circuits is the optimal design among all evaluated systems in terms of the dc-fault-handing capability, semiconductor power losses, and component requirements. [ABSTRACT FROM PUBLISHER]