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The missing capability of DC fault current limitation is an inherent disadvantage in the typical half-bridge modular multilevel converter (MMC), which restricts its application in long-distance high voltage direct current (HVDC) systems. The full-bridge submodule (FBSM) and clamped double submodule (CDSM) topologies allow for fault current self-clearing, but also suffer from additional hardware cost and power losses. In this paper, an improved submodule topology utilizing the new reverse-blocking insulated gate bipolar transistor (RB-IGBT) is proposed to improve system economy without compromising its performance. The operating principles and DC fault characteristics of the proposed topology are analyzed in details, including comparison with various topologies in terms of cost, losses, fault current clearing speed and thermal. Compared with the traditional CDSM topology, the proposed RBSM can clear DC faults faster with reduced cost of switching devices. A DC fault protection strategy for MMC-HVDC system is also presented. Simulation results under normal operating, permanent and transient fault conditions are carried out to verify the effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

DC transformer is an essential equipment for formation of multi-voltage-level DC grid. This paper proposes a novel non-isolated Boost-type alternate arm DC transformer (Boost-AADCT) for medium- and high-voltage level DC grid application. The Boost-AADCT is comprised of three submodule-cascaded arms, two thyristor-cascaded director switches, and two buffer capacitors. Bidirectional power transmission is achieved by alternatively charging and discharging of the intermediate arm following the Boost principle, while the pulsating power component caused by intermittent transmission is actively smoothened by grid-side buffer subcircuits formed by the buffer capacitors and grid-side arms. The active power buffering method increases the tolerance range of voltage ripple of the buffer capacitor, and the required energy storage capacity is resultantly reduced. Circuit configuration, operation principle, and mathematical model are first introduced. Then, the control strategy is proposed, the main circuit parameters are designed, and bidirectional fault-blocking capability is analyzed. Comparison with other DC-DC converters shows that the Boost-AADCT significantly reduces the requirement of semiconductors and has relatively lower synthetic cost. At last, performance of the Boost-AADCT and the proposed control strategies are evaluated by simulation tests conducted in MATLAB/Simulink environment. [ABSTRACT FROM AUTHOR]

Modular multilevel converter based high voltage direct current (MMC-HVDC) transmission is the prospective technology for large-scale wind farms integration. In this paper, a comprehensive coordinated control strategy for DC fault ride-through (FRT) of wind farms connected to the grid through bipolar MMC-HVDC transmission is proposed. To reduce the requirement of breaking speed and capacity of DC breakers, an active current-limiting control method is proposed to limit the rise rate of DC fault current, and the principle of parameter selection is designed. After DC breakers isolate fault, the control mode switching methods of bipolar MMC are designed to make the fault pole MMC operate as a STATCOM to support the AC grid and improve the active power transmission capability of the healthy pole MMC, which can reduce the impact range of unbalanced power between wind farms and converter station. In addition, a coordinated control strategy for wind farms load-shedding considering speed constraints is designed to realize the optimal distribution of load-shedding power among wind turbines, which can regulate unbalanced power together with the healthy pole MMC to realize DC FRT. Finally, the effectiveness and feasibility of the proposed control methods are verified by simulation results. [ABSTRACT FROM AUTHOR]

Pole-to-pole dc short circuit fault blocking capability is a major concern when modular multilevel converters (MMCs) are applied in high voltage direct current (HVDC) transmission systems. Traditional MMCs based on half-bridge submodules (HBSMs) cannot block the fault current, thus needing expensive direct current circuit breakers (DCCBs). There are MMCs based on improved submodule topologies that can block dc faults, but usually with significantly increased device cost. This paper proposes an improved HBSM-based MMC (HB-MMC) which needs fewer extra semiconductor devices. The improved HB-MMC is more competitive than other schemes when it comes to investment cost and loss. An H-bridge circuit composed of two director switches and two diode valves is installed around one arm of the HB-MMC, which will not change the direction of current during the normal operation, whereas it can change the direction of the fault current when a pole-to-pole dc short circuits fault is detected. After two director switches have been turned off, a reverse-biased voltage provided by one arm can block the fault current. The topology can be further improved to provide reactive power during faults. Simulation results are presented to validate the features of the proposed improved HB-MMC. [ABSTRACT FROM AUTHOR]

The standard alternative-arm converters (AAC) with the sweet spot or short overlap operation have faced a challenge of balancing submodule (SM) capacitor voltages, where this issue has not been paid much attention so far. In this paper, a new control strategy for the SM-capacitor voltage balancing of the AAC applied in high-voltage dc transmission systems is proposed. The suggested control technique is composed of three regulators, where a control for the average voltage of all SM capacitors, the voltage balancing among the converter arms, and the voltage balancing of the individual SM capacitor are performed. Based on the operation principle of the standard AAC, which activates only three of six converter arms simultaneously, the energy balancing of the three activated arms is performed every one sixth of the fundamental cycle by the converter common offset voltage. Band-stop filters with the central frequencies at the fundamental, second-, and third-order components of the line frequency are applied to obtain the average values of the SM capacitor voltages for the feedback controllers. The simple proportional and integral controllers are employed for this scheme and the voltages of SM capacitors are mostly balanced during the steady states and kept closely to the rating with overshoot of less than 7% under the transient conditions. The proposed control method is verified by simulation results for a 33-level AAC under both normal and fault conditions. [ABSTRACT FROM AUTHOR]

With the development of HVdc transmission technology, the isolation of dc faults is becoming increasingly important. As the most effective solution, hybrid HVdc circuit breaker (CB) is not mature enough, which has restricted its engineering application. Accordingly, this paper proposes an auxiliary dc CB scheme suitable for HVdc grid. In this scheme, the traditional half-bridge modular multilevel converter (MMC) is partially innovated to have the ability of auxiliary breaking operation. With the effect of the MMC auxiliary breaking (MAB) operation at both ends of the fault line, the dc fault current can be easily interrupted and isolated by low-cost CB unit installed in the dc transmission line. The equivalent circuit under MAB process is analyzed, and the fault isolation sequences are designed. Furthermore, the economic comparative analysis among three schemes is performed. Finally, a four-terminal bipolar HVdc grid test model is built in PSCAD/EMTDC; in addition, an MMC prototype with proposed scheme is also developed. The simulation and experimental results validate the effectiveness of the proposed scheme. [ABSTRACT FROM AUTHOR]

Future multi-terminal dc networks are envisioned for the large-scale integration of renewable energy sources into today's power systems. An essential aspect for the reliable operation of these systems is the fast and selective dc-side fault handling and separation of faulted lines. The objective of this paper is the development and evaluation of a multi-terminal dc protection strategy based on fault-blocking converters (e.g., full-bridge based modular multi-level converters) and high-speed switches. Both a suitable fault control and a new high-speed switch design for a fast separation of faulted dc lines are elaborated. The novel concept is intended to reduce the requirements on the high-speed switches compared to dc circuit breakers and to ensure a fast restoration of the active power transmission capability, as well as the dc voltage. The fault-clearing strategy is analyzed using electromagnetic transient (EMT) simulations under variation of the fault location, type, and resistance. The investigations are carried out in a cable-based multi-terminal HVdc system with full-bridge modular multi-level converters in symmetrical monopole configuration. [ABSTRACT FROM AUTHOR]

This paper proposes a modified bridge switch-type flux-coupling nonsuperconducting fault current limiter (BSFC-NSFCL) for suppressing the fault current and voltage sag. A flux-coupling reactor and a bidirectional bridge switch are combined to perform the functions of steady-state line current sharing and fault current suppression. The modified BSFC-NSFCL mainly utilizes the magnetic flux cancellation effect to make the limiter behave as a short circuit on the circuit during normal operation. Hence, there is almost no impact on the power system when the limiter is used. When a fault event occurs, the bridge switch turnsoffimmediately, and then, the magnetic flux cancellation effect disappears. Thus, the impedance of primary coil inserts into the circuit to restrict the fault current and voltage sag phenomena. Once the fault is removed, the bridge switch turnsonagain, and the BSFC-NSFCL recovers to the normal operation. The modified NSFCL is more cost-effective and easy to be implemented than the flux-coupling superconducting fault current limiter. Theoretical analysis for the BSFC-NSFCL has been fully developed and proven by MATLAB software. Finally, the analytical, simulated, and experimental results have been carried out to verify the feasibility and performance of the proposed BSFC-NSFCL. [ABSTRACT FROM AUTHOR]

In this paper, a static synchronous compensator (STATCOM) operation scheme of the modular multilevel converter adopting clamp double submodules (CDSM-MMC) during a pole-to-pole dc fault is proposed. By analyzing the current paths of a CDSM, this paper proposes three new operation states of the CDSM, which allow the CDSM to provide bipolar voltages when the arm current that flows through it is negative. Through control of the CDSMs to operate in these new states along with the blocked state, the arms of the CDSM-MMC can operate alternately in two different modes, that is, the conducting mode and blocked mode even when the dc-link voltage drops to zero. Thus, the CDSM-MMC is capable of working as a STATCOM during a dc fault. Moreover, a control strategy of the dc-fault STATCOM operation mode is designed to control the reactive power provided by the CDSM-MMC, to limit the dc fault current, and to reserve and balance the energies stored in capacitors. Simulation results conducted in PSCAD/EMTDC demonstrate the validity of the proposed STATCOM operation scheme and control strategy of the CDSM-MMC during a pole-to-pole dc fault. [ABSTRACT FROM AUTHOR]

This paper presents a breaker arrangement concept, the multiline breaker (MLB), for the protection of multiterminal high voltage dc (MTdc) networks. Based on the design of a hybrid breaker, the MLB is an economically attractive solution for the protection of multiple dc lines in nodal connection using a single main breaker path. By using commutation units, the MLB directs the fault current through the main breaker in a unidirectional way, irrespective of the fault location. Hence, this study presents the design requirements for the MLB, regarding both hardware and control, and evaluates its operation within a grid. For this reason, a four-terminal half-bridge multilevel modular converters-based MTdc grid in radial configuration was used and pole-to-ground dc fault conditions were investigated. The dc fault response of the grid with one MLB at the central node is compared to the respective response of the grid when one hybrid breaker is employed at each dc line. The simulations show that the MLB is feasible and that the overall MTdc grid fault response for the two protection systems is very similar. As a result, the design advantages of the MLB make it a promising solution for the dc fault isolation in MTdc grids. [ABSTRACT FROM AUTHOR]

This paper studies the dc fault development stages and analyzes the fault dynamics in a point-to-point multilevel modular converters (MMC)-based dc connection. First, the effect of the dc grid configuration on the normal operation was investigated by comparing an asymmetric monopole with metallic return and a symmetric monopole. Then, the main parameters that affect the dc fault response of a grid, such as the fault type, impedance and converter blocking, were examined. Compared to previous studies, which are based on simulation results, the analysis is performed hereby both in theory, deriving the equations that describe the dc fault stages, as well as using experimental results obtained in the designed laboratory setup. The setup consists of two MMC terminals connected to two ac sources representing independent ac grids. These terminals are connected using a simple dc link based on pi-section equivalent of dc cables. The obtained results, which verified the theoretical analysis, can be used to determine the protection function thresholds of the MMC, as well as to estimate the developed stresses on dc lines during fault conditions and to define the design requirements for dc breakers. [ABSTRACT FROM PUBLISHER]

High-voltage direct current (HVDC) grids will require the development of dc protections that provide fast fault isolation and minimize the disturbance caused to the existing ac power networks. This paper investigates how the dc fault recovery performance of a half-bridge modular multilevel converter (HB-MMC) is impacted by different dc protection design choices. An HB-MMC point-to-point HVDC system that is protected with dc circuit breakers (CBs) is simulated on a real-time digital simulator using detailed switch models of the converters and switch gear. A dc CB controller has been developed and implemented in a software-in-the-loop fashion, and has been made available free for download. A novel blocking scheme for the HB-MMC is proposed, which limits the prospective dc-side fault current, benefiting dc switch gear. A comparison of circulating current controllers shows that the standard d —q controller is likely to be unsuitable for fault studies. Finally, benchmarking shows that a 48% reduction in power-flow recovery time and a 90% reduction in the energy dissipated in the circuit breaker can be achieved, along with other benefits, depending on the protection design. [ABSTRACT FROM PUBLISHER]

Current-transformer (CT) saturation causes severe distortion in the measured current waveform which may lead to maloperation of the protective devices. This paper proposes a low-cost, power-electronic device to prevent the CT from saturation. The proposed compensator is inserted in series with the relay in the CT secondary circuit and acts as a controlled voltage source (CVS). The proposed CVS generates a time-varying voltage to cancel the voltage developed across the CT burden; therefore, the CT magnetic flux remains almost constant and undistorted during the power system transients. It will be shown that this device can precisely compensate fault current, inrush current, and other probable transient currents despite its simplicity. The proposed device can be employed to compensate the already in-service CTs connected to nondigital and digital relays. Comprehensive computer simulations are carried out to validate the effectiveness of the proposed compensator. The performance of a sample compensator of this type is validated through special high-current laboratory experiments (carried out over several hundred amperes up to 1.6 kA), and the obtained results illustrate the capability of the proposed compensator to prevent CT saturation. [ABSTRACT FROM PUBLISHER]

Without additional circuitry, the half-bridge modular multilevel converter (HB-MMC) is endangered under dc-side faults. Typically, a bypass thyristor is augmented to each HB cell to take up fault current until ac circuit breakers interrupt the dc fault. This paper proposes a dc fault protection concept for HB-MMC stations that requires insignificant extra silicon area relative to the thyristor bypass concept. Herein, bypass thyristors of typical HB cells are rearranged such that an independent modular shadow rectifier bridge (SRB) is formed. A low-loss switch assembly is utilized to immediately isolate the MMC following fault detection and the SRB suppresses the fault current by injecting a reverse dc voltage. Among several advantages, the proposed arrangement incurs insignificant losses in steady state, and in some arrangements the MMC is capable of operating in STATCOM mode briefly after fault inception to support ac grid voltage. The proposed concept may be suitable for clearing temporary faults on overhead HVdc lines. Several structural variations will be viewed and discussed. Applicability for a two-level voltage source converter will be addressed. The concept is validated by detailed numerical simulations of a ±200-kV HB-MMC station under dc fault. [ABSTRACT FROM PUBLISHER]

In this paper, a novel solid-state fault current-limiting circuit breaker (SSFCLCB) based on a series resonance LC tank is proposed. Since the series configuration of the resonance structure (a capacitor and a reactor) of the SSFCLCB is invisible during normal operation mode, it shows negligible impedance in the line. In fault conditions, the SSFCLCB topology changes to a rectifier bridge and feeds the resonance structure with rectified ac voltage. With the rectified voltage, the series capacitor is charged and, as a result, the faulty line is opened and the fault current is seized. Hence, the suggested SSFCLCB cannot only limit the fault current but can also open the faulty line and acts as a circuit breaker. For confirmation of these aspects, simulations are performed using MATLAB software. Also, a prototype structure is designed and built for results confirmation. This experimental setup is established to prove that SSFCLCB has excellent performance in its startup, normal operation, and current-limiting/breaking conditions. The results show that the SSFCLCB has the ability to improve distribution network reliability and it can decrease the network fault current level successfully. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel bridge-type solid-state fault current limiter (BSSFCL) based on one series reactor which operates in ac and dc modes. The proposed BSSFCL includes a rectifier bridge with a reactor. This reactor is used as a dc reactor in normal operation mode and as an ac reactor in fault conditions. The advantages of the proposed BSSFCL over the existing dc reactor-type FCLs are its negligible impedance in normal operation mode and its high impedance during a fault interval using simple and novel switching. In other words, during the normal operation mode, the proposed BSSFCL operates in dc mode and in the fault interval, its topology is changed to the ac mode. This switching decreases the switching transient recovery voltage and introduces considerable impedance during the fault period. MATLAB/Simulink software is used for simulations and a prototype is designed and tested for results verification, and to show the performance of the proposed BSSFCL. [ABSTRACT FROM PUBLISHER]

This paper presents a novel mitigation technique to reduce the effects of geomagnetically induced currents (GICs) on high-voltage power systems. The method consists of connecting switching devices at the neutral grounding connection point of transformer banks. Only one transformer bank needs to be grounded through a switch to reduce GIC in a two-terminal system. For multiterminal systems, n-1 switches are necessary and the operation is independent from each other. The switching frequency and the duty cycle are selected from a tradeoff between the effectiveness of the method and the detection of fault currents. Transient simulations on a two-bus 230/500 kV system show that the proposed switching at the neutral successfully mitigates the GIC. This proposed technique opens the door to a new family of GIC mitigation methods. [ABSTRACT FROM AUTHOR]

This paper compares how a dc fault affects a multiterminal dc (MTdc) network depending on the HVDC transmission system topology. To this end, a six-step methodology is proposed for the selection of the necessary dc fault protection measures. The network consists of four voltage-source converters converters radially connected. The converters natural fault response to a dc fault for the different topologies is studied using dynamic simulation models. For clearing of the dc faults, four different dc breaker technologies are compared based on their fault interruption time, together with a current direction fault detection method. If necessary, the converters are reinforced with limiting reactors to decrease the peak value and rate of rise of the fault currents providing sufficient time for the breakers to isolate the fault without interrupting the MTdc network operation. The study shows that the symmetric monopolar topology is least affected by dc contingencies. Considering bipolar topologies, the bipolar with metallic return exhibits better fault response compared to the one with ground return. Topologies with ground or metallic return require full semiconductor or hybrid breakers with reactors to successfully isolate a dc fault. [ABSTRACT FROM AUTHOR]

The applications of power semiconductors in circuit-breaker (CB) technology can help achieve considerable improvement in its performance and possible new capabilities. In this paper, new trends in power electronics for the applications in CBs are presented. It also summarizes and reviews the appropriate hybrid mechanical-static CB topologies. Various conventional and derived topologies for ac as well as dc applications are described. Discussions about common and future trends in this technology development are presented. This study will provide a useful framework and point of reference for the future development of hybrid CBs for various different applications. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC) has become the most promising converter technology for high-voltage direct current (HVDC) transmission systems. However, similar to any other voltage-sourced converter-based HVDC system, MMC-HVDC systems with the half-bridge submodules (SMs) lack the capability of handling dc-side short-circuit faults, which are of severe concern for overhead transmission lines. In this paper, two new SM circuit configurations as well as a hybrid design methodology to embed the dc-fault-handling capability in the MMC-HVDC systems are proposed. By combining the features of various SM configurations, the dc-fault current path through the freewheeling diodes is eliminated and the dc-fault current is enforced to zero. Several MMC configurations based on the proposed hybrid design method and various SM circuits, that is, the half-bridge, the full-bridge, the clamp-double, and the five-level cross-connected SMs, as well as the newly proposed unipolar-voltage full-bridge and three-level cross-connected SMs, are investigated and compared in terms of the dc-fault-handing capability, semiconductor power losses, and component requirements. The studies are carried out based on time-domain simulation in the PSCAD/EMTDC software environment for various SM configurations and dc-fault conditions. The reported study results demonstrate the proposed hybrid-designed MMC-HVDC system based on the combination of the half-bridge and the proposed SM circuits is the optimal design among all evaluated systems in terms of the dc-fault-handing capability, semiconductor power losses, and component requirements. [ABSTRACT FROM PUBLISHER]

This paper describes a method to apply a generalized systematic approach, useful to identify the faults' effect on load points' reliability accounting for intentional islanding, with either random or sequential Monte Carlo simulation (RMCS, SMCS) in order to assess distribution system reliability in smart grids. Moreover, a simple RMCS based on an annual branch fault probability, which correlates with the branch fault frequency, is described as well. A study case is presented to validate the results (in terms of expected reliability indices) of the proposed method in comparison with the analytical one. Further, other useful information, such as the best and worst results as well as the probability distribution of load-point annual outages number and duration is presented too. Finally, the results show that islanding positively affects reliability and then it could became a standard practice provided that the main technical issues are addressed. [ABSTRACT FROM PUBLISHER]

This paper proposes an LCL dc-dc converter concept which is capable of achieving very high stepping ratios with megawatt-level power transfers. The converter can find potential application in connecting high-power dc sources to high-voltage dc transmission including future dc transmission networks. This converter is based on two ac/dc insulated-gate bipolar transistor-based converters and an internal passive LCL circuit without internal ac transformers. The LCL circuit is designed to enable voltage stepping without any reactive power circulation and with potentially soft switching operation which minimizes the switching losses. The designed converter has the ability to achieve current regulation even under extreme external dc faults and, therefore, the converter can operate through dc faults. The switch utilization is better than similar topologies and losses are reasonably low. A dual-active-bridge transformer-based converter design is presented to compare with the proposed LCL converter. A detailed PSCAD model confirms conclusions using a 100-MW 20-kV/300 kV test system. An LCL 200-W 20-V/100-V dc/dc prototype converter is built to validate the proposed topology. [ABSTRACT FROM AUTHOR]

A high-voltage direct current system using modular multilevel converter (MMC-HVDC) is a potential candidate for grid integration of renewable energy over long distances. The dc-link fault is an issue MMC-HVDC must deal with, especially for the nonpermanent faults when using overhead lines. This paper proposed a protection scheme to implement fast fault clearance and automatic recovery for nonpermanent faults on dc lines. By employing double thyristor switches, the freewheeling effect of diodes is eliminated and the dc-link fault current is allowed to freely decay to zero. Then, the dc arc can be naturally extinguished and the insulation on the short-circuit point can be restored. The thyristor switches convert the dc-link fault into an ac short circuit of the ac grid through MMC arms. The ac short-circuit current can be cleared simply by turning off all thyristor switches. Since circuit breakers are not tripped during fault clearance, MMC can immediately and automatically rebuild the dc-link voltage and restart power transmission. Simulation results using PSCAD/EMTDC have verified the validity of the proposed protection scheme. [ABSTRACT FROM AUTHOR]

In this paper, a new method is proposed that can be used to discriminate faults from switching transients. The method is primarily intended for use in systems where fast fault detection and fast fault clearing before the first peak of the fault current are required. An industrial system, in which high short-circuit power is desired but in which high short-circuit currents cannot be tolerated is an example of such a system. A phase-locked loop (PLL) is used to perform the discrimination. Computer simulations have been performed and it has been demonstrated that the output of the PLL is completely different for a fault compared to a switching transient. This difference can be used for discrimination between a fault and a switching transient. [ABSTRACT FROM AUTHOR]