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This paper investigates the Multilevel Current Source Converter (MCSC) STATCOM. It proposes a new method of modulation. The new modulation method produces less THD and di/dt at the terminals of the MCSC STATCOM when compared to the widely used Phase-Shifted Carrier SPWM (PSC-SPWM). To ensure the inductors' currents remain balanced, a Current Balancing Algorithm (CBA) is presented. The CBA does not require any controls. It relies on assigning optimum switching states to each CSC module in real-time. In addition, two control strategies are presented in this paper. The first one assumes the STATCOM to be a SISO. Therefore, it only requires one PI controller. However, the gains for the controller must be changed if the STATCOM was to transition from capacitive mode to inductive mode, or vice versa. The second control strategy overcomes this problem by implementing a TITO integral state feedback controller. The contributions of this paper are validated via simulation and experimental results. [ABSTRACT FROM AUTHOR]

The three-phase series-connected modular multilevel converter (SC-MMC) is presented as one option for high-voltage direct current (HVDC) tap to reduce the cost of an HVDC station. Compared with conventional three-phase parallel-connected MMC, the number of semiconductor switches in SC-MMC is reduced by one-third to withstand the same dc voltage. First, the paper studies the operating principle of SC-MMC, and then presents an interspacing phase-shifted pulsewidth-modulated method which could improve the waveform of the output ac voltage for a given switching frequency. Next, the control strategy based on the identical real power input of each phase is proposed to balance the dc voltage of each phase under an unbalanced grid condition. The current limit of switching devices is also taken into consideration to protect SC-MMC from overcurrent. Furthermore, a universal zero-sequence current controller is developed as one part of the control strategy. In addition, an innovative method to suppress the third harmonics of ac current is presented. With the third harmonic suppression strategy, the SC-MMC can operate with much smaller SM capacitors without deteriorating the ac current, which contributes to the cost reduction further. Finally, simulation results obtained in PSCAD/EMTDC are provided to validate the proposed control strategies. [ABSTRACT FROM PUBLISHER]

The large number of voltage levels in a modular multilevel converter (MMC) make staircase modulation a feasible alternative, particularly in high-power applications. However, staircase waveforms do not necessarily mean operation of the MMC submodules (SMs) at the fundamental frequency. This paper presents an analysis of SM switching frequencies in staircase-modulated MMCs and their correlation to the modulation index and load phase angle. A carrier-based pulsewidth-modulation (CB-PWM) equivalent technique is also developed. This analysis demonstrates that CB-PWM techniques provide a similar switching frequency with superior harmonic performance and improved voltage balancing characteristics at all modulation indices compared to staircase modulation. The theoretical analysis is verified with extensive simulation results for MMCs with different SMs and experimental results from a laboratory prototype. [ABSTRACT FROM PUBLISHER]

Multilevel current source converters are a smart choice for the high-power applications with low-voltage and high-current requirements. This paper presents the detailed analysis of a current source modular multilevel converter (CSMMC) and its application as a STATCOM. Various properties of CSMMC are compared with the voltage-source modular multilevel converter (VSMMC). The submodule inductance selection method and a sorting-based algorithm for inductor current balancing are proposed for CSMMC. The validity of the inductance selection method and the inductor current balancing algorithm are confirmed by the simulation of a three-phase CSMMC using PSCAD/EMTDC. The carrier phase-shifted sinusoidal pulsewidth modulation is used as the switching technique. The performance of a converter is analyzed with interleaved and noninterleaved carrier signals for the upper and lower arms. Results show that CSMMCs and corresponding VSMMCs have analogous features. Hence, the development on VSMMCs can be used for reference to CSMMCs and vice-versa. Furthermore, the control designs for CSMMC-based STATCOM are presented and verified using simulations. The obtained results of the proposed STATCOM show that the steady-state and transient performance of the system are quite satisfactory. This makes the CSMMC suitable for HVDC and flexible ac transmission systems applications. [ABSTRACT FROM PUBLISHER]

This letter presents a Space Vector Pulse Width Modulation (SVPWM) strategy for reducing the DC-link current harmonics in a multi– Voltage Source Inverter (VSI) topology with common DC-link bus. The DC current harmonic reduction is achieved by phase-shifting the PWM pattern of individual VSIs, with the inverters sharing the system total power. Simulation and experimental results are shown to validate the proposal. [ABSTRACT FROM AUTHOR]

The carrier-based pulse width modulation (CBPWM) with zero-sequence component injection is equivalent to the space-vector PWM (SVPWM), and hence it can be taken as a simplified alternative to the SVPWM. However, it is quite complex to calculate the zero-sequence component in CBPWM for three-level (3L) converters such as the T-type converter, making the 3L SVPWM still have a large computation burden. In this letter, unified expressions for the zero-sequence component are analytically derived, and the modulation waves of 3L SVPWM can be directly calculated by only 7 simple equations with 3 steps. The computation burden for implementing 3L SVPWM is therefore significantly reduced without sector determination, calculation and assignment of dwell times. [ABSTRACT FROM AUTHOR]

This letter proposes a new scheme of phase-shifted carrier pulse-width modulation for the modular multilevel converter with redundancy submodules (SMs). The proposed scheme can offer a smooth transition for the redundancy SM from the standby state to the startup operation when normally operating down. The operational feasibility of the proposed scheme was first verified through simulations with PSCAD/EMTDC, and then hardware-in-the-loop system tests with the real-time digital simulator. [ABSTRACT FROM PUBLISHER]