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In 2017, three sub-synchronous resonance (SSR) events were reported in the transmission system of Electric Reliability Council of Texas (ERCOT). These three events with different consequences are due to the same cause, i.e., Type-3 wind farms radially connected to a series compensated transmission line. The objectives of this paper are: 1) to build a testbed to replicate these real-world events and investigate what causes the different consequences; 2) to find out the impact of wind penetration level and wind speed on SSR; and 3) to investigate how to mitigate SSR. The replication testbed is built in MATLAB/Simpowersystems with each wind farm represented by a single aggregated wind turbine with full dynamics. The challenge of replication is the limited information about those three events, the ERCOT system, and the wind farms. Nevertheless, relying on simplification and assumptions, we are able to replicate the three events. Our contributions include the configured testbed for Type-3 wind farm SSR studies, diagnosis of impacting factors on SSR, and the confirmation of an SSR mitigation strategy through grid-side converter ac voltage command signal modulation. [ABSTRACT FROM AUTHOR]

Conventional half bridge modular multilevel converter (MMC) system will suffer great over-current when there is a dc side fault. Therefore, topology study in sub-modules with dc side fault blocking capability have become one of the hotspots in MMC field. However, fault blocking topologies using conventional IGBT devices must employ more semiconductors than half bridge topology. The extra semiconductor devices employed in the topology will lead to the increase of cost and conduction loss. To reduce the conduction loss of the fault blocking topology, a novel sub-module topology is proposed in this paper. The proposed topology employs reverse blocking devices to form the low conduction loss path. Conduction loss analysis is conducted in this paper to show the priority of the proposed topology. Simulation and experiment results verified the dc fault blocking capability of the proposed topology. [ABSTRACT FROM AUTHOR]

DC-DC converters are needed for the future development of high voltage direct current (HVDC) grids, as they allow to interconnect lines with different voltages and topologies. The dc-dc converters can increase the grid controllability adding power flow control, voltage regulation and/or fault blocking capability. The dc modular multilevel converter (dc-MMC) is a non-isolated solution proposed to interconnect HVDC systems with the same line topology. This paper proposes a new dc-MMC with a control strategy, which allows the converter to interconnect different line topologies (e.g., rigid bipole connected to a symmetric monopole). The paper presents the different line topologies in HVDC installations. Then, a mathematical model with a variable transformation is proposed for the new dc-dc converter. A control structure is proposed and implemented in Matlab/Simulink using an average arm model and simplified dc grids. The results validate the control in normal operation, fault blocking capability and post-fault scenario (degraded mode). [ABSTRACT FROM AUTHOR]

A modular multilevel converter control system, based on converter energy storage, is proposed in this paper for two different control modes: active power and dc voltage. The proposed control system decouples the submodule (SM) capacitor voltages from the dc bus voltage. One of the practical applications is the management of active redundant SMs. A practical HVDC system with 401-level MMCs, including 10% redundancy in MMC SMs, is used for validating and demonstrating the advantages of the proposed control system. This paper also presents a novel capacitor voltage balancing control based on \max–\min functions. It is used to drastically reduce the number of switchings for each SM and enhances computational efficiency. [ABSTRACT FROM AUTHOR]

The objective of this two-part paper is to provide clarity to physical concepts used in the field of transformer modeling, to dispel common misconceptions regarding numerical instabilities, and to present unified modeling techniques for low-frequency transients. This paper focuses on proper modeling of nonlinearities (magnetizing branches) since these components are critical to determine the low-frequency behavior. A good low-frequency model should properly represent: normal operation, inrush currents, open and short circuit, out-of-phase synchronization transient of step-up transformers, geomagnetic-induced currents, ferroresonance, and harmonics. This paper discusses the derivation of electrical dual models from the equivalent (magnetic) reluctance networks and the direct application of the principle of duality. It is shown that different dual models need to be derived for different transformer geometries and the advantages and disadvantages of each method are discussed. This paper also compares double-sided versus single-sided dual models, and shows that the double-sided model is a more general approach. The mathematical equivalency of several leakage models (negative inductance, mutual coupling, and BCTRAN) is demonstrated for three-winding transformers. It is also shown that contrary to common belief, a negative inductance is not the source of numerical oscillations, but they occur due to the use of noncorrect topological models for representing the core. [ABSTRACT FROM PUBLISHER]

Negative-sequence current is required to be intentionally injected to support the power grid or compensate the imbalanced load in asymmetrical faults utilizing STATCOM. However, the extreme compensation range of negative-sequence current injection becomes complicated when grid voltage becomes asymmetrical. This article presents a novel off-line strategy for negative-sequence current compensation under two typical kinds of asymmetrical grid faults — single-phase voltage drop and double-phase voltage drop, with the following two benefits simultaneously: maximizing negative current compensation capacity; avoiding iterations and reducing computation burdens. In this paper, the mechanism of DC voltage balancing among three phases in STATCOM is analyzed and a new identification method of negative-sequence current compensation range is explored out. To simplify the calculation, this paper takes the ratio of negative-sequence reactive (Iq-) and active (Id-) current as a variable (s). In this way, the relationship between the extreme compensation range, asymmetrical voltage sag depth of power grid h is drawn with MATLAB. Different from the previous iterative method, the off-line identification method is applied to avoid huge iterations. By fitting the curve, the precise ranges of negative-sequence current compensation under different asymmetrical grid faults are approximated as simple polynomials, thus significantly reducing the computation burdens. Simulation and experimental results verify the practicability of the proposed compensation method. [ABSTRACT FROM AUTHOR]

The modular multilevel DC converter (M2DC) exploits the interleaving between the three legs of an MMC to realize a promising uninsulated DC/DC converter to interconnect HVDC grids. This paper details a current and energies decoupled model of the M2DC. The major idea proposed in this paper is focused on the full energy control generating optimal current references to minimize the internal currents magnitude. The energy sum and difference models are fully detailed. Both current and energy control loops are based on the model inversion principle in order to control all the state variables. The proposed control is based a dynamic control developed with the model inversion principle associated with an optimization of the current magnitude deduced from a quasi-static analysis. All dynamics of the system are then explicitly controlled, which guarantee a good dynamic behavior during the transient. Therefore, current and energy controls are presented in detail. Simulation results show the dynamic behavior of the converter for various operating points. [ABSTRACT FROM AUTHOR]

The hybrid modular multilevel converter (HMMC), consisting of half-bridge and full-bridge submodules (SMs), has become a competitive topology due to the DC fault ride-through capability (FRTC). Redundancy schemes need to be employed to improve the reliability, including fixed-level and voltage-sharing active schemes, as well as passive scheme. However, different schemes affect reliability differently, which entails specific models. The contributions of this paper involve that analytical reliability models of HMMCs are proposed with considerations of voltage stress in active scheme, as well as imperfect bypass switch in passive scheme, and the comparison of different schemes is conducted to help the redundancy design. The reliability of HMMCs is divided into basic and extra components by the requirement of FRTC, which are modeled through the Markov chain and iteration method. A case study is conducted to validate the feasibility and accuracy of the proposed models, and the reliability analysis is presented, together with comparisons of different redundancy schemes. The results illustrate that reliability improvements of both fixed-level mode and passive scheme are prone to suffer saturation effect with the increase of redundant half-bridge SMs, which may even cause reliability decline in voltage-sharing mode. [ABSTRACT FROM AUTHOR]

When a fault occurs on the dc side of the voltage source converter based high voltage direct current (VSC-HVDC) transmission system, the fault current rises quickly due to the low damping of the dc system. Using a dc fault current limiter (DC-FCL) to limit the rise of the fault current can significantly reduce the breaking requirements of the DCCB. A topology of a bidirectional active dc fault current limiter (BA-FCL) based on coupled inductor is proposed in this paper. No expensive full-controlled power electronic devices are used in this topology. Only a few half-controlled power electronic devices are used to achieve active control of the current limiting unit. Compared with many topologies of current limiter at present, the fault current limiting effect of BA-FCL is improved significantly while the cost, volume, topology complexity, and control complexity are reduced. The stress analysis and parameter design of the proposed current limiter are carried out. Finally, the simulation case study and hardware experiment are implemented to verify the good economy and current limiting performance of the proposed topology. [ABSTRACT FROM AUTHOR]

As high-speed railways develop rapidly worldwide, the problems of neutral section and power quality are becoming increasingly prominent. These problems affect the normal operation of the power grid and the electric locomotives. The co-phase power supply schemes were proposed by researchers, which can solve these problems well. Among them, the MMC-based scheme (MMC-5 L) is a representative one. The existing scheme, when applied to the auto-transformer (AT)-fed system which is usually adopted by high-speed railways, needs to install an auto-transformer on the output side. To eliminate the auto-transformer and to obtain the more suitable and superior co-phase power supply schemes to AT-fed system, two improved schemes are proposed in this paper based on the novel MMC-based scheme (MMC-6 L) we proposed before. While establishing the mathematical model, creating the control system, and carrying out simulation verification of the proposed schemes, the proposed schemes are compared with MMC-6 L and MMC-5 L in terms of topological characteristics, control system complexity, power loss, and functionality. The results show that while the proposed schemes can fulfill the functions of the co-phase power supply scheme well like the MMC-5 L and MMC-6 L, they are more suitable and superior for the AT-fed system in terms of control system complexity and power loss. Among them, MMC-5L1CB performs best in power loss, and MMC-4L2CB performs best in control system complexity. [ABSTRACT FROM AUTHOR]

The safety of converters is key to the stable operation of AC/DC hybrid power grids after AC faults. Thyristor valve current is a direct manifestation of the converter observability, but there are no measuring elements inside the converter, so the thyristor valve current can be reflected only indirectly through external electrical quantities. This paper proposes a virtual measurement scheme based on the temporal features of the converter terminal current. First, under the action of the trigger pulse, the polarity characteristics of the AC current and temporal features between the valves are utilized to predictive estimate the valve state. Then, when commutation failures occur and the bypass paths form, the conduction state of valve is constructed based on the relationship between AC and DC current. Last, when the valve is to be shut-off in the bypass path, the blocking state of the valve is corrected based on the unidirectional conductance characteristics of the valve. According to the above analysis, combined with the topological current equation of the converter, the valve current can be calculated in the whole process. Through the simulation of the different valve states and bypass paths and analysis of the field record data, the results show that the valve current can still be accurately calculated based on the virtual measurement scheme. [ABSTRACT FROM AUTHOR]

Most microgrid protection schemes found in published literature suffer from a lack of generality in that they work well for the assumed topology, including type and placement of sources. Other generic protection schemes tend to be too complicated, too expensive, or both. To overcome these drawbacks, a topology-agnostic, scalable, and cost-aware protection based on fundamental principles that work in the presence of high penetration of inverter-based resources (IBRs) is developed and tested in this paper. The protection system also implements stable automatic reconfiguration of the healthy sections of the system after clearance of fault, thus increasing resilience by self-healing. To achieve this ambitious goal, stable inverter models are developed that operate in unbalanced networks in grid-connected and islanded modes, even with 100% IBRs, share power without conflicting controls, and can ride through faults while limiting fault currents. The scheme is tested for primary and backup protection and reconfiguration on the IEEE 123-node feeder in grid-connected and islanded modes with 15 IBRs connected to the system. [ABSTRACT FROM AUTHOR]

The advancements in smart grid technologies had brought forth the prospect of self-healing distribution grid through intentional islanding, aided by the steadily rising penetration of inverter-based distributed generations (IBDGs). Adaptive protection is the key enabler for this resilient grid architecture. For cost-effectiveness, overcurrent relays (OCRs) with adaptive features had been proposed, often with the sensitivity problem due to low short-circuit current magnitude from the IBDG taken into consideration and largely addressed. However, apart from this widely discussed sensitivity problem, there is an underlying issue on selectivity of the OCR which is frequently disregarded when designing an adaptive overcurrent protection scheme for IBDG dominated microgrid. This selectivity problem is mainly caused by the current diversion to load during fault, which is often disregarded when performing OCR grading for a conventional grid. In this paper, this selectivity problem of the OCR is discussed in depth through a comparative study of conventional grid and a modern IBDG dominated grid. The coordination time interval margin violations problems are demonstrated through theoretical calculations and real-time hardware-in-the-loop experiments. This research aims to provide better insights into the selectivity problem as a step towards achieving a cost-effective yet reliable overcurrent-based adaptive protection for IBDG dominated microgrid. [ABSTRACT FROM AUTHOR]

With the increasing number of controllable devices in the grid, devices owned by different entities are supposed to cooperatively support the grid operation. To balance the various interests of the customers and the utility, this paper proposes a two-level scheduling algorithm to address voltage regulation by coordinating the customer-owned battery energy storage system (BESS) and utility-owned load tap changers (LTCs) in power distribution systems. The objective is to find the optimal operation scheduling for both BESSs and LTCs that simultaneously maximize the economic payback and satisfy system operation rules. For BESSs, a local optimization problem is formulated in a chance-constrained manner in major consideration of the economic performance. For the utility interest, a Markov decision process (MDP) and a computationally efficient reinforcement learning (RL) algorithm are utilized to solve the optimal tap setting problem. To coordinate BESSs and LTCs, a global voltage adjustment is applied. The effectiveness of the proposed algorithm is validated via simulations on the IEEE 13-node and 34-node distribution test feeders. [ABSTRACT FROM AUTHOR]

Transformer-customer relationship identification refers to the determination of the physical connection relationship of electricity end-customers and their corresponding transformers. Such connection relationship is critical for distribution utilities to maintain their end-customer profiles. However, management of transformer-customer relationship becomes one of the most emerging challenges due to large number of end-customers and lack of measurement devices in low-voltage distribution systems. To address the above issue, this paper proposes an end-customer data-driven method to identify transformer-customer relationship in low-voltage distribution grid by utilizing the customer field data obtained from advanced metering infrastructure. Specifically, the incidence convolution identification method is proposed to build up the unique mapping relationship between end-customers and their transformers based on the principle of energy conservation. Then the voltage correlation maximization model based on Markov Random Field is proposed, where the voltage correlation matrix is exacted and combined with the adjacency matrix to establish an optimization model to correct the potential abnormal transformer-customer relationship. Finally, the effectiveness of the proposed method is verified by using practical utility tests. [ABSTRACT FROM AUTHOR]

Penetration of DC networks is rapidly increasing in modern power systems. As transient behavior of DC grids is different from that of AC ones, AC grid protection schemes might not be applicable to protect DC networks. Exact fault location is vital for protection of DC networks to reduce repair cost and achieve fast power recovery. This paper proposes a novel topology independent multi-terminal DC scheme to identify fault section and location for DC transmission systems. Voltage and current signals measured at the terminals are analyzed by the least squares error (LSE) algorithm. Then, the proposed scheme uses low frequency components of the signals to locate DC faults offline. Unlike some other methods, it does not require sophisticated sensors and hardware to capture very high frequency content of the signals. Hence, the proposed scheme can be implemented in practice without additional measuring infrastructure. The performance of the proposed scheme is evaluated under various fault conditions for different topologies of DC networks in both overhead lines and cables. Numerous simulations carried out demonstrate that the proposed scheme is quite accurate and provides excellent performance under different fault resistances, sections, and locations. [ABSTRACT FROM AUTHOR]

The missing capability of DC fault current limitation is an inherent disadvantage in the typical half-bridge modular multilevel converter (MMC), which restricts its application in long-distance high voltage direct current (HVDC) systems. The full-bridge submodule (FBSM) and clamped double submodule (CDSM) topologies allow for fault current self-clearing, but also suffer from additional hardware cost and power losses. In this paper, an improved submodule topology utilizing the new reverse-blocking insulated gate bipolar transistor (RB-IGBT) is proposed to improve system economy without compromising its performance. The operating principles and DC fault characteristics of the proposed topology are analyzed in details, including comparison with various topologies in terms of cost, losses, fault current clearing speed and thermal. Compared with the traditional CDSM topology, the proposed RBSM can clear DC faults faster with reduced cost of switching devices. A DC fault protection strategy for MMC-HVDC system is also presented. Simulation results under normal operating, permanent and transient fault conditions are carried out to verify the effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

Modular multilevel converters (MMCs) have been recognized as the most attractive technology for high voltage direct current (HVDC) applications during the last years. Their advantages include the ability to freely control the internally stored energy in the distributed submodules (SMs) and to independently control AC and DC powers. Recent studies showed that an MMC can take advantage of this degree of freedom to supply ancillary services with low energy requirements such as frequency response or power oscillation damping by connecting energy storage systems (ESSs) to its SM capacitors. This paper proposes a modular DC-DC converter as an interface between the energy storage element and the SM capacitor. As it can be built with switches allowing a high switching frequency, it is shown that the volume of the passive components can be reduced in comparison with interface converters known in the literature. The proposed control strategy avoids to transfer the harmonics of a SM to the ESS that prevents to drastically oversize the system. The proposed control method also provides an appropriate energy exchange without affecting the control philosophy of an MMC and it addresses balancing issues. Simulations and a downscaled prototype confirm the relevance of the proposed control. As the proposed interface converter is able to track the power reference with fast dynamics, it provides the same system-level advantages as other interface converters known in the literature but with a reduced volume. [ABSTRACT FROM AUTHOR]

DC technology has gained considerable interest in the medium voltage applications due to the benefits over the AC counterpart. However, to utilize the full capacity of this development, the selection of a suitable power electronic converter topology is a key aspect. From the pool of voltage source converters (VSC's), it is unclear which topology is suitable for multi-megawatt applications at medium voltage dc (MVdc) levels. To address this, the paper proposes a selection guideline based on reliability and optimum redundancy levels of VSCs for MVdc applications. This will be combined with other functional factors such as operational efficiency and return-on-investment. Three candidate multi-level topologies namely three-level neutral point clamped converter (3L-NPC), modular multi-level converter (MMC) and cascaded 3L-NPC (which is being used for the first MVdc link in the U.K.) have been evaluated over two-level-VSC from $\pm$ 10 kV to $\pm$ 50 kV. Results show that with the increase of MVdc voltage level MMC shows better performance whereas at low MVdc voltage levels 3L-NPC is the prominent topology. [ABSTRACT FROM AUTHOR]

This paper analyzes high-frequency interactions between a Modular Multilevel Converter (MMC) and High Voltage Direct Current (HVDC) grid resonances by studying their effect on the system stability. The recent appearance of converter-related instabilities due to high-frequency oscillations at the converter's ac side raises concerns about whether similar interactions can also take place at its dc side. To determine the risks imposed by such interactions within an HVDC grid, this paper assesses the impact of the MMC internal dynamics and dc system resonances on the stability using an analytical impedance-based method. The effect of fault current-limiting inductors, grid topology changes and transmission line length is investigated, indicating that these parameters considerably influence the electromagnetic characteristics of the HVDC grid and consequently the system stability. Furthermore, a sensitivity analysis of the MMC internal controller dynamics on the converter's non-passivity, causing the instability, is performed. [ABSTRACT FROM AUTHOR]

Modular multilevel converter (MMC) based high voltage direct current (HVDC) transmission system is one of the important development trends of DC power grid. After fault isolation, the traditional reclosing method of MMC-HVDC system is directly reclosing DC circuit breaker (DCCB). Once the fault point still exists, DCCB will be tripped again. This method will make the DC system suffer from the secondary strike of fault in a short time, and seriously endanger the service life of DCCB. In order to overcome the drawbacks of the traditional reclosing schemes, this paper proposes a novel adaptive reclosing scheme based on pulse injection from parallel energy absorption module. When dc fault current is interrupted by DCCB, the fault energy stored in current-limiting reactors (CLR) and dc lines is transferred to energy absorption module automatically. By switching on IGBTs embedded in absorption module for a short time, a voltage pulse is injected directly into the faulty line without interference from CLR. Then the nature of fault is identified and the fault distance can also be calculated in the case of permanent faults. The simulation results verify the effectiveness of the proposed reclosing scheme. [ABSTRACT FROM AUTHOR]

DC transformer is an essential equipment for formation of multi-voltage-level DC grid. This paper proposes a novel non-isolated Boost-type alternate arm DC transformer (Boost-AADCT) for medium- and high-voltage level DC grid application. The Boost-AADCT is comprised of three submodule-cascaded arms, two thyristor-cascaded director switches, and two buffer capacitors. Bidirectional power transmission is achieved by alternatively charging and discharging of the intermediate arm following the Boost principle, while the pulsating power component caused by intermittent transmission is actively smoothened by grid-side buffer subcircuits formed by the buffer capacitors and grid-side arms. The active power buffering method increases the tolerance range of voltage ripple of the buffer capacitor, and the required energy storage capacity is resultantly reduced. Circuit configuration, operation principle, and mathematical model are first introduced. Then, the control strategy is proposed, the main circuit parameters are designed, and bidirectional fault-blocking capability is analyzed. Comparison with other DC-DC converters shows that the Boost-AADCT significantly reduces the requirement of semiconductors and has relatively lower synthetic cost. At last, performance of the Boost-AADCT and the proposed control strategies are evaluated by simulation tests conducted in MATLAB/Simulink environment. [ABSTRACT FROM AUTHOR]

modular multilevel matrix converter (M3C) has considerable application potential in motor driving and power systems, but its phasor model is rarely studied. This paper proposes a novel method for modelling and analysis of the M3C in the phasor domain. Firstly, an improved phasor method in matrix form is proposed for direct AC/AC MMC family. By including the frequency information into the phasor expression, it is capable of analysis towards interaction between AC variable groups with different frequencies. Secondly, based on the proposed phasor matrix method, the concept of two-dimensional phase-sequence is proposed to facilitate description and calculation of the AC variables in the 3-by-3 matrix-resembled circuit structure of M3C. Network of each phase-sequence is also derived. With the proposed methods, calculation burden for modelling and analysis of the M3C is significantly reduced. Then, the phasor model of M3C considering the DC, fundamental frequency and 2nd-order harmonic components is established. Finally, validation results with time-domain simulation is provided. [ABSTRACT FROM AUTHOR]

This paper presents the DC fault transient study of a meshed DC grid with high-temperature superconducting (HTS) HVDC cables to integrate offshore wind power. A four-terminal meshed DC grid model with a ±100 kV DC voltage rating is developed. DC circuit breakers (DCCBs) are implemented in the DC grid to deal with DC cable faults. To conduct the fault transient study, the fault scenarios with different fault locations and protection delays are studied. The sensitivity study versus different DC fault locations reveals that the faults on the faulted cable will not cause the quenching of healthy cables. The sensitivity study considering different DC fault protection delays demonstrates that the HTS cables have a current-limiting effect and the long delay of DC fault protection does not result in large fault current and the quenching of healthy cables. Extensive simulations in PSCAD/EMTDC validate the founding. [ABSTRACT FROM AUTHOR]

A novel single-stage doubly grounded transformerless inverter configuration which can buck-boost the output voltage is proposed in this paper. In this transformerless inverter configuration grid neutral is directly connected to PV panel negative rail which suppresses/eliminates the PV leakage currents. In addition, the tracking of maximum power point is possible for wide variation of weather conditions due to buck-boost voltage capability of inverter. Moreover, the proposed inverter topology has symmetrical operation in both half cycles hence injects negligible DC offset current in to the grid. Here the symmetrical operation of inverter is achieved due to one inductor is used for both half cycles of the grid. The proposed topology is realized using five switches, two of which work at 50 Hz and remaining three switches at high frequency which reduces overall semiconductor losses. Further, the proposed inverter topology is controlled through a newly developed modulation technique and possible working modes are analyzed and described thoroughly. For performance validation, the experimental analysis of grid connected proposed inverter is performed on a 1 kVA system and results show that proposed inverter feeds power in to the grid with lesser THD while achieving greater efficiency. [ABSTRACT FROM AUTHOR]

The use of power converters as solid state transformers is an attractive solution to modernize the power network, but this solution has not been fully addressed for MV and HV substations. This paper presents a customized and simple control for the Modular Multilevel Matrix Converter (M3C), specially conceived for its operation on synchronous ports, which is the case of AC substations. The control allows bidirectional power transfer, generation/absorption of reactive power and provisions of ancillary services. The converter is compared to the back-to-back Modular Multilevel Converter (B2B-MMC) where the key performance indicators to carry out the comparison are power efficiency, number of semiconductor devices, passive components required, footprint, voltage cell balance, fault blocking capability and stress of components. The simulation results show the features, performance and attractiveness of the M3C topology in a 33/11 kV, 16 MW substation under different operating conditions, including grid faults and dynamic operation. The M3C presents similar efficiency and performance than the B2B-MMC, but it uses fewer semiconductor devices, passive components and total cell capacitor energy than the B2B-MMC, reducing cost and footprint. The experimental results show the performance of the M3C under less ideal conditions including a substation transformer saturation and power step response. [ABSTRACT FROM AUTHOR]

DC ice melting is an effective technical method against ice disaster on transmission lines. To satisfy the demand for simultaneous de-icing and reactive power compensation for substations, this paper proposed a large-capacity low-cost DC deicer with reactive power compensation, which is mainly composed of rectifier transformer, Static Var Generator (SVG) and diode rectifier. In the proposed topology, SVG and diode rectifier share the rectifier transformer, but rectifier transformer capacity is not increased compared with a single deicer. This paper firstly presents the proposed topology and analyzes its advantages. Then, the rectifier transformer design is introduced, and the SVG control strategy is presented. Simulation results for the proposed device are presented, and an engineering devices with a capacity of 21.8 MVA developed for the 220 kV Fuchong substation is described. The simulation and application results indicate that the proposed devices work well. [ABSTRACT FROM AUTHOR]

The high-speed accurate electromagnetic transient (EMT) simulation of the power electronic transformers (PET) has become a challenge, due to the microsecond-range time steps and the large number of high-frequency semiconductor switches and isolating transformers. Taking the input-series-output-parallel (ISOP) connected cascaded H-bridge (CHB) type dual active bridge (DAB) based PET as an example, this paper proposes a general high-speed equivalent EMT modelling method of PET. First, the isolating transformer within each DAB is discretized into two-port Norton circuits. Second, each CHB-DAB is equivalent to two single-port circuits by eliminating the internal nodes. And the input-side is represented by a Thévenin circuit and the output-side is represented by a Norton circuit. Third, all the CHB-DABs are equivalent to a two-port circuit with all the internal node information preserved. Fourth, the implementation of PET blocking is also considered for startup and fault protective actions. Fifth, the stability of the proposed discrete decoupling method of the PET is verified that it does not introduce specific limitation on the simulation step size. Finally, the developed PET models on PSCAD/EMTDC are shown to be two orders of magnitude faster than the currently available fully-detailed models with negligible loss of accuracy. [ABSTRACT FROM AUTHOR]

This paper introduces a current differential protection scheme, appropriate for application in medium voltage active distribution systems, where it is desired to keep the greatest possible number of loads and DG units energized during a fault. Conventional two-terminal percentage current differential relays are used to form successive, time-current-coordinated, differential protection zones. Multiple time-delayed differential elements in each protection zone guarantee coordination with the zone's lateral protection devices, as well as between successive differential protection zones. Sensitive time-delayed differential elements protect against relatively high-resistance faults, while instantaneous differential elements minimize protection speed whenever possible. Additional emergency differential elements deal with post-fault topology changes and breaker failure conditions enhancing the overall scheme's performance. The proposed scheme is applied to a model of real medium voltage distribution system with distributed generation, considering a ring topology operation. A detailed simulation-based study proves the applicability and enhanced performance of the proposed scheme. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC), owing to the presence of a large number of submodules (SMs) and energy storing elements, requires a large footprint and initial investment. To address these issues, this paper proposes the switched modular multilevel converter (SMMC). It consists of two major elements; the chain-links (CLs), consisting of cascade connection of SMs as in MMC, and the single-pole-triple-throw (SPTT) switches, which can be realized using either the T-type or NPC-type switch strings. The SMMC works on the principle of connecting all the phase-legs in series and their respective positions are mutually interchanged. It offers a compact structure as the SMs count is reduced to 33% of MMC, which results in a much lower energy storage requirement. Furthermore, it does not have inter-phase circulating current problem and hence the CL inductors can also be avoided. The SMMC structure, operating principles, control, and modulation schemes are explained in detail. A detailed comparison of SMMC with the other major existing converters is carried out to highlight the important features of SMMC. The efficacy of SMMC is validated using PSCAD simulation studies with a 19-level grid-connected SMMC model. A 3-phase 19-level SMMC laboratory prototype is developed to further validate its feasibility. [ABSTRACT FROM AUTHOR]

This paper proposes a DC Circuit Breaker (DCCB) topology for the DC fault clearance of the Modular Multilevel Converter based High Voltage Direct Current (MMC-HVDC) grid. By utilizing the voltage clamping and current limiting functions of the pre-charged capacitors in the DCCB, the DC-side short-circuit fault is isolated. First, the topological mechanism and operational principle of the unidirectional topology are analyzed, and the bidirectional topology is provided for backup protection. Then, the residual energy dissipation branch of the DC transmission line is introduced and the reclosing strategy after the deionization process is provided. Further, a step-insert method of the clamping branch is designed to relieve the sudden change of the electrical stresses during the voltage clamping based fault clearance process. Compared to the conventional DCCB schemes, the main advantage of the proposed topology is the decoupling of fast fault isolation and slow energy dissipation processes, which will accelerate the power recovery speed of the healthy parts of the HVDC grid. The proposed approaches are verified first by fully detailed Electro-Magnetic Transient (EMT) simulations on PSCAD/EMTDC then by a down-scaled hardware experiment. [ABSTRACT FROM AUTHOR]

Pole-to-pole dc short circuit fault blocking capability is a major concern when modular multilevel converters (MMCs) are applied in high voltage direct current (HVDC) transmission systems. Traditional MMCs based on half-bridge submodules (HBSMs) cannot block the fault current, thus needing expensive direct current circuit breakers (DCCBs). There are MMCs based on improved submodule topologies that can block dc faults, but usually with significantly increased device cost. This paper proposes an improved HBSM-based MMC (HB-MMC) which needs fewer extra semiconductor devices. The improved HB-MMC is more competitive than other schemes when it comes to investment cost and loss. An H-bridge circuit composed of two director switches and two diode valves is installed around one arm of the HB-MMC, which will not change the direction of current during the normal operation, whereas it can change the direction of the fault current when a pole-to-pole dc short circuits fault is detected. After two director switches have been turned off, a reverse-biased voltage provided by one arm can block the fault current. The topology can be further improved to provide reactive power during faults. Simulation results are presented to validate the features of the proposed improved HB-MMC. [ABSTRACT FROM AUTHOR]

Two key problems in meshed high-voltage direct current (HVDC) transmission grids are managing line power flows and protection against dc faults. Current flow controllers (CFCs) will be required to balance cable currents in meshed dc grids, in order to prevent individual line power capacity limits restricting overall power flow in the grid. Direct current circuit breakers (DCCBs) will be also required to protect HVDC grids from dc faults. This paper demonstrates that the current flow controller functionality can be added into a hybrid CB's design. This paper proposes integrating an interline CFC into the load commutation switch (LCS) of a hybrid DCCB. The integrated design LCS/CFC is analyzed and a state-space model is derived. The control of the CFC is designed and the performance of the LCS/CFC during normal operation is verified by means of MATLAB Simulink and PSCAD simulations. A comparison of the integrated LCS/CFC and the separate design is given. The case studies show a reduction in total power losses, and improved protection operation times can be achieved. [ABSTRACT FROM PUBLISHER]

Smart Grids employ intelligent control applications that require high quality data: fast, secure, and error free. Several researchers have focused on providing techniques for low latency and secured data links for these applications. Bad data detection is however generally provided only at the central level due to limitations in legacy technologies employed in many substations. With the introduction of IEC61850 data sharing within the substation becomes more flexible and transparent allowing more sophisticated management of data quality. Hence, this paper proposes a substation level bad data detection algorithm to facilitate also these types of requirements from applications. The algorithm is based on automatically detecting the substation topology by parsing standard substation description files and online state of circuit breakers and disconnectors. By applying linear weighted least square based state estimation algorithm, bad data from failing current transformers (CT) can be detected. By conducting the verification of different types of bad data, the results show the output of bad data detection algorithm provides higher accuracy than output from both measurement and protective CT in both static and faulty situations. [ABSTRACT FROM PUBLISHER]

This paper revisits the analysis of the well-known infeed effect on transmission lines distance protection. A new adaptive algorithm to overcome this drawback is proposed, which requires solely impedance data and the operational status of power apparatus to perform overreaching distance zones settings. A comparison of the proposed strategy and the traditional one is performed. The obtained results demonstrate that the proposed settings ensure the correct operation of overreaching zones. Thereby, the backup coverage is improved significantly, besides avoiding distance zones overlapping between adjacent lines. It reveals the proposed strategy usefulness and value from the practical point of view, since it can be implemented with technology readily available on the market. [ABSTRACT FROM AUTHOR]

Similar to the conventional three-phase parallel-connected MMC (PC-MMC), the three-phase series-connected MMC (SC-MMC) is a strong potential solution for high-voltage direct current (HVDC) applications. The study of SC-MMC focuses on the control strategy, neglecting its small-signal dynamics, not to mention its stability when interacting with the AC grid. Work on small-signal modeling of MMC is limited to parallel-connected configurations. SC-MMC differs from PC-MMC in structure and harmonic content; hence, it is necessary to establish an accurate model of SC-MMC according to its own characteristics. This paper introduces the circuit and control of SC-MMC and compares it with PC-MMC. Multi-harmonic linearization is used to establish the AC impedance model of SC-MMC over the whole control system, including the third harmonic suppression controller. We take a PC-MMC station of the Wudongde HVDC project as a benchmark to explore the potential application of SC-MMC when constructing new HVDC stations to extract power from an existing DC transmission corridor. The strengths and weaknesses of SC-MMC in HVDC applications are discussed, and it is compared to PC-MMC with regard to the impedance characteristic. [ABSTRACT FROM AUTHOR]

The single-phase-to-ground (SPG) fault at the valve side of the converter transformer is one of the most critical faults threatening the operation of bipolar half-bridge modular-multilevel-converter-based multi-terminal direct-current (HB-MMC MTDC) systems. Following a valve-side SPG fault, the upper-arm submodule (SM) capacitors in the faulty converter may suffer a serious overvoltage, and the grid-side fault currents may experience no zero-crossings. The existing protection methods generally rely on tripping the grid-side alternate-current circuit-breaker (ACCB), which cannot fully isolate the fault. The healthy poles and stations may encounter severe disturbance and be all blocked, which will lead to a power outage of the entire MTDC system. This paper proposes an ACCB-independent scheme based on thyristor-pairs and damping SMs to address these problems. Antiparallel thyristor-pairs are connected in series within the upper and lower arms in each phase. Serial damping SMs are connected within the lower arms to help the lower-arm thyristor pairs cut off the fault currents. Although the proposed additional devices inevitably cause conduction losses, they can effectively protect the faulty converter and healthy circuit in the MTDC system. Simulations in PSCAD/EMTDC have been conducted to verify the effectiveness of the proposed strategy. [ABSTRACT FROM AUTHOR]

The HVDC systems have been employing modular multilevel converters (MMC) due to their unique high voltage high power potential. However, the lack of fault ride-through capability imposes restrictions on MMCs that are based on half-bridge (HB) modules. Since it is necessary to limit the fault currents to protect MMCs from serious short circuit faults against pole-to-pole DC fault, several protection schemes have been introduced to deal with the DC short circuit faults. This paper proposes a new hybrid MMC protective topology consisting of a combination of the HB and three-quarter-bridge (TQB) modules. The TQB behaves like an HB under normal operation and has low power losses compared to other protective topologies. Modulation and control of this configuration are like HB-based MMC. In the proposed hybrid protective topology, during a pole to pole DC fault, the fault current can be either blocked or be limited by TQB-SMs. Both simulations and experiments were performed to verify the operation of the suggested hybrid MMC in different modes of operation. [ABSTRACT FROM AUTHOR]

This paper presents a new power electronic topology for a STATCOM allowing the generation of multilevel AC voltages. This topology is characterized by a modular configuration since it uses two well known four-leg two-level voltage source inverters. A Scott transformer with multiple secondary windings connects the two four-leg inverters to the grid. One of the important features of the proposed power topology is the capability to generate AC voltages with high number of levels, in spite of using only two four-leg two-level voltage source inverters. To maximize the number of voltage levels a geometric progression ratio of 3 between the windings of the transformers connected in cascade is proposed. However, to reduce the turns-ratio span, alternatively a fractional geometric ratio of 1.5 is also proposed and analyzed. A control strategy adapted to the proposed power converter topology is also presented. Besides the control of the reactive power the regulation of the four-leg inverter DC voltage will also be considered. To support the theoretical studies and assumptions, simulations and experiments are presented. Experimental results were obtained using a low power laboratory prototype. The results shown give evidence to the characteristics and features of the proposed power converter topology and control system. [ABSTRACT FROM AUTHOR]

The high voltage direct current transmission system based on modular multilevel converter (MMC-HVDC) technology is now studied and used widely. But traditional half bridge topology of sub module (HBSM) of MMC can't block dc link fault current because of the freewheeling effect of diodes. In order to solve this problem, firstly, this paper improves HBSM topology, a series connected double sub module (SDSM) is designed and dc link fault current blocking capability is realized without tripping ac circuit breaker, so MMC-HVDC with this improved topology can immediately rebuild dc link voltage and resume power transmission. Secondly, the self starting and fault disposing procedure are also designed. At last, simulations in the software PSCAD/EMTDC are carried out to verify its effectiveness and feasibility. [ABSTRACT FROM AUTHOR]

This paper compares how a dc fault affects a multiterminal dc (MTdc) network depending on the HVDC transmission system topology. To this end, a six-step methodology is proposed for the selection of the necessary dc fault protection measures. The network consists of four voltage-source converters converters radially connected. The converters natural fault response to a dc fault for the different topologies is studied using dynamic simulation models. For clearing of the dc faults, four different dc breaker technologies are compared based on their fault interruption time, together with a current direction fault detection method. If necessary, the converters are reinforced with limiting reactors to decrease the peak value and rate of rise of the fault currents providing sufficient time for the breakers to isolate the fault without interrupting the MTdc network operation. The study shows that the symmetric monopolar topology is least affected by dc contingencies. Considering bipolar topologies, the bipolar with metallic return exhibits better fault response compared to the one with ground return. Topologies with ground or metallic return require full semiconductor or hybrid breakers with reactors to successfully isolate a dc fault. [ABSTRACT FROM AUTHOR]

In this paper, a traveling wave based fault location method is proposed for distribution networks. Before fault occurs, an intrinsic distance difference matrix (IDDM) is established based on the characteristics of traveling wave propagation and the topology of distribution network. After the fault, the initial fault traveling wave signals are decomposed into several intrinsic mode function (IMF) signals by variational mode decomposition (VMD), and the first IMF signal is analyzed by teager energy operator (TEO) to determine the arriving time of initial fault traveling waves. According to the double-ended traveling wave method and the arrival time of traveling wave at all recorders, a fault distance difference matrix (FDDM) is built. By comparing the difference between IDDM and FDDM, a fault branch determination matrix (FBDM) and the lateral index Q are used to locate the fault. The effectiveness of the proposed method is verified via EMTP/ATP simulations. Results show that the proposed method has a high fault location accuracy, and does not need that all terminals of lines are installed traveling wave recorders. [ABSTRACT FROM AUTHOR]

DC fault isolation is one of the main challenges of the HVDC grid. DC fault current can be interrupted within several milliseconds by employing hybrid HVDC circuit breaker. However, this scheme is not cost-effective, especially in meshed HVDC grid. In this paper, a novel integrated HVDC circuit breaker by sharing components is proposed to overcome these drawbacks. Suppose that a converter in a meshed HVDC grid is connected to m DC lines. The integrated HVDC circuit breaker consists of m + 1 ultra-fast disconnectors (UFDs), m + 1 load commutation switches (LCSs), m + 1 mechanical disconnectors (DSs), and only one main breaker (MB) and surge arrester (SA). The behavior of the proposed integrated HVDC circuit breaker is similar to that of the conventional hybrid HVDC circuit breaker. These two kinds of breakers have the same operating time, which means the integrated HVDC circuit breaker is fast enough to clear DC faults. Besides, the IGBT modules in the MB and LCSs of the proposed integrated HVDC circuit breaker are connected in one direction, and the m DC lines share a single MB. Therefore, this scheme is more cost-effective compared to the conventional hybrid HVDC circuit breaker. Moreover, the adjacent lines can still be used to transmit power after DC bus faults. Simulation results on a three-terminal HVDC grid are presented to verify the effectiveness and feasibility of the proposed scheme. [ABSTRACT FROM AUTHOR]

DC–DC converters are expected to interconnect High Voltage Direct Current (HVDC) grids with different configurations or voltage levels, which will increase reliability and operational flexibility. The dc Modular Multilevel Converter (DC-MMC) is suggested as a potential non-isolated topology for HVDC applications. This paper presents an energy-based closed-loop control for the DC-MMC. Such control structure provides a full control of the current components, while ensuring energy balancing in normal and fault operation. First, the converter configuration is described and the fundamental equations are presented. Then, the normal operation of the converter is explained from the steady state conditions and the energy and current components. A closed-loop control is designed to ensure a proper dynamic response, balance the internal energies of the converter, and minimize the ac circulating current. Also, the control structure is modified to ensure dc fault ride through capability. Simulation results in MATLAB/Simulink are used to validate the converter control under normal operation and DC faults. [ABSTRACT FROM AUTHOR]

Severe Geomagnetic Disturbances (GMD) pose a threat to the reliability of the United States bulk electrical power system. The NERC reliability standard TPL-007 requires transmission planners to assess potential problems in their service territories due to Geomagnetically Induced Currents (GIC) including transformer thermal assessment. If the assessment indicates a vulnerability, the standard requires the development of a corrective action plan to resolve potential issues. GIC calculation accuracy is critical to the assessment. In this paper, the impact of various geoelectric field calculation methods on the accuracy of calculated GIC is evaluated by comparing with observations for a geomagnetic storm that occurred on 07–08 September, 2017. The GIC calculation is carried out for a fairly large-scale power system model and the comparison with observation indicates that better results are achieved using magnetotelluric transfer functions that incorporate the effects of 3-D earth conductivity. The results also indicate an improvement in the comparisons when the transfer-function derived E-fields are interpolated between the original survey site locations. [ABSTRACT FROM AUTHOR]

In this paper, a static synchronous compensator (STATCOM) is proposed in which a new modular structure with conventional three-phase voltage source inverters is used to multilevel operation. The inverters are connected to a transformer in an open-end winding configuration and with three independent DC links. In this structure, the inverters will be connected in a cascade configuration. Besides the multilevel operation, the system is also characterized by low required blocking voltages for switch ratings, since the proposed STATCOM can apply the double of the DC capacitor voltage to the transformer windings. The development of the control system for the proposed topology is also presented. The operation of the proposed topology and the performance of the developed control system will be tested through several simulation and experimental tests. [ABSTRACT FROM AUTHOR]

In this paper, a simple static var compensating scheme using a cascaded two-level inverter-based multilevel inverter is proposed. The topology consists of two standard two-level inverters connected in cascade through open-end windings of a three-phase transformer. The dc-link voltages of the inverters are regulated at different levels to obtain four-level operation. The simulation study is carried out in MATLAB/SIMULINK to predict the performance of the proposed scheme under balanced and unbalanced supply-voltage conditions. A laboratory prototype is developed to validate the simulation results. The control scheme is implemented using the TMS320F28335 digital signal processor. Further, stability behavior of the topology is investigated. The dynamic model is developed and transfer functions are derived. The system behavior is analyzed for various operating conditions. [ABSTRACT FROM AUTHOR]

This paper investigates the influence of dc network topology with respect to two important aspects: the steady-state losses and the transient fault currents. For this, optimal power flow in a combined ac–dc multiterminal HVDC cable system based on voltage–source converters and the development of prospective fault currents during a pole-to-ground fault is simulated. The results prove that an evaluation of grid topologies must include both of the aforementioned aspects and that no network topology can optimize both at the same time. [ABSTRACT FROM PUBLISHER]

This paper presents a system which predicts the grounding topologies of grounding systems (GS) with one, two, three, or four ground rods in straight line, when no prior information about the grounding topology, soil or rod properties is given. This is achieved through the exploration of the information contained into the impulse response of the GS together with the pattern recognition framework. The proposed system is composed by four main elements, an excitation system, a high-speed data acquisition system, a feature extraction, and a pattern recognition model. Experimental setup comprises the evaluation of the accuracy of the proposed system in discriminating among four grounding configurations, composed by the topologies of one, two, three, and four ground rods in straight line. This paper also proposes a new data driven approach to improve the classification performance, in pattern classification models, when dealing with undersampling problem in the acquired signal used to extract the features. [ABSTRACT FROM AUTHOR]

This paper proposes a novel bipolar modular multilevel converter (MMC) topology with dc fault ride-through capability. The proposed bipolar MMC topology is a hybrid of two types of arms: the half-bridge submodule (HBSM)-based arms (HBSM-arms) which are connected to the ground pole, and the unipolar-voltage full-bridge submodule (UFBSM)-based arms (UFBSM-arms) which are connected to the positive or negative pole. During a pole-to-ground or pole-to-pole dc fault, the hybrid-arm design offers the proposed UFBSM-based hybrid-arm bipolar MMC (UHA-BMMC) the capability to provide additional reactive power to support the ac grid while blocking the dc fault current. The topology, operation principle, dc fault mechanisms, and dc fault ride-through scheme of the UHAB-MMC are presented in this paper. Compared with other possible bipolar MMC topologies, the UHA-BMMC provides good dc fault ride-through capability with a small cost of power-electronic devices. The validity and features of the proposed UHA-BMMC are verified by simulation results conducted in PSCAD/EMTDC. [ABSTRACT FROM PUBLISHER]