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Voltage-controlled three-phase three-leg inverters are widely applied in various occasions. The inverters are generally switched to the current-controlled mode to limit the fault currents when short-circuit faults happen. Under symmetrical fault, the inverter can be controlled as a symmetrical, three-phase current source. However, the voltage limiting will happen under asymmetrical fault. As a result, the fault phase currents will be distorted and cannot be completely controlled. Considering that the voltage limiting is mainly caused by large load impedance of healthy phase under asymmetrical fault, the voltage limiting is avoided by paralleling the virtual impedance with the output filter capacitor in this paper. As a result, the current limiting loop is not broken and the fault phase currents can be effectively controlled. The implementation of virtual impedance in control system and the influence of virtual impedance on the stability of system are also analyzed in detail in this paper. The theoretical results are validated by experiments. [ABSTRACT FROM AUTHOR]

This paper proposes a novel polygonal voltage space vector structure (SVS) having 30 sides, for a star-connected induction motor drive. The SVS eliminates the presence of harmonics up to 25th order from motor phase voltage throughout the entire modulation range, providing a torque profile devoid of lower order pulsations. Linear modulation is extended till 99.63% of base speed without exceeding the motor phase voltage rating. Topology consists of a dc-link fed primary inverter and two equal low voltage modular capacitor fed secondary inverters. Here the harmonics generated by the primary inverter is canceled by the secondary inverter which acts as a switched capacitive filter. Detailed description of the SVS generation and timing calculations are provided in this paper. Effectiveness of the proposed scheme is validated using experimental results, inverter loss calculations, and harmonic analysis. [ABSTRACT FROM AUTHOR]

First harmonic analysis (FHA) is arguably the most widely used analytical technique for wireless power transfer (WPT) circuits due to its simplicity. Although FHA can provide closed-form solutions, the existence of rectifier diode forward voltage drop and higher order harmonics, especially the second and third harmonics at variable duty cycle operation, can significantly deteriorate its accuracy. This paper presents an accurate and efficient method called enhanced multiple harmonic analysis (eMHA) for the optimal design and optimal control of WPT systems. The eMHA method considers the nature of nonlinear rectification networks under nonsinusoidal current and reexamines the concept of the equivalent load. As a result, the rectified WPT system is transformed into a series of linear systems with complex load impedances. The steady-state electric quantities can be then explicitly calculated. This enables eMHA to seamlessly work with numerical optimization algorithms to facilitate the automated design and optimization of WPT systems. An example of optimal design and optimal control of a 10 W WPT system is demonstrated. The results obtained by eMHA and FHA are also compared. A prototype of the designed circuit was constructed. The accuracy and effectiveness of eMHA are verified by experimental measurements. This paper is accompanied by a MATLAB-based analytical tool with a graphical user interface demonstrating the effects of circuit variables on electrical quantities and waveforms. [ABSTRACT FROM AUTHOR]

This paper presents a novel seven-level inverter topology for medium-voltage high-power applications. It consists of eight active switches and two inner flying capacitor (FC) units forming a similar structure as in a conventional active neutral-point-clamped (ANPC) inverter. This unique arrangement reduces the number of active and passive components. A simple modulation technique reduces cost and complexity in the control system design without compromising reactive power capability. In addition, compared to major conventional seven-level inverter topologies, such as the neutral point clamped, FC, cascaded H-bridge, and ANPC topologies, the new topology reduces the dc-link voltage requirement by 50%. This recued dc-link voltage makes the new topology appealing for various industrial applications. Experimental results from a 2.2-kVA prototype are presented to support the theoretical analysis presented in this paper. The prototype demonstrates a conversion efficiency of around 97.2% ± 1% for a wide load range. [ABSTRACT FROM AUTHOR]

In low-power applications of photovoltaic (PV) systems, the transformerless grid-connected inverters have been preferred to increase the efficiency and reduce the cost, size, and power losses when they are compared to the ones with the transformer. A transformerless single-phase inverter topology with a single dc-link capacitor for the grid-connected PV systems is proposed in this paper. The proposed inverter has been simulated by using a cooperation process of the MATLAB and SPICE package programs and it has been implemented for experimental verification. The proposed inverter reduces the high-frequency common-mode leakage current caused by parasitic capacitances of PV panels, whereas it is controlled with the unipolar sinusoidal pulsewidth modulation. Also, the results show that the common-mode voltage remains constant. The efficiency of the proposed inverter has been compared to that of the most common topologies having the dc-link decoupling during the zero voltage states. This paper is accompanied by a video file demonstrating the power loss distribution in the inverter. [ABSTRACT FROM AUTHOR]

This paper describes a dc-link voltage control method of a single-phase back-to-back cascaded H-bridge inverter (SBCI) for a medium-voltage motor drive system. The main advantage of the SBCI topology over the conventional regenerative cascaded H-bridge topology with a three-phase active front-end (AFE) is a simple system structure, which is composed of an input transformer, a power cell, a current sensor, etc. However, the challenging points of the SBCI are larger voltage ripple in the dc-link capacitor and imbalance of dc-link voltages of each phase. The asymmetric dc-link voltage of each power cells could cause unstable operation such as over-modulation due to the lack of the dc-link voltage of a particular phase and result in over-voltage or under-voltage faults. In this paper, the control strategy of the dc-link voltage for the SBCI that uses the negative-sequence voltage of the converter is described. The proposed control method is verified with a computer simulation whose target is a 6.6-kV–1.25-MW medium-voltage drive system. Also, through the experimental setup with the prototype SBCI whose power rating is 16.2 kVA, the dc-link voltage of each AFE has been controlled within a 0.5% error of its reference value at the full load. [ABSTRACT FROM AUTHOR]

This paper proposes a novel method for instantaneous balancing of neutral-point (NP) voltages with stacked multilevel inverters (MLIs) for variable-speed drives. The stacked MLI uses series-connected dc sources and NPs (connecting points of dc sources) to obtain the desired levels. The balancing of NP voltages are obtained by using a low-voltage-capacitor-fed cascaded H-bridge (CHB) per phase of a symmetrical six-phase induction machine (IM), which ensures zero current drawn from NPs (at any given instant). Since no current is drawn from NPs, the single dc-link operation with stacked capacitors is also possible. The scheme is suitable for applications, where low-voltage dc sources and batteries are stacked to form a dc link. A variable-speed operation is done using a seven-level inverter scheme for a symmetrical six-phase IM, which is formed by three dc-link stacked capacitors cascaded with two low-voltage-capacitor-fed CHBs per phase. Furthermore, the method is extended for an open-end IM to obtain a seven-level common-mode eliminated space vector structure using a single dc link. The generalization of this method for any stacked $n$ -level inverter without NP voltage deviation is also presented in this paper. The experimental results and analysis are included to validate the proposed method. [ABSTRACT FROM AUTHOR]

This paper proposes a high-efficiency single-phase T-type boundary conduction mode (BCM) microinverter. The conventional full-bridge BCM microinverter has achieved zero voltage switching (ZVS) and thereby improved the efficiency, but it suffers from high switching losses under light load conditions. The proposed T-type BCM microinverter reserves ZVS and uses a multilevel technique to further decrease the switching losses. The BCM operation with multilevel technique will have too low switching frequency when the grid voltage approaches half of the dc link voltage. To solve this problem, this paper adopts a third operation mode for the T-type switching leg to maintain the switching frequency above a minimum value. The corresponding mode transitions are also detailed to ensure a smooth operation. Because of the turn-offdelay of the freewheeling transistor, the actual lower current boundary deviates from the programmed one, which will distort output current. To address this issue, this paper also proposes a boundary compensation method. A prototype has been built for performance verification, which can test both full-bridge and T-type topology. Compared with the full-bridge BCM microinverter, the proposed T-type BCM microinverter has a higher efficiency over the whole load range. [ABSTRACT FROM AUTHOR]

This paper presents the digital implementation of a boundary controller with unipolar switching characteristic for single-phase voltage source full-bridge inverters. This paper expands the application of a second-order switching surface-based control method to unipolar switching of single-phase voltage source inverters (VSIs) using a finite-state machine. The finite-state machine has been formulated considering four different states of the inverter; positive,zero1, negative, andzero2. The second-order boundary control governs the current state of the system and provides proper switching action to keep the system within the desired reference. The control law is implemented digitally in F28m35x digital control card. A full-bridge inverter topology is used to achieve the three-level voltage switching. Various simulations and experiments were performed in a 550 VA, 120 V, 60 Hz VSI with a digitally implemented controller to verify the theoretical predictions. A high-quality voltage output was obtained for various loading conditions. The transient performance of the controller was investigated using a reference and load changes. A comparison of the implementation was made with the existing classical controllers to verify the fast-dynamic response of the system. [ABSTRACT FROM AUTHOR]

This paper proposes a novel discontinuous pulse-width modulation (DPWM) method to reduce the current harmonics and improve the system efficiency for a single-phase three-level neutral-point clamped inverter. In single-phase inverters, the unipolar pulse-width modulation (UP-PWM) method is commonly used. However, this method has the disadvantage of power losses due to numerous switching operations. Conventional DPWM methods reduce the power losses and improve efficiency but increase the current total harmonic distortion (THD). To overcome these weaknesses, this paper proposes a hybrid DPWM switching method combining two PWM methods: the UP-PWM method and the conventional DPWM method called one-pole clamped PWM method. Since the proposed DPWM method offers all the advantages of both PWM methods, the optimal performance—with regard to the power losses and current THD—is obtained. The combination of two PWM methods is investigated by analyzing the power losses and current THD. Based on the analysis, the process determining the optimal operating condition is introduced. The effectiveness of the proposed DPWM method is demonstrated through simulations and experiments. [ABSTRACT FROM AUTHOR]

This paper proposes a new high-efficiency photovoltaic (PV) converter for grid connection through a high-leg delta transformer. The converter is composed of a symmetrically connected boost converter and three half-bridge inverters. One of the three half-bridge inverters is connected to the boost converter, and the others are directly connected to the PV terminals. As a result, this circuit configuration enables to reduce the power losses in both boost converter and inverters. This paper also proposes a new cooperative control method between the symmetrically connected boost converter and inverter. The control method can reduce the average switching frequency to 75% of that in a conventional one, resulting in a great reduction in the switching power loss. Experimental results confirm that the proposed circuit configuration makes it possible to improve its European efficiency from 91.6% to 94.5%. Moreover, system performance is evaluated on the assumption of maximum power point tracking operation. [ABSTRACT FROM AUTHOR]

The output voltage of power electronic converters is a very important quantity for dynamic control of power electronic systems. In electrical drives without electromechanical position or speed sensor, the terminal reference voltage is used to obtain the rotor position. Dead-time effects and semiconductor voltage drop lead to distortion in the actual output voltage and degrade the control performance when the back electromotive force magnitude is low. Thus, for stable low-speed operation, output voltage sensing becomes necessary. Due to the switching nature of power electronic systems, this is not a trivial task, especially when instantaneous measurement of the terminal voltage is required. In this paper, an instantaneous switching-period average voltage sensing technique is proposed that utilizes a combined approach of oversampling and filtering. Based on the theoretical analysis of the sampling- and filter-induced measurement distortion, a general solution for an optimal filter design is derived. The additional sensing circuit is integrated into the low-side gate driver of the converter outputs. This paper includes details about the hardware implementation and extensive verification measurements. [ABSTRACT FROM AUTHOR]

This paper proposes a new single-phase single-stage switched-boost inverter with four switches. Like the quasi-Z-source inverter and quasi-switched boost inverter (qSBI), the proposed inverter has the main features as continuous input current, buck/boost voltage with single-stage conversion, and shoot-through immunity. Compared to the qSBI, the proposed inverter uses one more capacitor and one less switch. This paper presents the operating principles, pulse-width modulation control strategy, parameter design guidelines, and simulation results for the proposed inverter. To verify the performance of the proposed inverter, an 800-W prototype was built with an 110 V/50 Hz output voltage in stand-alone and grid-connected modes. The simulation and experimental results matched those of the theoretical analysis. [ABSTRACT FROM AUTHOR]

In order to provide high and extendable power levels for inductive power transfer (IPT) system, a parallel multi-inverter system based on modular inverter is presented. Various power requirements can be implemented by an adjustment of the number of paralleled inverters, which provides a high modularity. A master−slave scheme is employed for the switching-driver signals of parallel inverters, where one acts as a leader while others act as followers. Despite the master−slave scheme, the proposed circuit topology has natural robustness because of the equality in terms of the hardware configuration of each modular inverter. For proper parameters, the output phase (current lagging corresponding voltage) of an inverter is lower than the average of output phase of all inverters, when its output voltage lags behind others, and vice versa. Based on this approach, PI controllers are designed to implement phase synchronization for output voltages of all inverters. An IPT prototype supplied by the proposed parallel multi-inverter with three inverters was designed, built, and tested. Experiments show that the proposed parallel multi-inverter system has not only good circulating current suppression capacity but also excellent performance of phase synchronization. The maximum dc−dc efficiency was 94% at a 35.1 kW receiving power. This paper is accompanied by a Matlab/Simulink file demonstrating phase synchronization control. [ABSTRACT FROM AUTHOR]

In this paper, a robust adaptive sliding-mode observer (SMO) is designed based on the surface permanent-magnet synchronous machine (SPMSM) model in rotor reference frame ($\gamma \delta $ -axis), and an online inverter nonlinearity identification and compensation method is proposed. In order to reduce the chattering of the SMO, an adaptive law is presented to help estimate the back electromotive forces of an SPMSM; thus, smaller gains can be set for switching functions of the SMO. The small-signal model of the proposed sensorless scheme is derived for analyzing the steady-state and dynamic behavior of the sensorless scheme. Voltage distortion, caused by nonlinear characteristics of switching devices, not only causes (6k ± 1)th harmonics in phase currents but also leads to a rotor position estimation error. The equivalent amplitude of the voltage distortion can be identified based on the derived small-signal model of the proposed sensorless scheme. To improve the accuracy of the estimated voltage distortion, a recursive restricted total least squares is applied to obtain the estimated amplitude of the voltage distortion. Experimental results validate the proposed sensorless control scheme and its effectiveness. [ABSTRACT FROM AUTHOR]

The efficiency improvement of the on–off controlled Class E dc–dc converter operated at 20 MHz switching frequency is investigated in this paper. It is found that with the on–off control, the input power of the converter during the on mode increases with the increase of the input voltage, and it can be reduced by increasing the switching frequency. With this discovery, a variable switching frequency (VSF) on–off control is proposed, which slightly increases the switching frequency when the input voltage increases, maintaining the input power during the on mode slightly higher than the rated output power over the entire input voltage range, and thus highly improving the efficiency of Class E dc–dc converter at high input voltage. A prototype of 9-V–18-V input, 10-W Class E dc–dc converter has been fabricated and tested in the lab. The experimental results show that the proposed VSF on–off control improves the conversion efficiency of the Class E dc–dc converter by 4%–10% compared to the constant switching frequency on–off control. [ABSTRACT FROM AUTHOR]

In order to reduce switching loss of neutral point clamped three-level inverter (NPC TLI), generally discontinuous pulsewidth modulation (DPWM) is used. But it can result in dc offset and ac ripple on neutral point (NP) voltage. So a novel pulse sequence DPWM (NPSDPWM) is proposed to reduce switching loss and control NP voltage simultaneously in this paper. NP voltage is controlled by choosing proper clamping modes. To avoid unexpected switching action during changing clamping mode, an improved pulse sequence is also presented. The switching loss and NP voltage ripple of NPSDPWM, traditional and proposed DPWM in previous literature are compared, respectively. The experimental results show that NPSDPWM has well NP voltage control ability and the switching losses are reduced effectively. [ABSTRACT FROM AUTHOR]

Three-level inverter has an outstanding performance and is more advantageous in the switching vector selection than two-level inverter. In particular, the neutral-point voltage unbalance and common-mode voltage (CMV) reduction of three-level inverter should be carefully regulated for the appropriate operation, both of which, however, are mutually coupled resulting that the conventional space vector modulation (SVM) scheme cannot deal with them properly. To overcome this limitation, this paper proposes an improved space vector modulation (ISVM) technique to reduce the CMV and neutral-point voltage imbalance simultaneously. The generating mechanism of neutral-point voltage oscillation is derived. Based on the analysis, the proposed ISVM method adopts four voltage vectors (large, medium, small, and zero vectors) with adjusted dwell times to eliminate the ac unbalance of the neutral-point voltage. Considering the occurrence of neutral-point voltage disturbances, the dc neutral-point unbalance voltage is controlled by selecting the P-type or N-type small vector and adjusting the dwell times of small vectors for neutral-point voltage recovery. In addition, a novel switching sequence arrangement method with the minimal number of switches transition in one switching cycles and between switching cycles is proposed to reduce the total switching loss. Theoretical analysis and verification results show that the proposed ISVM scheme can reduce the magnitude of CMV to half of value using the conventional SVM, and an accurate control of ac and dc unbalanced neutral-point voltage can be obtained. [ABSTRACT FROM AUTHOR]

The degradation in power quality causes adverse economical impact on the utilities and customers. Harmonics in current and voltage are one of the most commonly known power quality issues and are solved by the use of a hybrid series active power filter (HSAPF). In this paper, a new controller design using sliding-mode controller-2 is proposed to make the HSAPF more robust and stable. An accurate averaged model of a three-phase HSAPF is also derived in this paper. The design concept of the robust HSAPF has been verified through simulation and experimental studies, and the results obtained are discussed. [ABSTRACT FROM AUTHOR]

This paper studies pulse width modulation (PWM) techniques suitable for a four-level five-phase open-end winding (OeW) drive. The drive comprises a five-phase induction machine, supplied using two two-level voltage source inverters with isolated and unequal dc-link voltages, in the ratio 2:1. A decoupled carrier-based (CB) PWM modulation strategy, based on unequal voltage reference sharing between the two converters, is introduced in this paper. The stability of dc-link voltages in OeW drives is investigated next, using a novel analysis technique. Several modulation methods are analyzed and the results show that application of the coupled PWM technique, with carriers having in-phase disposition, leads to overcharging of the capacitor in the dc-link of the inverter intended to operate with the lower dc-link voltage. On the other hand, the proposed decoupled CB PWM scheme naturally eliminates the dc-link capacitor overcharging problem. These findings are verified experimentally, using open-loop V/f control. Two different decoupled CB modulation methods are compared and the best performing modulation method is selected and incorporated further into an OeW drive with field-oriented control. The presented steady state and transient experimental results demonstrate that the decoupled CB PWM technique is suitable for high-performance variable speed drive applications. [ABSTRACT FROM AUTHOR]

This paper presents a pulse width modulation (PWM) technique for the minimization of the leakage current in the grid-connected/stand-alone transformerless photovoltaic (PV)-cascaded multilevel inverter (CMLI). The proposed PWM technique is integrated with the MPPT algorithm and is applied to the five-level CMLI. Furthermore, using the proposed PWM technique the high-frequency voltage transitions in the terminal and common mode voltages are minimized. Thus, the proposed PWM technique minimizes the leakage current of the PV array and electromagnetic interference filter requirement in the system without addition of any extra switches. Furthermore, this paper also presents the analysis for the terminal voltage across the PV array and the common mode voltage of the inverter based on the switching function. Using the given analysis, the effect of the PWM technique can be analyzed, as it directly links the switching function with the common mode voltage and leakage current. Also, the proposed PWM technique requires reduced number of carrier waves compared to the conventional sinusoidal pulse width modulation technique for the given CMLI. Complete details of the working principle and analysis with the support of simulation and experimental results of the proposed PWM technique are presented in this paper. [ABSTRACT FROM PUBLISHER]

This paper proposes a dual-space vector control scheme for the open-end winding permanent magnet synchronous motor (OEW-PMSM) drive fed by the dual inverter with a single dc supply. Potential zero-sequence current in the open-end winding drive system has to be considered since it causes circulating current in the winding and leads to high current stress of power semiconductor devices and high losses. Zero-sequence current in open-end winding ac motor drives is usually caused by the zero-sequence voltage, and therefore switching combinations which do not produce zero-sequence voltage are used to synthesize the reference voltage in existing methods. But even so, the zero-sequence voltage can also be produced by the dead time of the inverter. In order to suppress zero-sequence current in the OEW-PMSM drive, a dual-space vector control scheme is proposed and a novel dual-inverter space vector pulse width modulation (PWM) with the zero-sequence voltage reference is employed to regulate system zero-sequence voltage in this paper. Compared with existing dual inverter PWM strategies, the novel algorithm build a regulation mechanism for the zero-sequence voltage. The proposed method is compared with the conventional vector control by simulations and experiments, and the results shown that the proposed scheme can suppress zero-sequence current effectively. [ABSTRACT FROM AUTHOR]

Magnetically coupled impedance-source (MCIS) networks are recently introduced impedance networks intended for various high-boost applications. It employs coupled magnetic in the circuit to achieve higher voltage gain. Various MCIS networks have been proposed in the literature for myriad applications; however, due to effective role of system modeling in the closed-loop controller design, this paper is allocated to small-signal modeling and analysis of MCIS converters. The modeling is performed by means of the circuit averaging and averaged switch technique. A generalized small-signal derivation is demonstrated for pulse width modulation (PWM) MCIS converters and it is shown that the derived transfer functions can simply be applied to Y-source, Γ-source, and T-source impedance networks. Various transfer functions for capacitor voltage, output voltage, magnetizing current, input and output impedance are derived and have been validated through frequency and dynamic responses of computer simulation results. In addition, a comprehensive analysis has been done for all mentioned PWM MCIS converters regarding their circuit parameters. Furthermore, the effect of considering the equivalent series resistances of capacitor and inductor on the stability margin of MCIS converters is revealed in this paper. Finally, in order to validate the derived transfer functions and to consolidate the perfumed analysis, experimental results are presented for all mentioned MCIS converters. [ABSTRACT FROM PUBLISHER]

Based on the Z-source inverter, this paper proposes a novel commutation torque ripple reduction strategy for brushless DC motor (BLDCM). The proposed strategy employs the same modulation mode in both the normal conduction period and the commutation period, and the commutation torque ripple is reduced by regulating the shoot-through vector and active vector duty cycles. The proposed detection method acquires the end point of commutation by comparing the clamped terminal voltages with reference zero level, and the signal-noise-ratio of the detection is improved by avoiding the attenuation of the terminal voltages. Furthermore, a certain pulse width of the shoot-through vector can not only reduce the commutation torque ripple but also provide a new opportunity to detect the end point of commutation. Moreover, Z-source inverter provides the buck–boost ability for BLDCM drive system, then the dc voltage utilization can be improved, and the safety of the drive system can also be improved. In addition, this paper analyzes the terminal voltages during each vector. The experimental results verify the correctness of the theories and the effectiveness of the proposed approach. [ABSTRACT FROM PUBLISHER]

The increasing interest in multiphase drive systems has led to the extension of inverter topologies and pulse width modulation (PWM) methods from three-phase to multiphase occasions. Carrier-based PWM (CPWM) dominates space vector PWM when the phase number increases, because of its simple computation and modular implementation. Although intensive work has been done on modifying PWM methods to reduce the common-mode voltage (CMV), not enough work has been done on CPWM methods with CMV reduction for multiphase drives. This paper extends the phase-shifted sinusoidal PWM (PS-SPWM) method for five-phase and six-phase two-level voltage-source inverters (VSI) and employs the intersection-plotting method and Fourier analysis to reveal the nature of the CMV. Both experiment and simulation results comply with theoretical analysis that compared with the conventional SPWM, the PS-SPWM can effectively reduce the CMV in peak-to-peak value and RMS value, though it leads to a higher phase current distortion. In addition, the hardware realization of PS-SPWM for multiphase inverters by a distributed control system is presented in this paper. [ABSTRACT FROM AUTHOR]

This paper identifies extra junction capacitances and switching commutation loops introduced by line-frequency devices (i.e., non-active every other half line cycle) in three-level ac/dc converters and investigates the corresponding effects. Junction capacitances and power loops are well known as the key factors that impact converter switching loss and device stress, thus influence device selection, power stage layout, and thermal design. By examining switching transients of the commonly used T-shaped and I-shaped three-level converters, the cause and mechanism of the extra junction capacitances and power loops are presented. The impacts on switching loss, device voltage stress, and ac-side voltage/current distortion are respectively reported and analyzed. A loss calculation scheme for the three-level converter to include that extra loss is proposed. A power layout scheme to mitigate the device voltage stress is provided. Compensation and modeling of the voltage and current distortion are also proposed. Experimental results conducted on several types of three-level converter prototypes including a gallium nitride based 115 $V_{{\text{ac}}}{\text{/650}}$ Vdc/1.5-kW/450-kHz Vienna-type rectifier and a SiC mosfet based 1-kV/10-kW/280-kHz three-level active neutral-point-clamped inverter confirm the presented effects and verify the associated analysis and solutions. [ABSTRACT FROM AUTHOR]

The strive to increase the energy yield of photovoltaic (PV) power systems has made PV module integrated dc–dc converters (dc-MICs) a reality of modern PV plants. These converters regulate their input voltage, and their dynamic behavior is heavily influenced by the non-linear characteristic of the PV module. The regulation of the PV module voltage and average inductor current by means of a linear cascaded controller is a popular control technique, simplifying the converter dynamics, and providing inherent current limiting; however, it is prone to instability depending on the interaction between the PV source and the interfacing converter, as well as the value of the controller parameters. These factors present a clear challenge for control design; moreover, the converter transient response undesirably depends on the PV module operating point. In order to solve these issues, while maintaining regulation of PV module voltage and average inductor current, this paper proposes to adopt a non-linear controller designed with the feedback linearization control (FLC) technique. The control laws are derived and implemented in a non-inverting buck–boost dc module integrated converter, as this is a favorite topology for the PV interfacing application. A digitally controlled converter prototype is built and used to obtain experimental results, where the FLC technique is compared with a linear cascaded control technique. The results confirm the superior performance of the presented FLC technique, which is robust and able to regulate the converter input voltage with fast and consistent dynamics, regardless of the PV module or load operating conditions. [ABSTRACT FROM AUTHOR]

SiC mosfets allow a higher frequency, lighter weight inverter over their Si counterparts for electric vehicle (EV) applications. However, using SiC-based EV traction inverters is likely to increase the shaft voltage in an ac motor drive system, which significantly affects the reliability of the system. This paper investigates the impact of high-speed switching of SiC devices and high switching frequency of SiC-based inverter on the common-mode voltage (CMV) and the shaft voltage. It is theoretically illustrated and experimentally demonstrated that the high switching frequency increases the amplitude of the shaft voltage, while the fast switching speed has limited influence on both CMV and the shaft voltage. Afterward, active zero state pulsewidth modulation (AZSPWM) and common-mode chokes are employed to mitigate the shaft voltage. The experimental results show that either the AZSPWM modulation scheme or common-mode chokes have the capability to minimize the shaft voltage. Better performance can be achieved by utilizing both techniques simultaneously. It is also observed that the high switching frequency enabled by the fast-speed SiC device is able to be helpful to the use of reduced shaft voltage technologies. [ABSTRACT FROM AUTHOR]

Several applications need a high power, high output voltage ac/dc converter. The structure includes a dc/dc resonant stage, which is fed from a three-phase line. Due to standards, rectified dc input voltage varies largely from 400 to 750 V affecting the adversely overall design and current levels. In fact, losses in the inverter become unbearable if both switching frequency and transferred power are desired beyond a certain level. In those cases, it is necessary to connect several switches in parallel. As an alternative, the new switches can configure a new modular structure instead, adding more flexibility in the control to compensate input voltage variations. As a result, the required circulating current is reduced to a half, with benefits in total power losses. Moreover, the nature of the topology allows a reconfiguration of the resonant net (LCC) for low power, reducing even further the minimum circulating current under those conditions (fluoroscopy, for instance). In this paper, the new multilevel resonant topology is mathematically modeled and proposed for radiography and fluoroscopy. An example illustrates the design procedure for a given application at 100 kW, 50–150 kV. [ABSTRACT FROM AUTHOR]

Impedance-source inverters using coupled inductors have been investigated as alternatives for providing high step-up voltages. However, leakage inductances of the coupled inductors have commonly led to lower overall effectiveness, in addition to generating high dc-link voltage spikes. The latter raises voltage stresses of switches, which in turn, may reduce the power levels of the inverters. A high step-up Y-source inverter has therefore been proposed in this paper to provide a high boost with a smooth dc-link voltage ensured by proper recycling of the leakage energy. These features have been verified by comparing simulation and experimental results of an existing Y-source and the proposed inverters. Factors compared are their respective boost ratios, voltage stresses, current stresses, and dc-link voltage spikes. [ABSTRACT FROM AUTHOR]

A 1-φ hybrid nine-level inverter (H9LI) topology has been proposed in this paper. The proposed H9LI topology uses a simple phase disposition pulsewidth modulation strategy to generate nine-voltage levels in the output. The main advantage of this topology is that it has a low switch count (ten switches) compared to the existing nine-level inverter topologies. To regulate the voltage across auxiliary capacitor, two innovative control techniques are proposed, which are integrated with the inverter modulation technique itself. Hence, it does not require any extra voltage balancing circuits to maintain the voltage across the auxiliary capacitor and input dc capacitors. A major advantage of these control techniques is that they eliminate the sensing of the coupled inductor current. Another significant advantage of H9LI is that loss distribution among all the power switches is more uniform compared to existing nine-level inverters. Due to low part count and absence of extra voltage balancing circuits, the H9LI achieves higher efficiency (η ≍ 94.5%) and lower cost. Furthermore, the requirement of filter size reduces due to the presence of coupled inductor in H9LI. The proposed 1-φ grid connected H9LI is verified through MATLAB/Simulink simulations and validated through experiments on a laboratory prototype of 400-VA rating. [ABSTRACT FROM AUTHOR]

In this paper, a novel space-vector pulsewidth modulation technique for a five-level active neutral-point clamped (5L-ANPC) inverter is proposed to eliminate the common-mode voltage (CMV). For the 5L-ANPC inverter, which produces a good output voltage performance and lowdv/dt, the total 125 voltage vectors can be generated, among which the proposed scheme employs only 19 voltage vectors producing a zero CMV. Due to the limitation of voltage vectors selected, the dc-link capacitor voltages of the 5L-ANPC inverter cannot be balanced by themselves. Therefore, the capacitor voltages of the inverter should be controlled by choosing the redundant switching states appropriately. The validity of the proposed modulation scheme has been verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

Common-mode voltage (CMV) is known as a major cause of premature motor failures. The form and amplitude of the CMV generated by any converter depends on both the circuit topology and modulation technique. Among single stage ac–ac converters employed in drive applications, the Z-source ultra sparse matrix converter (ZSUSMC) is a desirable choice due to reduced number of switches in its structure and voltage boosting capability. Based on these considerations, this paper aims to: 1) theoretically determine and compare the CMV of the ZSUSMC with four well-known impedance networks, namely, cascaded, switched-inductor, quasi, and series, in its structure and 2) propose modulation techniques for CMV reduction in the ZSUSMCs. To this end, first, it is shown that the ZSUSMC, depending on the impedance network used in its structure, provides more freedom to choose from redundant switching states compared to the ultra sparse matrix converter. Then, by taking advantage of this feature, novel modulation strategies that attenuate the CMV without affecting the boosting capability are developed. The proposed modulation schemes are based on avoiding the switching states most contributing to the CMV during a switching period. Through hardware-in-the-loop studies, the effectiveness of the proposed modulation strategies in reducing the CMV of the ZSUSMCs is verified. [ABSTRACT FROM AUTHOR]

In voltage-source inverters (VSIs), dead time is used to prevent shoot-through over switching devices. However, the existence of the dead time will distort the output phase current, which degrades the performance of the inverter as well as influences the common-mode voltage (CMV), particularly in CMV elimination relevant modulation schemes, such as zero-common-mode (CM) pulsewidth modulation (PWM)-based paralleled inverters. In the light of the situation that the normal sampling-based dead-time compensation (DTC) methods are often disturbed by the current ripple, this paper introduces a novel DTC method for the VSI, which can mitigate the impact of the current ripple and improve the accuracy of DTC. The proposed method deduces the real-time current ripple, which can reconstruct the actual trajectory of phase-leg currents, and the peak values corresponding to rising and falling edges for PWM signals can be predicted. In this way, DTC can be implemented based on the direction of relevant instantaneous switching currents and finally improves the accuracy. Especially, the current-ripple-prediction-based DTC can help to improve the CMV distortion caused by the dead time for paralleled inverters with zero-CM PWM. Simulation and experimental results are provided to validate that the proposed method can be applied to different topologies and modulation schemes with good performance. [ABSTRACT FROM AUTHOR]

The three-phase four-wire inverter with split dc-link capacitors can supply unbalanced loads. For the purpose of reducing the filter inductors, a neutral inductor could be introduced into the neutral line. This paper analyzes the operation principle of the three-phase four-wire inverter with split dc-link capacitors when a neutral inductor is introduced. It is illustrated that the neutral inductor can reduce the zero-sequence switching harmonics in the voltages between the phase-leg midpoints and the output neutral point, thus the filter inductors can be reduced. The optimized design of the neutral inductor and filter inductors is proposed with the considerations of the inductor current ripple, the ability of supplying unbalanced loads, and the total energy stored in the inductors. The equivalent circuits of the three-phase four-wire inverter with split dc-link capacitors and neutral inductor is derived in the α–β–0 frame, and the zero-axis voltage regulator is modified to suppress the third-order harmonic in the zero-sequence current caused by the deadtime of the drive signals for the power switches. Finally, the experimental results from a 9-kW prototype are provided to prove the effectiveness of the proposed optimized design of the neutral inductor and filter inductors and the control strategy of the inverter. [ABSTRACT FROM AUTHOR]

In this paper, a modified selective harmonic mitigation pulse amplitude modulation (SHM-PAM) is presented to be capable of canceling all triplen harmonic orders and suitable for single-phase application of five-level type of voltage source inverters. To this end, a new constraint is established for the two switching angles (α1, α2) to derive the new formula for the harmonics’ amplitude, which results in self-elimination of all triplen harmonics (e.g., 3rd, 9th, 15th, …). The fifth and seventh harmonic orders are mitigated through normal operation of the proposed SHM-PAM technique. It is also shown that the proposed technique is extendable to other multilevel voltage waveforms and a flowchart of self-elimination of all triplen harmonics has been presented. Mathematical analysis supported by experimental investigations show the desired performance of the proposed SHM-PAM algorithm on a two-cell single-phase cascaded H-bridge inverter as a typical five-level configuration in dealing with linear and nonlinear loads. Then, it is demonstrated that the maximum number of harmonic orders would be controlled with the minimum number of available angles in a low switching frequency voltage waveform. [ABSTRACT FROM AUTHOR]

In this paper, a novel space vector modulation (SVM) strategy is proposed and designed for dual three-phase three-level motor drives based on vector space decomposition (VSD), which could be applied for high-power and high-reliability applications. The key of the proposed method is to design two decoupled groups of voltage vector candidates for synthesis on α − β subspace and x − y subspace, respectively. The two decoupled groups of voltage vectors will synthesize respective voltage references on α − β subspace and x − y subspace, while having no impact on each other. The redundant small voltage vectors and zero-sequence voltage vectors are utilized to mitigate voltage oscillation in midpoint of dc link and suppress zero-sequence current component for dual three-phase windings with a common neutral. For comparison, another VSD-SVM strategy is designed based on traditional solution, which cannot offer closed-loop control on x − y subspace. Both simulation and experiments have been given to verify that the proposed decoupled VSD-SVM can suppress harmonic components on x − y subspace besides tracking torque components on α − β subspace. Furthermore, the harmonic performance of the proposed decoupled VSD-SVM has been compared with the traditional VSD-SVM strategy and the carrier disposition based pulsewidth modulation. [ABSTRACT FROM AUTHOR]

Although high-frequency circulating current exists in parallel-operated inverters, it has not attracted as much attention as low-frequency circulating current, and thus has not been analyzed in detail previously. In this paper, a mathematical model and analysis are presented, which reveal the spectrum components and their changing trends of the circulating currents caused by carrier phase differences. The impact of carrier phase difference on high-frequency circulating current is also analyzed and verified. A closed-loop control scheme is proposed to suppress the switching frequency circulating current caused by carrier phase difference. In addition, the deadbeat and closed-loop control are combined to suppress the low- and high-frequency circulating currents simultaneously, to improve the overall performance of circulating current suppression. The effectiveness of the proposed scheme is verified by the simulation and experimental results acquired from a laboratory platform. [ABSTRACT FROM AUTHOR]

This paper proposes a control method for a five-level hybrid flying-capacitor (5L-HFC) inverter, of which structure stems from the conventional five-level active neutral-point-clamped (5L-ANPC) topology by dividing the dc-link stage into three series-connected capacitors. In this inverter, the voltage stress on the power switches connected to the dc link is reduced by a half compared with that of the 5L-ANPC topology, thus the lower number of equally voltage-rated power devices can be employed. Also, the power losses in the 5L-HFC inverter are more evenly distributed than in the 5L-ANPC. In order to balance the dc-link capacitor voltages, a third-order harmonic offset injection is applied. When a diode rectifier is used to supply the dc bus voltage, the balancing method is not effective if the modulation index is higher than 0.64. Thus, an auxiliary circuit is needed to support the balancing of the dc-link capacitor voltages. However, the unbalancing problem can be overcome in a full-range operation without the auxiliary circuit if the back-to-back configuration is utilized. Finally, simulation and experiment results have verified the performance of the 5L-HFC inverter with the proposed control method. [ABSTRACT FROM AUTHOR]

This paper proposes the new clamping angle control (CAC) pulse width modulation (PWM) method to restore its maximum linear modulation range of voltage source inverters (VSIs) reduced by the duty ratio limitation in hardware implementation, which makes the VSIs to operate nonlinearly in the high modulation range. The deadtime and the bootstrap gate driver circuit mainly cause this duty ratio limitation in practice. In particular, the bootstrap gate driver circuit is used in many industrial applications by avoiding the additional power supply to apply the gate-source voltage of power switches, and therefore making the VSIs to be small size with the low cost. First, the proposed CACPWM method is theoretically analyzed. Then, it is applied in the high modulation range to overcome the limitation of the duty ratio due to the use of the bootstrap gate driver circuit. Thereafter, its practical effectiveness is verified by both simulation and experimental tests. Also, the resulting harmonic distortions are compared with those by the conventional PWM methods. [ABSTRACT FROM AUTHOR]

Parallel inverters are commonly adopted in high-power applications, for instance wind energy systems, smart transformers, and power conditioners. Meanwhile, interleaved pulse width modulation is usually considered as an optimal approach to reduce the current ripple and harmonics of the parallel inverters. However, in the case of a common dc link, the problem of circulating current emerges and leads to performance degradation. This paper aims at investigating the influence of different modulation techniques on the circulating current of two neutral-point-clamped (NPC) inverters under interleaved operation. Two modulation techniques, phase disposition (PD) and alternative phase opposite disposition (APOD), have been studied and compared in terms of current ripple, spectrum quality, and circulating current. Though the PD modulation was regarded as the optimum solution in most of the single-NPC cases, it offers worse performance in the two parallel NPC applications due to higher circulating current. Simulation and experimental validations are provided and show that the APOD leads to much lower circulating current and similar current ripple as well as spectrum quality compared to the PD. [ABSTRACT FROM AUTHOR]

Inductive power transfer (IPT) for battery charging applications has significant advantages over the traditional plug-in system. Since misalignment between the primary and secondary windings is inevitable, it is of significance to improve the misalignment tolerance of IPT systems with constant-current (CC) and constant-voltage (CV) outputs for battery charging. In this paper, the load-independent output characteristic of the hybrid topology and the function switching between CC and CV of the reconfigurable topology are analyzed. Besides, a hybrid and reconfigurable IPT system with 3-D misalignment tolerance for CC and CV outputs is proposed, simplifying or even canceling control schemes. Moreover, a novel parametric design method is given for the IPT system, which can suppress the fluctuation of the output voltage/current within a certain range of misalignment. In order to validate the performance of the proposed topology, a 1-kW prototype is built, and the corresponding experiments are carried out. In the CC/CV mode, the system can operate with the longitudinal misalignment to 50% when the load varies from 36 to 480 Ω, and the fluctuation of the output current/voltage is within 5%. Similarly, the misalignment in Y- and Z-axis is 12.5% and 33.3%, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a novel three-phase DC-link multilevel inverter topology with reduced number of input DC power supplies. The proposed inverter consists of series-connected half-bridge modules to generate the multilevel waveform and a simple H-bridge module, acting as a polarity generator. The inverter output voltage is transferred to the load through a three-phase transformer, which facilitates a galvanic isolation between the inverter and the load. The proposed topology features many advantages when compared with the conventional multilevel inverters proposed in the literatures. These features include scalability, simple control, reduced number of DC voltage sources, and less devices count. A simple sinusoidal pulse-width modulation technique is employed to control the proposed inverter. The performance of the inverter is evaluated under different loading conditions and a comparison with some existing topologies is also presented. The feasibility and effectiveness of the proposed inverter are confirmed through simulation and experimental studies using a scaled down low-voltage laboratory prototype. [ABSTRACT FROM AUTHOR]

Owing to low cost, small size, and low weight, transformerless inverters became prominent in single-phase grid connected photovoltaic (PV) systems. Key issues pertaining to these inverters include suppression of common mode (CM) leakage current and improvement of conversion efficiency. Achieving higher efficiency in single-phase grid-connected photovoltaic systems depends on the number of stages involved in feeding power to the grid, predominantly, if the PV array voltage is less than the peak value of the grid voltage. In this paper, an integrated dc–dc converter based grid-connected transformerless PV inverter is proposed which is aimed at maintaining high efficiency, even if the PV array voltage falls below the peak value of grid voltage (efficient operation at an extended input voltage range). A modulation strategy is discussed in order to minimize the flow of CM leakage current. Further, the efficiencies of certain transformerless inverter topologies are analyzed and compared with that of the proposed topology. Detailed simulation studies are carried out in MATLAB/Simulink environment to verify the analysis. Experimental results for a scaled down laboratory prototype are included as a proof-of-concept to validate the claims. [ABSTRACT FROM AUTHOR]

In this paper, a modular control approach has been proposed for a single- and three-phase differential-mode Ćuk inverter (DMCI) operating with a recently proposed discontinuous-modulation scheme that offers tangible performance benefits over conventional continuous modulation scheme. The modular control scheme uses a combination of a transformation and adaptive control law to meet tracking requirements in the presence of converter nonlinearity. Experimental results for the single- and three-phase DMCI are provided for startup, steady state, load transition, and total harmonic distortion using different types of loads, which validate the efficacy of the implemented modular tracking controller. Further, detailed stability of the closed-loop DMCI module is provided. [ABSTRACT FROM AUTHOR]

This paper presents a model-based method to diagnose single- and multiple-transistor open-circuit (OC) faults in grid-tied three-phase voltage-source inverters (VSIs). The method is based on calculated average bridge arm pole-to-pole (PTP) voltages and error-adaptive thresholds. Only existing signals for closed-loop control are needed; thus, this method can be easily embedded in the system without extra sampling and circuits. Average PTP voltage deviations are chosen as diagnosis variables, which show considerable distinction quickly after fault. Consequently, fast fault diagnosis speed can be achieved. The fault diagnosis time for single fault can be as short as two switching periods. Besides, diagnosis variables show the same faulty characteristics in inverter mode and rectifier mode; thus, this method is effective in both modes. Moreover, for the first time, the variation of inductance caused by conducted current is considered to obtain a more accurate variable-inductance model, and the thresholds are updated according to mathematically estimated diagnosis variable calculation errors from sampling error, inductance error, dead time, and delay time, which maintains high robustness as well as fast speed. Finally, the effectiveness of the proposed method is validated with experiments. [ABSTRACT FROM AUTHOR]

In this paper, a novel platform for the single phase switched-capacitor multilevel inverters (SCMLIs) is presented. It has several advantages over the classical topologies, such as an appropriate boosting property, higher efficiency, lower number of required dc voltage sources, and other accompanying components with less complexity and lower cost. The basic structure of the proposed converter is capable of making nine-level of the output voltage under different kinds of loading conditions. Hereby, by using the same two capacitors paralleled to a single dc source, a switched-capacitor (SC) cell is made that contributes to boosting the value of the input voltage. In this case, the balanced voltage of the capacitors can be precisely provided on the basis of the series–parallel technique and the redundant switching states. Afterward, to reach the higher number of output voltage levels, two suggested SC cells are connected to each other with a new extended configuration. Therefore, by the use of a reasonable number of required power electronic devices, and also by utilizing only two isolated dc voltage sources, which their magnitudes can be designed based on either symmetric or asymmetric types, a 17- and 49-level of the output voltage are obtained. Based on the proposed extended configuration, a new generalized version of SCMLIs is also derived. To confirm the precise performance of the proposed topologies, apart from the theoretical analysis and a complete comparison, several simulation and experimental results are also given. [ABSTRACT FROM AUTHOR]

This paper presents a new application of power and voltage balance control schemes for the cascaded H-bridge multilevel inverter (CHMI)-based solid-state transformer (SST) topology. To reduce load on the controller and simplify modulation algorithm, a master–slave control (MSC) strategy is designed for the dual active bridge (DAB) stage. The master controller executes all control and modulation calculations, and the slave controllers manage only device switching and protection. Due to the inherent power and dc-link voltage unbalance in cascaded H-bridge-based SST, this paper presents a compensation strategy based on three-phase dq decoupled current controller. An optimum zero-sequence component is injected in the modulation scheme so that the three-phase grid currents are balanced. Furthermore, to tightly regulate the output voltage of all the DAB modules to target value, a dynamic reference voltage method is also implemented. With this proposed control method, the three-phase grid currents and dc-link voltage in each module can be simultaneously balanced. Finally, simulation and experimental results are presented to validate the performance of the controller and its application to microgrid SST. [ABSTRACT FROM PUBLISHER]

A virtual space vector modulation technique reducing both magnitude and third-order harmonic component of the common-mode voltage (CMV) in a two-level voltage-source inverter (VSI) is proposed in this paper. The presented method employs a set of virtual space vectors constructed from original stationary space vectors to conduct modulation. Since the created virtual vectors have the lowest instantaneous and zero average CMVs, both the magnitude and third-order harmonic component of the generated CMV are reduced, contributing to better overall CMV performance and common-mode filter design in VSI applications. Three variants of the proposed modulation method using different virtual space vector combinations are presented. The concept of the virtual space vector modulation technique demonstrated with two-level inverter in this paper can also be extended to multilevel inverters. Simulation and experimental results, as well as comparisons with existing methods are provided to verify the proposed technique. [ABSTRACT FROM AUTHOR]

Based on the Z-source inverter, this paper proposed a novel approach to zero-crossing point (ZCP) detections during the shoot-through vectors for sensorless brushless dc motor (BLDCM). The proposed approach separates the ZCP detections from speed adjustment, and makes the shoot-through vector not influence the motor speed-adjustment directly, while the zero-vectors and active-vectors are used exclusively to adjust the speed of BLDCM. With the proposed approach, the sensorless BLDCM can operate in a wide speed range without switching the detection points and the reference levels, and it is unnecessary to change the reference levels according to the PWM technique. The terminal voltages limited by diode can be directly compared with the reference zero level during the shoot-through vectors, so as to reduce the detection error caused by attenuation. Moreover, Z-source inverter not only provides boost voltage for sensorless BLDCM drive system, but also improves the utilization rate of dc source voltage and the safety of the drive system. In addition, this paper analyzed the terminal voltages of the floating phase during each vector. The experimental results verified the correctness of above theories and proved the effectiveness of the proposed approach. [ABSTRACT FROM AUTHOR]