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In this paper, a systematic and analytical study of non-isolated topologies belonging to the family of reduced redundant power processing (R2P2) converters is presented. Based on this study, all the non-isolated R2P2 topologies that can be implemented in reality are derived. Detailed examples clarify all possible cases of this analysis. In addition to this, the voltage ratio and the efficiency for each one of the R2P2 configurations are calculated, being further illustrated with examples. A comparison among configurations is also discussed with criteria the high step-up voltage gain and efficiency, aiming for high-power applications. One of these R2P2 converters is selected for further examination, as the most suitable for such applications. The theoretical analysis, as well as the calculations of the step-up voltage ratio and efficiency of the selected converter, is compared to experimental results conducted on a 2-kW laboratory prototype designed to operate in various step-up voltage ratios and in a high-power range, proving the effectiveness of the proposed investigation. [ABSTRACT FROM AUTHOR]

The efficiency improvement of the on–off controlled Class E dc–dc converter operated at 20 MHz switching frequency is investigated in this paper. It is found that with the on–off control, the input power of the converter during the on mode increases with the increase of the input voltage, and it can be reduced by increasing the switching frequency. With this discovery, a variable switching frequency (VSF) on–off control is proposed, which slightly increases the switching frequency when the input voltage increases, maintaining the input power during the on mode slightly higher than the rated output power over the entire input voltage range, and thus highly improving the efficiency of Class E dc–dc converter at high input voltage. A prototype of 9-V–18-V input, 10-W Class E dc–dc converter has been fabricated and tested in the lab. The experimental results show that the proposed VSF on–off control improves the conversion efficiency of the Class E dc–dc converter by 4%–10% compared to the constant switching frequency on–off control. [ABSTRACT FROM AUTHOR]

In order to reduce switching loss of neutral point clamped three-level inverter (NPC TLI), generally discontinuous pulsewidth modulation (DPWM) is used. But it can result in dc offset and ac ripple on neutral point (NP) voltage. So a novel pulse sequence DPWM (NPSDPWM) is proposed to reduce switching loss and control NP voltage simultaneously in this paper. NP voltage is controlled by choosing proper clamping modes. To avoid unexpected switching action during changing clamping mode, an improved pulse sequence is also presented. The switching loss and NP voltage ripple of NPSDPWM, traditional and proposed DPWM in previous literature are compared, respectively. The experimental results show that NPSDPWM has well NP voltage control ability and the switching losses are reduced effectively. [ABSTRACT FROM AUTHOR]

Three-level inverter has an outstanding performance and is more advantageous in the switching vector selection than two-level inverter. In particular, the neutral-point voltage unbalance and common-mode voltage (CMV) reduction of three-level inverter should be carefully regulated for the appropriate operation, both of which, however, are mutually coupled resulting that the conventional space vector modulation (SVM) scheme cannot deal with them properly. To overcome this limitation, this paper proposes an improved space vector modulation (ISVM) technique to reduce the CMV and neutral-point voltage imbalance simultaneously. The generating mechanism of neutral-point voltage oscillation is derived. Based on the analysis, the proposed ISVM method adopts four voltage vectors (large, medium, small, and zero vectors) with adjusted dwell times to eliminate the ac unbalance of the neutral-point voltage. Considering the occurrence of neutral-point voltage disturbances, the dc neutral-point unbalance voltage is controlled by selecting the P-type or N-type small vector and adjusting the dwell times of small vectors for neutral-point voltage recovery. In addition, a novel switching sequence arrangement method with the minimal number of switches transition in one switching cycles and between switching cycles is proposed to reduce the total switching loss. Theoretical analysis and verification results show that the proposed ISVM scheme can reduce the magnitude of CMV to half of value using the conventional SVM, and an accurate control of ac and dc unbalanced neutral-point voltage can be obtained. [ABSTRACT FROM AUTHOR]

The degradation of submodule (SM) insulated gate bipolar transistors (IGBTs) in a modular multilevel converter (MMC) can be monitored through their on-state voltages. This paper proposes a scheme to calculate the IGBT on-state voltages at rated current and normal junction temperature. The equations of on-state resistances are established based on Kirchhoff voltage laws (KVL) in one MMC arm for positive and negative current directions separately. The arm current, arm voltage, capacitor voltages, gate signals, and junction temperatures are utilized in the equations, and most of the signals are known for the control system. The dimension of the equation set is reduced to make it solvable based on an assumption that all the on-state resistances of diodes remain equal. In addition, the Kalman filter (KF) is used to improve the stability and accuracy of the calculation results. The calculated results are converted to the normal condition based on the current-voltage (I–V) and resistance-temperature (R–T) characteristics of SM IGBTs and diodes. The scheme is verified by using the simulation of a five-level three-phase MMC model. The errors of the calculated VCE are within 0.3%, and the calculation accuracy is good enough for the estimation of IGBT degradation. Furthermore, the influences of the measurement accuracy and the equal diode voltage assumption on the calculation accuracy are analyzed. The proposed scheme is expected to be applicable in online condition monitoring of SM IGBTs. [ABSTRACT FROM AUTHOR]

In this paper, a novel discontinuous pulsewidth modulation (DPWM) modulation strategy for a neutral-point-clamped (NPC) three-level converter (TLC) is proposed to reduce the switching loss, reduce common-mode voltage (CMV), and remove dc offset from the neutral-point (NP) voltage simultaneously, which is named as RCMV_DPWM. Based on the space vector diagram with reduced CMV, all clamping modes under RCMV_DPWM are revealed. Then, the NP voltage is controlled by selecting proper clamping mode. The realization of RCMV_DPWM is also discussed. Moreover, the performances of RCMV_DPWM are analyzed and compared with other PWM strategies in term of the NP voltage ripple, switching loss, and waveform quality. Finally, the feasibility and superiority of RCMV_DPWM are verified by experiments. [ABSTRACT FROM AUTHOR]

A three-phase three-level (TPTL) converter is an optimal alternative for high-input and high-power dc/dc conversion system. The voltage stress on the primary switch is only half of the input voltage due to its three-level (TL) structure, and the current rating of power devices can be reduced by the three-phase configuration. To achieve soft switching and improve efficiency, the resonant tank can be introduced to optimize the performance of the converter. In this paper, a novel TPTL LC-type series resonant converter with few switches and simple configuration is proposed. The voltage stress on all switches can be reduced to the half of the input voltage, and the voltage across output rectifiers is clamped to the output voltage; as a result, the proposed converter is suitable for high-input/output applications. Meanwhile, the ripple frequency of the output current can be increased significantly, resulting in a reduced filter requirement. Variable frequency control strategy is adopted in order to obtain zero-voltage switching for all switches and zero-current switching for all rectifier diodes in wide input voltage and load range. In this paper, the comprehensive analysis on the proposed converter is carried out, including the operation mode classification, the operating mechanism under different operation mode, along with the circuit model, and gain characteristics of the converter by the fundamental harmonic analysis. Experimental results from a 440–590 V input and 400 V/5 A output are presented to verify the theoretical analysis and the performance of the converter. [ABSTRACT FROM AUTHOR]

This part of the paper illustrates the use of the expression derived in Part I for predicting subharmonic oscillation in switching regulators. Six case studies with different control schemes from the recent literature are used to validate the novel approach and the new derived expression, which is benchmarked for these case studies against results obtained using the discrete-time modeling approach or Floquet theory combined with Filippov method. Numerical simulations from the circuit-level switched models, implemented in PSIM software, are used to demonstrate the correctness of the derived closed-form condition. A procedure is presented to apply the approach of the paper to power converters with nonlinear sources, such as photovoltaic (PV) arrays or fuel cells. Experimental measurements from a boost converter prototype for PV applications are also provided to validate the theoretical predictions and the numerical simulations showing a remarkable agreement. [ABSTRACT FROM AUTHOR]

In high-voltage applications, the magnitude of total semiconductor losses (on-state and switching) determines the viability of modular-type multilevel converters. Therefore, this paper presents a new cell arrangement that aims to lower total semiconductor loss of the modular multilevel converter (MMC) to less than that of the half-bridge modular multilevel converter (HB-MMC). Additional attributes of the proposed cell are: it eliminates the protective thyristors used in conventional half-bridge cells that deviate part of the dc-fault current away from the antiparallel diode of the main switch when the converter is blocked during a dc short-circuit fault, and it can facilitate continued operation of the MMC during cell failures without the need for a mechanical bypass switch. Thus, the MMC that uses the proposed cell retains all advantages of the HB-MMC such as full modularity of the power circuit and internal fault management. The claimed attributes of the proposed cell are verified using illustrative simulations and reduced scale experimentations. Additionally, this paper provides brief and critical discussions that highlight the attributes and limitations of popular MMC control methods and different MMC cells structures proposed in the literature, considering the power electronic system perspective. [ABSTRACT FROM AUTHOR]

This paper extends the voltage-doubler concept to the single-phase SEPIC rectifier in discontinuous conduction mode and, as a consequence, novel rectifiers are proposed. A comparison with the classic SEPIC rectifier shows that the proposed converters can either provide reduced voltage stress on the semiconductors for the same output voltage level or supply double the gain of the output voltage with the same voltage stress. The proposed voltage-doubler SEPIC rectifiers provide a high power factor with no current control and they can be applied in order to improve the static gain of the structure, which can make the SEPIC rectifier suitable for applications that require a high voltage level. In this paper, the generic structure based on a three-state switch, four different implementations of the proposed concept (including bridgeless structures), steady-state analysis, a dynamic model, system control, and experimental results are presented. The proposed rectifiers were verified by experimental results obtained with a prototype built with the following specifications: 1000 W output power, 220 V input voltage, 400 V output voltage, and 50 kHz switching frequency. Peak efficiency of 95.84%, THD of 2%, and power factor of 0.9997 were obtained and, most importantly, double the gain of the output voltage was verified. [ABSTRACT FROM AUTHOR]

This paper presents the analysis and design of an isolated high-voltage LLC resonant dc–dc full-bridge converter based on symmetrical quadrupler rectifier (SQR). Unlike conventional Cockcroft–Walton and full-bridge diode rectifiers, the SQR circuit provides significant improvement in power density by reducing the transformer turns-ratio without much increase in the output impedance. Moreover, the LLC converter can provide additional voltage boost, if operated, below the series resonant frequency of the LLC tank. The operating region of the converter is chosen in such a way that the converter always operates in ZVS for all line and load conditions with additional voltage boost. A new method based on basic differential equation is proposed for the accurate analysis and design of the converter and subsequently, the key results are compared with a first harmonic approximation based analysis method. A 120 V dc input, 2 kV output, 200 W laboratory prototype has been designed, built, and tested. Simulation and experimental results shown in this paper demonstrate the validity of the analysis and design of the presented converter. [ABSTRACT FROM AUTHOR]

For the conventional PFC rectifiers, the high efficiency cannot be achieved over a wide input range, and the efficiency will be greatly decreased at low-input voltages. In order to overcome the efficiency bottleneck under low-line input, a flexible mode bridgeless boost power factor correction (PFC) rectifier is proposed in this paper. According to the input voltage, the proposed rectifier can be flexibly adapted to the suitable operating mode to obtain the maximum efficiency. Meanwhile, the circuit components can be reused by different operating modes, so the extra cost is low. In the proposed rectifier, a back-to-back bridgeless boost PFC topology is adopted at high-line conditions and a three-level bridgeless boost PFC topology is rebuilt to reduce the switching losses at low-line conditions. Compared with the traditional bridgeless boost PFC rectifier, an extra low-voltage bidirectional switch (usually composed of two switches) is added, so the increased cost is low. In addition, the low common-mode noise can be achieved at both high- and low-line conditions due to the direct connection between the input mains and the output electrolytic capacitor. The detailed principle analysis about the proposed rectifier is presented in this paper. Finally, an experimental prototype is built to verify the feasibility and the effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

The degradation in power quality causes adverse economical impact on the utilities and customers. Harmonics in current and voltage are one of the most commonly known power quality issues and are solved by the use of a hybrid series active power filter (HSAPF). In this paper, a new controller design using sliding-mode controller-2 is proposed to make the HSAPF more robust and stable. An accurate averaged model of a three-phase HSAPF is also derived in this paper. The design concept of the robust HSAPF has been verified through simulation and experimental studies, and the results obtained are discussed. [ABSTRACT FROM AUTHOR]

This paper presents a single-switch isolated dc–dc converter suited for a very high-frequency switching operation, especially above 10 MHz. The converter features a small number of passive components, low-switching loss, and low-voltage stress on the switch. In order to achieve low-voltage stress while maintaining zero voltage switching, the voltage waveform across the switch is shaped by designing the resonant network of the converter. The resonant network includes main parasitic components, such as leakage inductances of the transformer and the junction capacitance of the switch. Furthermore, some resonant elements are entirely replaced by these parasitic components under the specific condition. This paper derives the conditions and then minimizes the number of passive components. To validate the design procedure and the performance of the proposed converter, a GaN-based prototype was implemented. It operates at 10 MHz and provides the output power of 10 W from the dc input voltage of 50 V. The output voltage is regulated to 20 V by the ON–OFF control. Experimental results show that the peak voltage on the switch is reduced to 2.2–2.3 times the dc-input voltage and the efficiency of 69% is achieved under the full load. [ABSTRACT FROM AUTHOR]

This paper studies pulse width modulation (PWM) techniques suitable for a four-level five-phase open-end winding (OeW) drive. The drive comprises a five-phase induction machine, supplied using two two-level voltage source inverters with isolated and unequal dc-link voltages, in the ratio 2:1. A decoupled carrier-based (CB) PWM modulation strategy, based on unequal voltage reference sharing between the two converters, is introduced in this paper. The stability of dc-link voltages in OeW drives is investigated next, using a novel analysis technique. Several modulation methods are analyzed and the results show that application of the coupled PWM technique, with carriers having in-phase disposition, leads to overcharging of the capacitor in the dc-link of the inverter intended to operate with the lower dc-link voltage. On the other hand, the proposed decoupled CB PWM scheme naturally eliminates the dc-link capacitor overcharging problem. These findings are verified experimentally, using open-loop V/f control. Two different decoupled CB modulation methods are compared and the best performing modulation method is selected and incorporated further into an OeW drive with field-oriented control. The presented steady state and transient experimental results demonstrate that the decoupled CB PWM technique is suitable for high-performance variable speed drive applications. [ABSTRACT FROM AUTHOR]

This paper presents a novel family of single-switch resonant dc–dc converters with low switch voltage stress. The single-switch resonant converter which has a ground-referenced switch is advantageous for implementing the gate drive circuit and operating at several-MHz switching frequency. However, the conventional ones mostly have high voltage stress on the switch, roughly 4–5 times the input voltage. In this paper, we propose the single-switch converter topologies derived from the drain-source impedance networks consisting of two inductors and two capacitors. The switch voltage of the proposed converters is shaped into a near trapezoid by designing the resonant networks to have the desired drain-source impedance. Furthermore, a simple and specific design scheme is presented here so that the peak switch voltage is lowered to 2.2–2.5 times the input voltage while zero voltage switching is achieved. Experimental results from a 20-W GaN-based prototype operating at 10 MHz demonstrate the feasibility of the proposed converter topologies and the design method. [ABSTRACT FROM AUTHOR]

A family of bidirectional switched-capacitor (SC) converters with high-gain ratio of any positive integer is proposed in this paper for distributed energy resources applications. As compared with other existing SC converters achieving a same conversion gain, the main advantages of the proposed converters are that they require a relatively lower number of switches and capacitors, have a relatively lower switch's and capacitor's stress, and that their associated driver circuits are simpler to realize. Importantly, with the achievable conversion ratio being flexible and that the input and output of the proposed converters are of common ground, the proposed converters are widely suitable for many applications. Moreover, as the proposed converters do not possess magnetic component or any component that can severely degrade the converters’ performance at high temperature, they are especially useful for high-temperature applications. Besides, the proposed converters are capable of delivering bidirectional power, which is a key requirement for emerging applications with battery storages. Different aspects of the proposed converters, including a simple auxiliary power supply circuit for the MOSFETs’ drivers, will be discussed in this paper. A nine-time SC converter prototype that operates with 20-V input voltage, 100-W output, and at 75 kHz, is constructed and tested. Experiment results show that the maximum efficiency achievable with this prototype is over 98% (without driver's loss) and the efficiency over the entire load range between 25 and 100 W is over 95.5% including the driver's loss. The output voltage ripple of the SC converter is less than 1%. When the SC converter is open-loop controlled, the load voltage regulation is relatively well kept at less than 5% between full load and no load conditions. [ABSTRACT FROM PUBLISHER]

This paper presents a pulse width modulation (PWM) technique for the minimization of the leakage current in the grid-connected/stand-alone transformerless photovoltaic (PV)-cascaded multilevel inverter (CMLI). The proposed PWM technique is integrated with the MPPT algorithm and is applied to the five-level CMLI. Furthermore, using the proposed PWM technique the high-frequency voltage transitions in the terminal and common mode voltages are minimized. Thus, the proposed PWM technique minimizes the leakage current of the PV array and electromagnetic interference filter requirement in the system without addition of any extra switches. Furthermore, this paper also presents the analysis for the terminal voltage across the PV array and the common mode voltage of the inverter based on the switching function. Using the given analysis, the effect of the PWM technique can be analyzed, as it directly links the switching function with the common mode voltage and leakage current. Also, the proposed PWM technique requires reduced number of carrier waves compared to the conventional sinusoidal pulse width modulation technique for the given CMLI. Complete details of the working principle and analysis with the support of simulation and experimental results of the proposed PWM technique are presented in this paper. [ABSTRACT FROM PUBLISHER]

This paper proposes a dual-space vector control scheme for the open-end winding permanent magnet synchronous motor (OEW-PMSM) drive fed by the dual inverter with a single dc supply. Potential zero-sequence current in the open-end winding drive system has to be considered since it causes circulating current in the winding and leads to high current stress of power semiconductor devices and high losses. Zero-sequence current in open-end winding ac motor drives is usually caused by the zero-sequence voltage, and therefore switching combinations which do not produce zero-sequence voltage are used to synthesize the reference voltage in existing methods. But even so, the zero-sequence voltage can also be produced by the dead time of the inverter. In order to suppress zero-sequence current in the OEW-PMSM drive, a dual-space vector control scheme is proposed and a novel dual-inverter space vector pulse width modulation (PWM) with the zero-sequence voltage reference is employed to regulate system zero-sequence voltage in this paper. Compared with existing dual inverter PWM strategies, the novel algorithm build a regulation mechanism for the zero-sequence voltage. The proposed method is compared with the conventional vector control by simulations and experiments, and the results shown that the proposed scheme can suppress zero-sequence current effectively. [ABSTRACT FROM AUTHOR]

In this paper, the Z-source converter is introduced to power factor correction (PFC) applications. The concept is demonstrated through a wireless power transfer (WPT) system for electric vehicle battery charging, namely Z-source resonant converter (ZSRC). Due to the Z-source network (ZSN), the ZSRC inherently performs PFC and regulate the system output voltage simultaneously, without adding extra semiconductor devices and control circuitry to the conventional WPT system such as conventional PFC converters do. In other words, the ZSN can be categorized as a family of the single-stage PFC converters. In addition, the ZSN is suitable for high-power applications since it is immune to shoot-through states, which increases reliability and adds a boost feature to the system. The ZSRC-based WPT system operating principle is described and analyzed in this paper. Simulations and experimental results based on a 1-kW prototype with 20-cm air gap between the system primary and secondary sides are presented to validate the analysis and demonstrate the effectiveness of the ZSN in the PFC of the WPT system. [ABSTRACT FROM PUBLISHER]

Magnetically coupled impedance-source (MCIS) networks are recently introduced impedance networks intended for various high-boost applications. It employs coupled magnetic in the circuit to achieve higher voltage gain. Various MCIS networks have been proposed in the literature for myriad applications; however, due to effective role of system modeling in the closed-loop controller design, this paper is allocated to small-signal modeling and analysis of MCIS converters. The modeling is performed by means of the circuit averaging and averaged switch technique. A generalized small-signal derivation is demonstrated for pulse width modulation (PWM) MCIS converters and it is shown that the derived transfer functions can simply be applied to Y-source, Γ-source, and T-source impedance networks. Various transfer functions for capacitor voltage, output voltage, magnetizing current, input and output impedance are derived and have been validated through frequency and dynamic responses of computer simulation results. In addition, a comprehensive analysis has been done for all mentioned PWM MCIS converters regarding their circuit parameters. Furthermore, the effect of considering the equivalent series resistances of capacitor and inductor on the stability margin of MCIS converters is revealed in this paper. Finally, in order to validate the derived transfer functions and to consolidate the perfumed analysis, experimental results are presented for all mentioned MCIS converters. [ABSTRACT FROM PUBLISHER]

Based on the Z-source inverter, this paper proposes a novel commutation torque ripple reduction strategy for brushless DC motor (BLDCM). The proposed strategy employs the same modulation mode in both the normal conduction period and the commutation period, and the commutation torque ripple is reduced by regulating the shoot-through vector and active vector duty cycles. The proposed detection method acquires the end point of commutation by comparing the clamped terminal voltages with reference zero level, and the signal-noise-ratio of the detection is improved by avoiding the attenuation of the terminal voltages. Furthermore, a certain pulse width of the shoot-through vector can not only reduce the commutation torque ripple but also provide a new opportunity to detect the end point of commutation. Moreover, Z-source inverter provides the buck–boost ability for BLDCM drive system, then the dc voltage utilization can be improved, and the safety of the drive system can also be improved. In addition, this paper analyzes the terminal voltages during each vector. The experimental results verify the correctness of the theories and the effectiveness of the proposed approach. [ABSTRACT FROM PUBLISHER]

Various magnetically coupled impedance source (MCIS) networks have been proposed in the literature for increasing voltage gain and modulation index simultaneously while reducing the number of passive components used in the converter. However, applications of such networks have been limited by their discontinuous currents drawn from the sources and/or high stresses experienced by their components. This paper thus proposes three new MCIS networks named, respectively, as quasi-Y-source, quasi-Γ-Z-source, and quasi-T-source or quasi-trans-Z-source networks. These new networks inherit all advantages of the existing MCIS networks. In addition, they demonstrate advantages like continuous input currents, reduced source stresses, and lower component ratings that are not achievable by other existing networks. Further, dc-current-blocking capacitors used in the networks help to avoid saturation of magnetic core. Derivations of all two-winding MCIS networks, including existing and new networks, from the generalized three-winding MCIS networks are then systematically illustrated, before comparing them. Operational principles, mathematical derivations, simulation, and experimental results of all studied networks have been presented in the paper. [ABSTRACT FROM PUBLISHER]

Modular multilevel converters (MMCs) are being developed for the grid connection of offshore wind or tidal farms. In order to reduce the construction and maintenance costs, it is desirable to reduce the weight and volume of the system. In current MMC submodule designs, the reservoir capacitor usually accounts for over 50% of the total volume and 80% of weight. This paper presents a new design concept and control principle for a submodule using the stacked switched capacitor (SSC) architecture that can significantly reduce the capacitor size in an MMC. Practical considerations for a high-voltage high-power SSC-based MMC submodule are presented in this paper, through the design of a 21-level, 40-kV (pole-pole dc), 19.1-MW, grid-connected system, and the concept is demonstrated experimenttally on a scaled-down 400-V, 12.3-Apeak laboratory prototype submodule. It is shown that with the proposed SSC architecture, the total volume of capacitors in each submodule can be reduced by more than 40% without significantly increasing the power loss. [ABSTRACT FROM AUTHOR]

The low threshold voltage of Gallium Nitride enhancement mode FETs is a concern in synchronous dc–dc buck converters. This paper presents a converter using a gate drive with a negative biased gate voltage on the low-side FET to improve the dV/dt robustness. The resulting much larger voltage drop during the dead time conduction is a concern as it can quickly overcharge the bootstrap capacitor voltage. This paper demonstrates that with a negative biased gate voltage, the rise in the bootstrap capacitor voltage is predominantly caused by the change in effective dead time conduction due to a variation in output load. A spice model to estimate the change is presented and verified. This paper also found that a change in the bootstrap capacitor voltage must be prevented as it leads to a significant change in turn-on dynamics, resulting in higher dV/dt stress with an increase in output load. To prevent a change in bootstrap capacitor voltage, different techniques such as Zener diode clamping and an external free-wheeling Schottky diode are tested and discussed. Finally, a modification of a standard bootstrap circuit using a series inductor is proposed and tested. It has been found to be the most effective method in preventing a variation in the bootstrap capacitor voltage and should be included when using a negative gate drive in a GaN dc–dc buck converter. [ABSTRACT FROM AUTHOR]

The increasing interest in multiphase drive systems has led to the extension of inverter topologies and pulse width modulation (PWM) methods from three-phase to multiphase occasions. Carrier-based PWM (CPWM) dominates space vector PWM when the phase number increases, because of its simple computation and modular implementation. Although intensive work has been done on modifying PWM methods to reduce the common-mode voltage (CMV), not enough work has been done on CPWM methods with CMV reduction for multiphase drives. This paper extends the phase-shifted sinusoidal PWM (PS-SPWM) method for five-phase and six-phase two-level voltage-source inverters (VSI) and employs the intersection-plotting method and Fourier analysis to reveal the nature of the CMV. Both experiment and simulation results comply with theoretical analysis that compared with the conventional SPWM, the PS-SPWM can effectively reduce the CMV in peak-to-peak value and RMS value, though it leads to a higher phase current distortion. In addition, the hardware realization of PS-SPWM for multiphase inverters by a distributed control system is presented in this paper. [ABSTRACT FROM AUTHOR]

This paper identifies extra junction capacitances and switching commutation loops introduced by line-frequency devices (i.e., non-active every other half line cycle) in three-level ac/dc converters and investigates the corresponding effects. Junction capacitances and power loops are well known as the key factors that impact converter switching loss and device stress, thus influence device selection, power stage layout, and thermal design. By examining switching transients of the commonly used T-shaped and I-shaped three-level converters, the cause and mechanism of the extra junction capacitances and power loops are presented. The impacts on switching loss, device voltage stress, and ac-side voltage/current distortion are respectively reported and analyzed. A loss calculation scheme for the three-level converter to include that extra loss is proposed. A power layout scheme to mitigate the device voltage stress is provided. Compensation and modeling of the voltage and current distortion are also proposed. Experimental results conducted on several types of three-level converter prototypes including a gallium nitride based 115 $V_{{\text{ac}}}{\text{/650}}$ Vdc/1.5-kW/450-kHz Vienna-type rectifier and a SiC mosfet based 1-kV/10-kW/280-kHz three-level active neutral-point-clamped inverter confirm the presented effects and verify the associated analysis and solutions. [ABSTRACT FROM AUTHOR]

This paper proposes a novel modular equalization architecture for series-connected electric double-layer capacitor (EDLC) modules, each consisting of multiple cells connected in series. Cell voltages in a module are equalized by an inductive voltage divider (IVD)-voltage multiplier (VM)-based cell equalizer, while module voltages are unified by switched capacitor converters (SCCs). Square wave voltages generated at switching nodes of the IVD-VM-based cell equalizers are utilized to drive the SCC-based module equalizers, realizing the switchless topology of SCC-based module equalizers. The required switch count of the proposed system can be halved compared to conventional systems, allowing simplified circuit. An experimental equalization test for three EDLC modules, each consisting of six cells in series, was performed from an initially voltage-imbalanced condition. Module and cell voltages were equalized at different rates, and the equalization performance of the proposed modular equalization system was successfully demonstrated. [ABSTRACT FROM AUTHOR]

The strive to increase the energy yield of photovoltaic (PV) power systems has made PV module integrated dc–dc converters (dc-MICs) a reality of modern PV plants. These converters regulate their input voltage, and their dynamic behavior is heavily influenced by the non-linear characteristic of the PV module. The regulation of the PV module voltage and average inductor current by means of a linear cascaded controller is a popular control technique, simplifying the converter dynamics, and providing inherent current limiting; however, it is prone to instability depending on the interaction between the PV source and the interfacing converter, as well as the value of the controller parameters. These factors present a clear challenge for control design; moreover, the converter transient response undesirably depends on the PV module operating point. In order to solve these issues, while maintaining regulation of PV module voltage and average inductor current, this paper proposes to adopt a non-linear controller designed with the feedback linearization control (FLC) technique. The control laws are derived and implemented in a non-inverting buck–boost dc module integrated converter, as this is a favorite topology for the PV interfacing application. A digitally controlled converter prototype is built and used to obtain experimental results, where the FLC technique is compared with a linear cascaded control technique. The results confirm the superior performance of the presented FLC technique, which is robust and able to regulate the converter input voltage with fast and consistent dynamics, regardless of the PV module or load operating conditions. [ABSTRACT FROM AUTHOR]

SiC mosfets allow a higher frequency, lighter weight inverter over their Si counterparts for electric vehicle (EV) applications. However, using SiC-based EV traction inverters is likely to increase the shaft voltage in an ac motor drive system, which significantly affects the reliability of the system. This paper investigates the impact of high-speed switching of SiC devices and high switching frequency of SiC-based inverter on the common-mode voltage (CMV) and the shaft voltage. It is theoretically illustrated and experimentally demonstrated that the high switching frequency increases the amplitude of the shaft voltage, while the fast switching speed has limited influence on both CMV and the shaft voltage. Afterward, active zero state pulsewidth modulation (AZSPWM) and common-mode chokes are employed to mitigate the shaft voltage. The experimental results show that either the AZSPWM modulation scheme or common-mode chokes have the capability to minimize the shaft voltage. Better performance can be achieved by utilizing both techniques simultaneously. It is also observed that the high switching frequency enabled by the fast-speed SiC device is able to be helpful to the use of reduced shaft voltage technologies. [ABSTRACT FROM AUTHOR]

Many research works have been conducted on increasing the efficiency of interleaved boost converters (IBCs) applied for power factor correction (PFC) by using high-performance power electronic devices and soft switching circuits, which are not helpful in reducing the hardware cost and systematic complexity. In this paper, three intrinsic parameters affecting the efficiency of IBC PFC are found and analyzed, including the switching frequency value, boost inductor value, and output voltage value. Based on the findings, considering the limitations of current ripples, power factor, maximum magnetic flux density, and volume of a boost inductor, an optimization design method for high-efficiency IBC PFC is proposed. A 3.3-kW IBC PFC prototype is developed based on Si devices. The experimental result verifies that the proposed method can improve the efficiency of IBC PFC with low-cost low-performance devices in the full-load range. [ABSTRACT FROM AUTHOR]

This paper presents an improved H8 power converter for common-mode voltage (CMV) reduction and electromagnetic interference suppression. The proposed H8 converter can realize zero CMV variation when entering and leaving the zero state, which is mainly achieved by both the improvement of the structure and the control strategy. For the system structure, two switches are added on the dc bus to float the ac part of the three-phase converter in the zero state. Besides, additional capacitors are used to realize controllable CMV. For the control strategy, a simple control strategy is proposed for the H8 converter. It can automatically adapt to the flowing orientation of the load current to realize synchronous switching of the power switches, which effectively eliminates the impact of the dead time. Through analysis, simulations, and experiment, a comparison between the proposed H8 converter and the conventional H6 converter is performed. Results validate the effectiveness of the H8 topology. [ABSTRACT FROM AUTHOR]

Due to the zero-sequence currents in the four-wire systems, the three-phase currents become more complex on both amplitudes and phases in the unbalanced load conditions, so that the existing open-circuit (OC) fault diagnosis methods of the switching devices cannot be directly used. In this paper, an OC fault diagnosis strategy applied to four-wire T-type converter systems is proposed, which is implemented by decomposing the circuit model into a positive- and negative-sequence model and a zero-sequence model, and locating the OC fault based on the law of positive- and negative-sequence voltage error offsets and zero-sequence voltage error offsets. The proposed diagnosis method is suitable for both unbalanced load and unbalanced input voltage conditions. Meanwhile, the differences of fault-tolerant control between four-wire and three-wire systems are analyzed and compared. An effective fault tolerance strategy for inner OC faults applied to four-wire T-type converter systems is presented, which owns the ability to suppress dc bus imbalance. Simulation and experimental results are presented to verify the correctness of the proposed strategy. [ABSTRACT FROM AUTHOR]

Several applications need a high power, high output voltage ac/dc converter. The structure includes a dc/dc resonant stage, which is fed from a three-phase line. Due to standards, rectified dc input voltage varies largely from 400 to 750 V affecting the adversely overall design and current levels. In fact, losses in the inverter become unbearable if both switching frequency and transferred power are desired beyond a certain level. In those cases, it is necessary to connect several switches in parallel. As an alternative, the new switches can configure a new modular structure instead, adding more flexibility in the control to compensate input voltage variations. As a result, the required circulating current is reduced to a half, with benefits in total power losses. Moreover, the nature of the topology allows a reconfiguration of the resonant net (LCC) for low power, reducing even further the minimum circulating current under those conditions (fluoroscopy, for instance). In this paper, the new multilevel resonant topology is mathematically modeled and proposed for radiography and fluoroscopy. An example illustrates the design procedure for a given application at 100 kW, 50–150 kV. [ABSTRACT FROM AUTHOR]

Impedance-source inverters using coupled inductors have been investigated as alternatives for providing high step-up voltages. However, leakage inductances of the coupled inductors have commonly led to lower overall effectiveness, in addition to generating high dc-link voltage spikes. The latter raises voltage stresses of switches, which in turn, may reduce the power levels of the inverters. A high step-up Y-source inverter has therefore been proposed in this paper to provide a high boost with a smooth dc-link voltage ensured by proper recycling of the leakage energy. These features have been verified by comparing simulation and experimental results of an existing Y-source and the proposed inverters. Factors compared are their respective boost ratios, voltage stresses, current stresses, and dc-link voltage spikes. [ABSTRACT FROM AUTHOR]

In this paper, a developed structure is proposed for high step-up nonisolated noncoupled inductor based multiport dc–dc converters. The voltage gain per number of devices of the proposed topology is higher than that of similar topologies. This means that, by using the same number of devices, the proposed topology can generate higher gains than other structures. In other words, the proposed topology utilizes less number of devices for producing the same voltage gain, which leads to less total cost, size, weight, and complexity. Despite high voltage gain, the normalized peak inverse voltage (NPIV) on switches/diodes is low. Higher number of input ports leads to higher gains and lower NPIVs on devices. The load energy can be absorbed and stored in first input unit. Modularity, simple structure, continuous input currents, and low input current ripple are the other profits of proposed topology. Low/medium power applications are suggested for the proposed structure. Proposed topology has been explained and operational modes along with steady-state analysis have been discussed. For better verification, the proposed topology has been compared with several multiport high gain converters. Comparison results confirm the advantages of the proposed topology. Finally, the proper performance of the proposed topology has been validated by experimental results. [ABSTRACT FROM AUTHOR]

A decentralized control method for power module (PM) capacitor voltage and switching frequency balancing in modular multilevel converter is presented in this paper. The proposed method is composed of a central controller, six arm controllers, and several group controllers. The group controller is only in charge of the PM capacitor voltage balancing within a corresponding group, and the arm controller is in charge of the PM capacitor voltage balancing and PM switching frequency balancing among groups within an arm. A control method based on a PI controller using the average PM capacitor voltage of each group to keep voltage balancing among groups is proposed. A dynamically adjusted extra exchange number strategy based on the voltage difference of each group is also developed to balance the PM switching frequency among groups. The key advantages of the proposed method are the reduction in the number of the PM capacitor voltages that need to be transmitted and sorted in each group controller as well as the reduction of the communication burden between the group and arm controllers. The proposed method is also highly effective under PM faults. The voltage ripple factor and the PM switching frequency of the proposed method are almost identical to the conventional centralized methods. The RT-LAB-based real-time control hardware in the loop test results of a ±350 kV/1000 MW MMC system verify the correctness and effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC) is attractive for medium- or high-power applications because of the advantages of its high modularity, availability, and high power quality. Reliability is one of the most important challenges for the MMC consisting of a large number of submodules (SMs). The capacitor monitoring is one of the important issues in the MMC. This paper proposed a reference submodule (RSM)-based capacitor monitoring strategy for the capacitance estimation in the MMC, where the capacitances in the monitoring SMs can be estimated based on the capacitor voltage relationship between the RSM and the monitoring SMs. The proposed monitoring strategy does not rely on the information of all capacitor voltage and current, which effectively simplifies the algorithm for capacitance estimation. The simulation studies with the time-domain professional tool PSCAD/EMTDC are conducted and a down-scale MMC prototype is also tested in the laboratory with the proposed capacitor monitoring strategy. The study results confirm the effectiveness of the proposed capacitor monitoring strategy. [ABSTRACT FROM AUTHOR]

The ultra-high voltage gain dc–dc converters are extremely required because of the low voltage level of many nonpolluting power resources. This paper proposes an ultra-high voltage gain converter based on an interleave technique and using three-winding coupled inductor and voltage multiplier cell. The interleave technique is useful for reducing the size of the filter components. In the proposed converter, high voltage gain is achieved without extreme duty cycle of solid-state switches. The voltage stress across the semiconductor devices can be reduced by increasing the turn ratio of the secondary of the coupled inductors. In addition, because of the implementation of the interleave structure, peak-to-peak variation of the main input current and switching losses are substantially reduced. The steady-state principles of the proposed converter in continuous conduction mode operation are given. Also, design equations are presented. Validity and performance of the proposed converter are surveyed by simulation and experimental results of a 120 W prototype. [ABSTRACT FROM AUTHOR]

A simple buck–boost LED driver suitable for battery operated applications with limited input voltage level is presented in this paper. Soft switching performance is provided for the main switch via a resonant circuit to improve the converter efficiency. The incorporated auxiliary switch also performs under zero voltage switching condition. Both power switches can be driven with a simple gate drive circuit, so, the additional switch does not add any driving complexity. In addition, only one magnetic element is utilized in the proposed LED driver which contributes to circuit simplicity and lower weight and size. Also, all diodes turn off at zero current switching which eliminates the reverse recovery losses and improves efficiency. A laboratory prototype converting 12 V input voltage to 32 V output operating at 26 W output power is implemented and tested to verify the effectiveness of the proposed LED driver. [ABSTRACT FROM AUTHOR]

A 1-φ hybrid nine-level inverter (H9LI) topology has been proposed in this paper. The proposed H9LI topology uses a simple phase disposition pulsewidth modulation strategy to generate nine-voltage levels in the output. The main advantage of this topology is that it has a low switch count (ten switches) compared to the existing nine-level inverter topologies. To regulate the voltage across auxiliary capacitor, two innovative control techniques are proposed, which are integrated with the inverter modulation technique itself. Hence, it does not require any extra voltage balancing circuits to maintain the voltage across the auxiliary capacitor and input dc capacitors. A major advantage of these control techniques is that they eliminate the sensing of the coupled inductor current. Another significant advantage of H9LI is that loss distribution among all the power switches is more uniform compared to existing nine-level inverters. Due to low part count and absence of extra voltage balancing circuits, the H9LI achieves higher efficiency (η ≍ 94.5%) and lower cost. Furthermore, the requirement of filter size reduces due to the presence of coupled inductor in H9LI. The proposed 1-φ grid connected H9LI is verified through MATLAB/Simulink simulations and validated through experiments on a laboratory prototype of 400-VA rating. [ABSTRACT FROM AUTHOR]

In this paper, a novel space-vector pulsewidth modulation technique for a five-level active neutral-point clamped (5L-ANPC) inverter is proposed to eliminate the common-mode voltage (CMV). For the 5L-ANPC inverter, which produces a good output voltage performance and lowdv/dt, the total 125 voltage vectors can be generated, among which the proposed scheme employs only 19 voltage vectors producing a zero CMV. Due to the limitation of voltage vectors selected, the dc-link capacitor voltages of the 5L-ANPC inverter cannot be balanced by themselves. Therefore, the capacitor voltages of the inverter should be controlled by choosing the redundant switching states appropriately. The validity of the proposed modulation scheme has been verified by simulation and experimental results. [ABSTRACT FROM AUTHOR]

High step-down voltage conversion is necessary to bridge the voltage gap between main power converters and low-voltage auxiliary electronics in power conversion systems. Switched capacitor converters (SCCs) are an attractive candidate as a high step-down converter, but their poor voltage regulation capability may limit their applications. Pulsewidth modulation (PWM) SCCs with adjustable high step-down voltage conversion are proposed in this paper. The proposed PWM SCCs can be derived from traditional SCCs by replacing an energy transfer capacitor with a switched-capacitor-inductor (SCL) cell that comprises inductors, capacitors, and diodes to realize PWM-controllable voltage conversion. The voltage step-down ratio of the proposed PWM SCCs is not only PWM controllable but also adjustable with structures of SCCs and SCL cells. Two representative PWM SCCs were taken as examples to perform the operational analysis. The prototypes of both representative PWM SCCs were built and tested to demonstrate the proposed concept. [ABSTRACT FROM AUTHOR]

Common-mode voltage (CMV) is known as a major cause of premature motor failures. The form and amplitude of the CMV generated by any converter depends on both the circuit topology and modulation technique. Among single stage ac–ac converters employed in drive applications, the Z-source ultra sparse matrix converter (ZSUSMC) is a desirable choice due to reduced number of switches in its structure and voltage boosting capability. Based on these considerations, this paper aims to: 1) theoretically determine and compare the CMV of the ZSUSMC with four well-known impedance networks, namely, cascaded, switched-inductor, quasi, and series, in its structure and 2) propose modulation techniques for CMV reduction in the ZSUSMCs. To this end, first, it is shown that the ZSUSMC, depending on the impedance network used in its structure, provides more freedom to choose from redundant switching states compared to the ultra sparse matrix converter. Then, by taking advantage of this feature, novel modulation strategies that attenuate the CMV without affecting the boosting capability are developed. The proposed modulation schemes are based on avoiding the switching states most contributing to the CMV during a switching period. Through hardware-in-the-loop studies, the effectiveness of the proposed modulation strategies in reducing the CMV of the ZSUSMCs is verified. [ABSTRACT FROM AUTHOR]

In voltage-source inverters (VSIs), dead time is used to prevent shoot-through over switching devices. However, the existence of the dead time will distort the output phase current, which degrades the performance of the inverter as well as influences the common-mode voltage (CMV), particularly in CMV elimination relevant modulation schemes, such as zero-common-mode (CM) pulsewidth modulation (PWM)-based paralleled inverters. In the light of the situation that the normal sampling-based dead-time compensation (DTC) methods are often disturbed by the current ripple, this paper introduces a novel DTC method for the VSI, which can mitigate the impact of the current ripple and improve the accuracy of DTC. The proposed method deduces the real-time current ripple, which can reconstruct the actual trajectory of phase-leg currents, and the peak values corresponding to rising and falling edges for PWM signals can be predicted. In this way, DTC can be implemented based on the direction of relevant instantaneous switching currents and finally improves the accuracy. Especially, the current-ripple-prediction-based DTC can help to improve the CMV distortion caused by the dead time for paralleled inverters with zero-CM PWM. Simulation and experimental results are provided to validate that the proposed method can be applied to different topologies and modulation schemes with good performance. [ABSTRACT FROM AUTHOR]

This paper proposes a Class-DEMtuned power amplifier. The proposed amplifier achieves zero-voltage switching (ZVS), zero-voltage derivative switching (ZVDS), and zero-current switching (ZCS) at turning-on, and ZVS, ZVDS, ZCS, and zero-current derivative switching at turning-off. Therefore, the switching losses are extremely low, which is suitable for high-frequency operation. Moreover, the switch voltage stress is low, which is no more than its input voltage. A proposed amplifier was designed, built, and tested. The measured power conversion efficiency was 93.2% under the condition of the main input voltage of 46.8 V, the operating frequency of 1 MHz, and the output power of 4.87 W. [ABSTRACT FROM AUTHOR]

The power conditioning interface circuit plays a crucial role in the energy harvesting (EH) capability enhancement in piezoelectric EH (PEH) systems. The principle of most existing synchronized switch circuits for PEH enhancement was summarized under the recently introduced synchronized multiple bias-flip (SMBF) model. The optimal bias-flip strategy derived from SMBF provides valuable insights for future circuit development. Based on such theoretical foundation, this paper implements a new interface circuit called theparallel synchronized triple bias-flip(P-S3BF) for further boosting the harvesting capability beyond the state-of-the-art solutions. By sophisticatedly allocating more bias-flip actions, it makes the best compromise between higher extracted power and lower dissipated power for power conditioning, toward maximum net harvested power. Moreover, the bias voltage reference in P-S3BF is self-contained and self-adaptive. Compared to the other existing solutions involving active voltage manipulations, these two conveniences brought in by P-S3BF are the most significant and necessary features, which facilitate the practical stand-alone implementation of P-S3BF under different periodic vibrations. Experimental result shows that, with the piezoelectric cantilever in use, which vibrates at a constant deflection magnitude, the P-S3BF circuit harvests 24.5% more power than its single bias-flip counterpart, the extensively studied parallel synchronized switch harvesting on inductor; and 287.6% more power than its null bias-flip counterpart, the standard EH bridge rectifier. [ABSTRACT FROM AUTHOR]

Owing to the operational characteristic of a Vienna rectifier, it is found that the traditional modulation method would result in the current distortion. This paper, therefore, proposes a novel zero-sequence component injection modulation method for improving the input quality of the Vienna rectifier with balanced or unbalanced dc-link voltages. In specific, the degree of unbalanced dc-link voltages increases the size of abnormal regions in a slant and asymmetrical space vector diagram, which leads to more serious current distortion. The proposed method identifies the abnormal intervals by average duties accurately without detecting the position of the reference vector. Considering the operational characteristics, three-phase compensation components are calculated respectively depending on an unbalanced factor and added to three-phase average duties in abnormal intervals. As a result, the current harmonics of the Vienna rectifier are mitigated significantly with balanced or unbalanced dc-link voltages. The effectiveness and the performance of the proposed zero-sequence component injection method for the Vienna rectifier are verified by simulation and experiments. [ABSTRACT FROM AUTHOR]

The three-phase four-wire inverter with split dc-link capacitors can supply unbalanced loads. For the purpose of reducing the filter inductors, a neutral inductor could be introduced into the neutral line. This paper analyzes the operation principle of the three-phase four-wire inverter with split dc-link capacitors when a neutral inductor is introduced. It is illustrated that the neutral inductor can reduce the zero-sequence switching harmonics in the voltages between the phase-leg midpoints and the output neutral point, thus the filter inductors can be reduced. The optimized design of the neutral inductor and filter inductors is proposed with the considerations of the inductor current ripple, the ability of supplying unbalanced loads, and the total energy stored in the inductors. The equivalent circuits of the three-phase four-wire inverter with split dc-link capacitors and neutral inductor is derived in the α–β–0 frame, and the zero-axis voltage regulator is modified to suppress the third-order harmonic in the zero-sequence current caused by the deadtime of the drive signals for the power switches. Finally, the experimental results from a 9-kW prototype are provided to prove the effectiveness of the proposed optimized design of the neutral inductor and filter inductors and the control strategy of the inverter. [ABSTRACT FROM AUTHOR]

In this paper, a family of step-up resonant switched-capacitor converters (RSCs) with a continuously adjustable conversion ratio is proposed based on the Cuk dual-resonance core (DRC) featuring two resonant paths. By adopting the on-time fixed frequency modulation, the two resonant paths can conduct simultaneously and satisfy the charge balance of the flying capacitor during the overlapping period. As a result, the conversion ratio—upper bounded by two determined by the circuit configuration—can vary continuously and efficiently even at the light load condition (1/10 of the rated power). A comprehensive analysis—the operation principle, voltage-gain curve, and voltage/current stresses—about the DRC is given. In addition, the Cuk DRC was extended to the series–parallel switched-capacitor converter (SCC), Fibonacci SCC, and voltage doubler to form a family of step-up RSCs, whose voltage-gain curves of different topologies are derived. Moreover, a characteristic comparison between the Cuk DRC and the traditional “direct” and “indirect” resonant core is given. Then, a 48 to 62–94.6 V resonant core with peak efficiency 97.8% and maximum power 120 W under the open loop condition was built. The analyses were verified by both experimental and simulation results. [ABSTRACT FROM AUTHOR]