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In the applications for high-power dc/dc conversion, the power devices usually suffer high voltage and current stress in traditional single-phase dc/dc topologies such as forward, half-bridge, and full-bridge converters, which limits the power level of converter to reach higher. As a superior alternative solution, a three-phase three-level (TPTL) dc/dc converter was investigated in this paper, which has the advantages of lower voltage and current stress on switches, as well as fewer power devices. Adopting a symmetrical control strategy, the input current and output current frequency can be increased by a factor of six compared to the switching frequency, resulting in a reduced filter requirement. However, all the switches are hard-switching, leading to a considerable switching loss. In this paper, an asymmetrical duty cycle control strategy was proposed to the TPTL dc/dc converter. The modified converter remains all the advantages of original control strategy; meanwhile, soft-switching can be achieved using the energy stored in output filter inductance and leakage inductances of transformers (or resonant inductances). The theoretical analysis was presented in details, along with the characteristics and soft-switching condition of the converter. Experimental results from 540 to 600 V input and 48 V/20 A output were presented to verify the theoretical analysis and the performance of the modified converter. [ABSTRACT FROM AUTHOR]

Leakage current minimization is one of the most important considerations in transformerless photovoltaic (PV) inverters. In the past, various transformerless PV inverter topologies have been introduced, with leakage current minimized by the means of galvanic isolation and common-mode voltage (CMV) clamping. The galvanic isolation can be achieved via dc-decoupling or ac-decoupling, for isolation on the dc- or ac-side of the inverter, respectively. It has been shown that the latter provides lower losses due to the reduced switch count in conduction path. Nevertheless, leakage current cannot be simply eliminated by galvanic isolation and modulation techniques, due to the presence of switches' junction capacitances and resonant circuit effects. Hence, CMV clamping is used in some topologies to completely eliminate the leakage current. In this paper, several recently proposed transformerless PV inverters with different galvanic isolation methods and CMV clamping technique are analyzed and compared. A simple modified H-bridge zero-voltage state rectifier is also proposed, to combine the benefits of the low-loss ac-decoupling method and the complete leakage current elimination of the CMV clamping method. The performances of different topologies, in terms of CMV, leakage current, total harmonic distortion, losses and efficiencies are compared. The analyses are done theoretically and via simulation studies, and further validated with experimental results. This paper is helpful for the researchers to choose the appropriate topology for transformerless PV applications and to provide the design principles in terms of common-mode behavior and efficiency. [ABSTRACT FROM AUTHOR]

This paper presents a generalized multilevel direct power control (ML-DPC) scheme for grid-connected multilevel power converters. The proposed method extends the original DPC operating principle by considering only the closest subset of two-level voltage vectors to the present switching state. The implementation of this principle requires the power derivatives for feedback, which can present numerical problems when applied experimentally, mainly due to high measurement noise sensitivity. Therefore, a derivative estimator is proposed based on the converter-grid model in the synchronous reference frame. In addition, a virtual flux observer is developed to achieve synchronization and improve robustness in the presence of grid voltage harmonics. The proposed method is applicable to any multilevel converter topology of any number of levels. In this paper, simulations and experimental results are presented for a seven-level cascaded H-bridge converter. [ABSTRACT FROM AUTHOR]

This paper presents a fast and generalized space vector pulse width modulation (SVPWM) scheme for any multilevel inverter. The SVPWM scheme generates all the available switching states and switching sequences based on two simple and general mappings, and calculates the duty cycles simply as if for a two-level SVPWM, thus independent of the level number of the inverter. Because the switching states, duty cycles, and switching sequences are all obtained by simple calculation in the proposed SVPWM scheme, no lookup table is needed and the scheme is computationally fast. The generalized method of generating the switching states (first mapping), calculating the duty cycles, and determining the switching sequence (second mapping) is described in this paper. The scheme is suitable for any reference vector with any modulation index, and can be conveniently extended to meet specific requirements, such as symmetric switching sequences. Compared with prior methods, the SVPWM scheme proposed in this paper provides two more degrees of freedom, i.e., the adjustable switching sequences and duty cycles, thus offering significant flexibility for optimizing the performance of multilevel inverters. The influence of redundant switching sequences in the output phase voltage of inverters is demonstrated for a nine-level inverter. This paper also thoroughly compares the proposed SVPWM scheme with prior methods. Both simulation and experimental results are given. [ABSTRACT FROM AUTHOR]

This paper presents an analysis of the Class-E ZVS rectifier using a common-grounded multistep controlled Shunt Capacitor (CSC). The Class-E ZVS rectifier using a common-grounded multistep CSC can regulate the output voltage by changing the shunt capacitance. The voltage over the diode and shunt capacitor in the conventional Class-E ZVS rectifier is shared by the series connected capacitors. In this paper, the Class-E ZVS rectifier using a common-grounded multistep CSC is analyzed, simulated, and experimented. Especially, the power conversion efficiency is discussed in detail. [ABSTRACT FROM AUTHOR]

In this paper, analytical expressions for waveforms and design relationships are derived for the class-E power amplifier with the MOSFET nonlinear drain-to-source parasitic capacitance under the subnominal operation, i.e., only zero-voltage switching (ZVS) condition, for any grading coefficient m of the MOSFET body junction diode and 50% duty ratio. Only the MOSFET nonlinear drain-to-source parasitic capacitance is used for the analysis of the class-E ZVS power amplifier, and its nonlinearity is determined by the grading coefficient m. The switch voltage waveform does not satisfy the class-E ZVS switching condition when only the linear shunt capacitance is considered. The grading coefficient m is used as an adjustment parameter that provides accurate design to satisfy the given output power and peak switch voltage simultaneously. Therefore, the grading coefficient m is the important parameter to satisfy the class-E ZVS condition and given design specifications, which is the most important result in this paper. Additionally, the output power capability and maximum operating frequency are affected by the grading coefficient m. The analytical expressions are obtained by considering the grading coefficient m as an adjustment parameter, which is validated by PSpice simulations and laboratory experiments. The measurement and PSpice simulation results agreed with the analytical expressions quantitatively, which denotes the usefulness and effectiveness of our obtained analytical expressions. [ABSTRACT FROM AUTHOR]

Insertion of dead time, transfer links between micro control unit (MCU) and voltage source inverter (VSI), VSI's nonideal characteristics all lead to deviation that cannot be ignored between the actual output voltage and the command voltage, which seriously affects the performance of the ac induction motor (ACIM) control system. Among many dead-time effect compensation methods, VSI usually operates under an open-loop condition, thus making complete compensation hard to achieve. This paper studies methods to obtain the two key elements of compensation voltage amplitude and current polarity and a novel phase voltage compensation method is proposed. In this method, a simple hardware circuit is applied to obtain the actual output of the VSI as feedback with which precise compensation amplitude can be calculated. And judgment of current polarity is accurately realized by reconstructing phase current from filtered current components under M-T coordinate with a Kalman filter. The compensation in a zero-crossing region is also closely discussed in this paper. To verify the validity of the method, simulations and experiments are carried out. The experiments emphasize on the efficacy of feedback, steady-state, and transient performance of current reconstruction; and the performance of a conventional method to that of the proposed method are also compared. Results show that the proposed method proves to be effective. [ABSTRACT FROM AUTHOR]

Switch fault diagnosis is an important design aspect for pulse width modulation (PWM) dc-dc power converters. It can prevent power converters from further damage, and also make preparations for remedial actions. In this paper, a fast switch fault diagnostic method is proposed for PWM dc-dc converters operating in continuous conduction mode. The proposed method utilizes the magnetic component (inductor or transformer) voltage for fault diagnosis. Based on the real-time voltage measurement and switch gate-driver signals, characteristics of switch open-circuit faults and short-circuit faults are rapidly extracted, and thus, switch faults can be quickly detected. The magnetic component voltage can be measured by an auxiliary winding in the magnetic core, and gate-driver signals can be easily got from the control circuit. Moreover, the fault detection can be implemented by a low-cost logical hardware circuit, and this circuit can be integrated into the control circuit. The fault diagnosis principle, design considerations, and implementation are discussed in this paper. Experiments are conducted to verify the theoretical analysis. [ABSTRACT FROM AUTHOR]

Generally, single-stage buck–boost inverters consist of distinct circuits operating individually in buck/boost or positive/negative modes, the latter definitely leading to crossover distortion in the output current. This paper proposes a switching strategy that changes the bimodal operation of a single-stage buck–boost topology to a single-mode inverter. This is due to the consequent voltage gain that ensures that the output voltage polarity, apart from its magnitude, is an exclusive function of the duty ratio. Operational principle and salient hardware design are explained with the help of equivalent circuits. Details about the dynamic model are presented, based on which controller design is carried out for both stand-alone and grid-connected operation. Experimental results obtained from a 300-W, 110-V laboratory prototype are presented to validate the performance of the proposed switching strategy. [ABSTRACT FROM PUBLISHER]

The flying-capacitor modular multilevel converter (FC-MMC) overcomes the low/zero-speed operation issues of conventional MMC-based drive. The FC-MMC injects no common-mode voltage (CMV) to the drive system. However, the pulse width modulator (PWM) introduces switching ripples, which appear as CMV on motor stator windings. To completely get rid of the CMV, an elimination method based on a new modulation scheme is proposed in this paper. The modulation algorithm places the switching pulses end to end for upper and lower arms, respectively. The consistent switching positions between upper and lower arms lead to the complete CMV elimination for FC-MMC-based drive system in entire speed range. Although the proposed method slightly increases the switching frequency as compared to conventional phase-shifted PWM, it is still acceptable in medium-voltage applications. The validation of the proposal is proved by simulations and experiments. [ABSTRACT FROM PUBLISHER]

The noninverting buck–boost converter has attracted significant attention in the photovoltaic (PV) module integrated application, as it offers high efficiency while maintaining a low cost and a simple topology. When this converter is employed, special care must be taken at the transition between buck and boost operating modes, as a dead-zone in the voltage transfer function can cause abrupt perturbations in the controlled voltage, decreasing the regulation quality and ultimately lowering the power conversion efficiency. In this paper, a new dead-zone compensation technique is proposed with the scope of smoothing the transition between operating modes, eliminating the voltage ripple and improving the regulation performance, while maintaining high efficiency. The converter under analysis is studied together with its gate driving circuit, which is based on a bootstrap capacitor power supply for the high-side switches. The proposed dead-zone compensation technique is deduced by using the principle of maintaining the ideal voltage gain function across the converter operating range. The technique is analyzed, implemented and tested on a purposely built PV module integrated noninverting buck–boost converter. The experiments reveal a sensible improvement of the voltage regulation during mode transition, confirming the effectiveness of the proposed technique and its fitness for the PV application. [ABSTRACT FROM AUTHOR]

Five-level hybrid-clamped (5L-HC) converter is a newly proposed topology which is suitable for high-performance medium-voltage high-power conversions without switches directly connected in series. The critical issue of this converter is that two flying capacitor voltages of each phase and two neutral-point potentials of the dc-link need to be balanced. This paper presents a decoupled voltage balancing method for this 5L-HC converter based on modified phase-shifted pulse width modulation (PS-PWM) and optimal zero-sequence voltage injection. The voltages across the central dc-link capacitor and two flying capacitors are balanced first by adjusting the width of four PWM signals. Second, the relationship between the neutral-point currents and the output phase voltage is studied and the upper and lower dc-link capacitor voltages are balanced by zero-sequence voltage injection. Both steady-state and dynamic-state simulation and experimental results are presented to confirm the validity of this method. [ABSTRACT FROM AUTHOR]

Presently, the neutral-point potential offset is an inherent problem for three-level converters on three-phase four-wire active power filters. The conventional three-dimensional space vector pulse width modulation (3-D-SVPWM) strategy is adopted as a normal solution to the problem, but the selection of space vector sectors for four-wire converter is both abstract and complicated in practice. This paper proposes a new PWM strategy accordingly to simplify the selection process and the calculation of duration. Compared to the conventional 3D-SVPWM, the proposed method locates the sector of optimal vector directly with the polarity of three-phase reference voltage. Then, by applying voltage–second balance rule, it can perform a fast calculation of the duration and generate PWM signals to control the switching devices’ on/off. As an approach to correct the imbalance dc-link capacitor voltage, this strategy reconstructs the switching sequence. A portion of state O duration is disassembled into states P and N to suppress the neutral-point potential offset. The proposed strategy is validated with a range of experiments. The results indicate that this simplified PWM strategy can effectively reduce the computational burden, and also the dc-link capacitor voltage is well controlled. [ABSTRACT FROM PUBLISHER]

This paper proposes a new control method of a direct ac-to-ac converter consisting of two half-bridge converters and a series-resonant circuit. This circuit converts the ac input power from the utility grid to a high-frequency ac output without any dc stage. This circuit does not require a diode bridge rectifier and, thus, makes it possible to reduce forward voltage drops and power losses in the diodes. A new switching sequence for phase-shift control is proposed to regulate the capacitor voltage in each half-bridge converter and to achieve both zero-voltage switching and synchronous rectification. The proposed phase-shift control is theoretically discussed and is also verified by experimental setup using superjunction power MOSFETs. As a result, the proposed direct ac-to-ac converter exhibits a good power conversion efficiency as high as 97.7% at the rated power of 1.3 kW. [ABSTRACT FROM PUBLISHER]

GaN power switches provide remarkable performance in terms of power-density, reduced parasitics, and high-thermal handling capability that enable the realization of very efficient and compact dc/dc converters. Despite exhibiting state-of-the-art channel conductivity, GaN high electron mobility transistor (HEMT) devices are affected by the degradation of the dynamic on-Resistance (RON) at increasing off-state voltages and operative temperatures. In this paper, a novel laboratory setup and characterization procedure for the dynamic RON of GaN HEMT switches in the presence of thermal- and trapping-effects is presented. The proposed setup allows the study of RON transients after the switching event at variable off-state voltages and temperatures. The use of custom-designed differential amplification stages and a voltage-controlled current source enables the accurate characterization of RON even on large periphery devices. At first, the proposed setup is tested with a well-established and mature device technology such as a Si MOSFET. Degradation of the RON up to 120% due to temperature variation is observed with the presented setup. The setup is then used for the characterization of commercial-grade GaN-on-SiC and GaN-on-Si HEMTs. For both technologies dynamic RON degradations up to 75% and 20% are observed for temperature and off-state voltage variations, respectively. These characterization data are fundamental for the accurate estimation of conduction losses during the design of switching-mode power converters. [ABSTRACT FROM PUBLISHER]

Primary side regulation (PSR) technology has the characteristics of lower cost and standby power losses. However, there is no algorithm suitable for discontinuous conduction mode (DCM) and continuous conduction mode (CCM) operations of primary side control for flyback converter because of the difficulty in estimating the output voltage correctly. In this paper, a PSR control algorithm suitable for DCM/CCM flyback converter is proposed and implemented with digital micro controller. The voltage drop on the secondary winding and output diode at CCM operation is compensated by sensing the secondary side current at the instant when primary side switch is being turned-on. The secondary side current is zero at the voltage sensing instant and equal to the current at the instant when primary side switch is being turned-on as flyback operated at DCM. In addition, the proposed algorithm can be used to regulate either the output voltage or current very well. An experimental prototype with 150 W rated power is built to verify the feasibility of the proposed control. Experimental results show that the output voltage can be controlled with error less than 0.25%, and the output current error is less than 5%. The conversion efficiency is up to 92.8%. [ABSTRACT FROM PUBLISHER]

A capacitor voltage balancing method for a modular multilevel dc (MMDC) converter is proposed. The MMDC inherits the desirable features of both a modular multilevel converter (MMC) and a dual active bridge, namely high voltage capability, fault tolerance, zero-voltage switching-on of all the power devices, and a wide operating range. These features are ideal for a dc transformer in any dc distribution system. One key MMDC control issue is balancing of submodule capacitor voltages. Conventional MMC balancing techniques cannot be used as arm currents of an MMDC change direction within each switching cycle. This paper establishes that the average capacitor voltage of each arm is self-balanced and proposes a method to balance voltages within an arm by assigning the gate signals with higher charge difference to the submodules with lower voltages and vice versa. Charge difference is obtained by the voltage difference, hence only the SM capacitor voltages are required for balancing control. Different from the existed methods, the proposed technique is not limited by voltage gain or load conditions. Simulation and experimental results show that capacitor voltages are balanced under different voltage gains, different output power, and also when the MMDC starts up, hence ensuring the stable MMDC operation. [ABSTRACT FROM PUBLISHER]

The voltage balancing of the floating capacitors in modular multilevel converter (MMC) is of great importance for the safe operation. However, the existing voltage-balancing algorithms usually suffer from high switching frequency, leading to unnecessary switching losses and device costs. This paper proposes an adaptive capacitor voltage-balancing method for high-power MMCs with reduced switching frequency. The operational characteristics and switching process of the submodules (SMs) are analyzed in detail. And then the relationship between the switching frequency and the capacitor voltage deviation is derived. Based on the analysis, an adaptive method is proposed to make a trade-off between the switching losses and the balancing effect through a closed-loop control of the alternating number of the SMs. The calculation formulas of the switching frequency are also presented. PSCAD/EMTDC simulation and RT-LAB-based real-time control hardware in the loop (HIL) test results demonstrate the effectiveness of the proposed method under different operating conditions. [ABSTRACT FROM PUBLISHER]

In this paper, a class of single-phase Z-source (ZS) ac–ac converters is proposed with high-frequency transformer (HFT) isolation. The proposed HFT isolated (HFTI) ZS ac–ac converters possess all the features of their nonisolated counterparts, such as providing wide range of buck-boost output voltage with reversing or maintaining the phase angle, suppressing the in-rush and harmonic currents, and improved reliability. In addition, the proposed converters incorporate HFT for electrical isolation and safety, and therefore can save an external bulky line frequency transformer, for applications such as dynamic voltage restorers, etc. The proposed HFTI ZS converters are obtained from conventional (nonisolated) ZS ac–ac converters by adding only one extra bidirectional switch, and replacing two inductors with an HFT, thus saving one magnetic core. The switching signals for buck and boost modes are presented with safe-commutation strategy to remove the switch voltage spikes. A quasi-ZS-based HFTI ac–ac is used to discuss the operation principle and circuit analysis of the proposed class of HFTI ZS ac–ac converters. Various ZS-based HFTI proposed ac–ac converters are also presented thereafter. Moreover, a laboratory prototype of the proposed converter is constructed and experiments are conducted to produce output voltage of 110 Vrms / 60 Hz, which verify the operation of the proposed converters. [ABSTRACT FROM AUTHOR]

In this paper, a novel converter is presented to improve the excitation process in switched reluctance generators (SRGs). Accumulator capacitor converter (ACC) is based on a singular scheme of flyback converters. ACC performs two main roles. First, in an initial step, it charges an accumulator capacitor with a determined value of voltage; then, during the magnetizing period, it discharges the stored energy into machine coils. Therefore, ACC provides the SRG with a determined magnetizing energy and uses the forced magnetizing phenomenon to magnetize its coils. The processes yield some outstanding superiority such as excellent operation at high speeds, simple controlling scheme, lower stress on the excitation source, etc., over conventional converters. To analyze the performance of ACC, the required analytical expressions for charging the capacitor and discharging it into the coils are developed and the constraints for switching periods are demonstrated in detail. Afterward, through MATLAB/Simulink and finite-element analysis (FEA) simulations, its operation is evaluated and compared to conventional asymmetric bridge and bifilar converters (BFCs); moreover, its test bed is assembled and tested experimentally, and its results, along with the simulation ones, validates ACC performance. [ABSTRACT FROM PUBLISHER]

DC–DC converters with voltage boost capability are widely used in a large number of power conversion applications, from fraction-of-volt to tens of thousands of volts at power levels from milliwatts to megawatts. The literature has reported on various voltage-boosting techniques, in which fundamental energy storing elements (inductors and capacitors) and/or transformers in conjunction with switch(es) and diode(s) are utilized in the circuit. These techniques include switched capacitor (charge pump), voltage multiplier, switched inductor/voltage lift, magnetic coupling, and multistage/-level, and each has its own merits and demerits depending on application, in terms of cost, complexity, power density, reliability, and efficiency. To meet the growing demand for such applications, new power converter topologies that use the above voltage-boosting techniques, as well as some active and passive components, are continuously being proposed. The permutations and combinations of the various voltage-boosting techniques with additional components in a circuit allow for numerous new topologies and configurations, which are often confusing and difficult to follow. Therefore, to present a clear picture on the general law and framework of the development of next-generation step-up dc–dc converters, this paper aims to comprehensively review and classify various step-up dc–dc converters based on their characteristics and voltage-boosting techniques. In addition, the advantages and disadvantages of these voltage-boosting techniques and associated converters are discussed in detail. Finally, broad applications of dc–dc converters are presented and summarized with comparative study of different voltage-boosting techniques. [ABSTRACT FROM AUTHOR]

This paper proposes a novel structure for fault current limiter (FCL), which not only controls the magnitude of fault current, but also is enable to power management in normal and fault condition of utility. The main capabilities of the proposed structure, which is able to connect both ac and dc systems, are controlling the dc reactor current for fault current magnitude control, and management and control of power flow from ac system to dc system. A boost converter is utilized in the proposed structure, that its output is connected to a dc bus, in order to control the dc reactor current. The proposed FCL, which ensures a high protection level of the system, has no impact on utility voltage and load currents. A boost converter is utilized to provide an almost sinusoidal input current. The simulation and experimental results are presented to clarify the theory and feasibility of the proposed FCL, which manifest simple structure of the circuit and show feasibility of the proposed FCL. [ABSTRACT FROM PUBLISHER]

The objective of this paper is to propose an efficiency model to evaluate the impact of the pulse width modulation (PWM) duty cycle jitter on the efficiency of switching-mode power converter. By taking the product of two perturbation terms into consideration, which is ignored in the conventional average small-signal model, the average efficiency model is proposed first. Due to the nonlinear characteristic of the PWM generator, the multifrequency efficiency model is also developed by considering the sideband frequency. Three different perturbation waves are induced to the control loop of the converter to generate the jitter to observe its impact on the efficiency. The mathematical expression of the efficiency drop based on the proposed multifrequency model is derived. The reason of control-to-output gain's magnitude spike on the Bode plot can be explained by the derived equations. Eventually, the methods to reduce the efficiency drop caused by the jitter are suggested. In spite of various perturbation frequencies, amplitudes, and waveforms, the mathematical calculation, the computer simulation, and the hardware measurement of the efficiency drop are consistent which validate the accuracy of the proposed multifrequency efficiency model. [ABSTRACT FROM AUTHOR]

Power systems for exploration rovers tend to be complex as three separate converters are necessary; in addition to a main dc–dc converter and cell equalizer for rechargeable energy storage cells, an equalizer for photovoltaic (PV) modules is desirably equipped in order to preclude negative impacts of partial shading. This paper proposes the pulse width modulation (PWM) converter integrating voltage equalizers for PV modules and energy storage cells. The proposed integrated converter comprises a switched capacitor converter, PWM buck converter, and series-resonant voltage multiplier that perform PV equalization, power conversion from the PV modules to the load, and cell equalization, respectively. Three converters can be integrated into a single unit with reducing the total switch counts, achieving not only system-level but also circuit-level simplifications. The derivation procedure of the integrated converter is explained, followed by the operation analysis. Experimental tests were performed using series-connected supercapacitor (SC) modules and solar array simulators to emulate a partial shading condition. With the integrated converter, the extractable maximum power from the PV modules significantly increased while voltage imbalance of SC modules was adequately eliminated, demonstrating the integrated performance of the proposed converter. [ABSTRACT FROM AUTHOR]

Dead time significantly affects the reliability, power quality, and efficiency of voltage-source converters. For silicon carbide (SiC) devices, considering the high sensitivity of turn-off time to the operating conditions (> 5× difference between light load and full load) and characteristics of inductive loads (> 2× difference between motor load and inductor), as well as large additional energy loss induced by the freewheeling diode conduction during the superfluous dead time (∼15% of the switching loss), then the traditional fixed dead time setting becomes inappropriate. This paper introduces an approach to adaptively regulate the dead time considering the current operating condition and load characteristics via synthesizing online monitored turn-off switching parameters in the microcontroller with an embedded preset optimization model. Based on a buck converter built with 1200-V SiC MOSFETs, the experimental results show that the proposed method is able to ensure reliability and reduce power loss by 12% at full load and 18.2% at light load (8% of the full load in this case study). [ABSTRACT FROM AUTHOR]

Dynamic voltage restorer (DVR) technology has become a mature power quality product. In high-power applications, DVR using a multilevel converter is commonly used. However, DVR using a multilevel direct pulse width modulation (PWM) ac–ac converter has not been well studied. This paper presents a new DVR topology using a cascaded multilevel direct PWM ac–ac converter. In the proposed scheme, the unit cell of the multilevel converter consists of a single-phase PWM ac-ac converter using switching cell structure with coupled inductors. Therefore, the multilevel converter can be short- and open-circuited without damaging the switching devices. Neither lossy RC snubber nor a dedicated soft commutation strategy is required in the proposed DVR. This improves the reliability of the DVR system. The output voltage levels of the multilevel converter increase with the number of cascaded unit cells, and a high ac output voltage is obtained by using low-voltage-rating switching devices. Furthermore, a phase-shifted PWM technique is applied to significantly reduce the size of the output filter inductor. A 1-kW prototype of single-phase DVR is developed, and its performance is experimentally verified. Finally, the simulation results are shown for a three-phase DVR system. [ABSTRACT FROM AUTHOR]

This paper proposes two direct torque control (DTC) strategies to reduce the common-mode voltage (CMV) in the five-phase induction motor driven by three-level five-phase inverter. In each technique, 31 voltage vectors consisting of 30 nonzero voltage vectors, and a zero voltage vector are selected out of available 243 voltage vectors. The selection of these voltage vectors are based on their capabilities of reducing the CMV, eliminating the x–y stator flux and maintaining the torque ripple under control. The ten large, ten small, and a zero voltage vector are same in both schemes, however only difference in designing the control strategy for the two schemes is the utilization of different ten medium voltage vectors. First proposal (DTC-I) reduces the CMV to $3V_{{\rm{dc}}}\,/ 10$ and second proposal (DTC-II) reduces to $V_{{\rm{dc}}}\,/ 10$. These schemes are compared with DTC technique of five-phase induction motor fed by two-level five-phase inverter in order to judge the capabilities of proposed schemes in context of reducing the CMV. The simulation and experimental results validate the proposed DTC techniques. [ABSTRACT FROM AUTHOR]

Current control loop response in voltage source inverters impacts the quality of output current and output voltage waveforms. Parabolic current control provides a fast transient response with approximate-constant switching frequency, solving the frequency variation problem of hysteresis current control. This makes it a good candidate for the current control loop of voltage source inverters to achieve a good system performance. Yet, parabolic current control is often implemented with digital-to-analog converters, analog comparators, and field-programmable gate array circuits where increasing switching frequency pushes update speed and bandwidth requirements. Concurrently, even if the transient response of parabolic current control is fast, it can still take up several switching cycles converging to steady state. In order to solve both problems, a new current control strategy, motivated by the convergence analysis of parabolic current control but with a convergence process that takes just one switching operation, is proposed: single-step current control. Since single-step current control samples two data points in a switching cycle instead of using continuous parabolic carriers, it can be easily implemented in a digital microcontroller then high switching frequency can be achieved. The small signal model, dead-time compensation, and stability analysis are also studied in this paper. The convergence speed of the algorithm is verified with experimental hardware prototype and the transient performance of the designed voltage source inverter meets expectation. [ABSTRACT FROM AUTHOR]

Traditional load regulation methods for a resonant converter mainly rely on frequency modulation. It is always a tradeoff between the design of the resonant network and the range of load. Especially for wireless power transfer (WPT) systems, the resonant network usually has a high quality factor. Small variation on frequency leads to huge drop in gain and efficiency. Due to this problem, many WPT systems are unregulated and they need one or two more front-end stages to regulate the dc bus voltage and perform power factor correction (PFC). In order to lower the cost and complexity of two- or three-stages structure, a single-stage solution with a silicon carbide (SiC) based Z-source resonant converter (ZSRC) was recently proposed. The Z-source network provides high reliability as being immune to shoot-through problems. Additionally, a ZSRC can boost the dc bus voltage while the traditional voltage-source inverter can only produce a lower voltage. However, the load regulation of this new topology has not been addressed. Two effective load regulation methods with constant frequency are presented for this SiC-based ZSRC specifically. Operation principle of the two load regulation methods are described in this paper. Experimental results based on a 200-W scale-down prototype with a full-bridge series resonant dc–dc converter are presented to illustrate the mechanism of these two methods. [ABSTRACT FROM AUTHOR]

This paper presents a primary-side regulation constant current constant voltage (CC-CV) Flyback ac–dc converter characterized by high efficiency and high precision of constant current control. In CC mode, a novel ring detection and demagnetization portion control technique is proposed, with which the ending time of demagnetization can be accurately determined and the portion of demagnetization in switching periods remain precisely the same, which enable the accuracy of constant current output that can reach a level as high as ±0.8%. In CV mode, a power stage model based on steady-state analyzing method is established, according to which the expression of static power loss is first obtained. After that total power loss expression including switching loss is derived as well. By MATLAB simulation, power loss mechanism is revealed and analysis is made in detail. According to which, optimized parameters of Flyback converter system and an effective CV regulation strategy are obtained eventually. Simulation as well as experimental results verifies the efficiency of the ac–dc converter system after optimization that can be more than 84.7% at 5 V/1 A application. [ABSTRACT FROM PUBLISHER]

To solve the problem of the mismatched voltage levels between the dynamic lower voltage of the fuel cell stack and the required constant higher voltage (400 V) of the dc-link bus of the inverter for fuel cell vehicles, a boost three-level dc–dc converter with a diode rectification quasi-Z source (BTL-DRqZ) is presented in this paper, based on the conventional flying-capacitor boost three-level dc–dc converter. The operating principle of a wide range voltage-gain for this topology is discussed according to the effective switching states of the converter and the multiloop energy communication characteristic of the DRqZ source. The relationship between the quasi-Z source net capacitor voltages, the modulation index, and the output voltage is deduced and then the static and dynamic self-balance principle of the flying-capacitor voltage is presented. Furthermore, a boost three-level dc–dc converter with a synchronous rectification quasi-Z source (BTL-SRqZ) is additionally proposed to improve the conversion efficiency. Finally, a scale-down 1.2 kW BTL-SRqZ prototype has been created, and the maximum efficiency is improved up to 95.66% by using synchronous rectification. The experimental results validate the feasibility of the proposed topology and the correctness of its operating principles. It is suitable for the fuel cell vehicles. [ABSTRACT FROM PUBLISHER]

This paper proposes a current-fed isolated bidirectional dc–dc converter (CF-IBDC) that has the advantages of wide input voltage range, low input current ripple, low conduction losses, and soft switching over the full operating range. Compared with conventional CF-IBDCs, the voltage spikes of the low-voltage (LV) side switches in the proposed converter can be eliminated without additional clamp circuits. The converter adopts the pulse width modulation plus hybrid phase-shift control scheme such that the bus voltage can match the output voltage by means of the transformer. Thus, the current stresses and conduction losses of the converter become lower. In addition, the practical zero voltage switching (ZVS) of the secondary-side switches can be realized by adjusting the phase-shift angle within the secondary side when in light load or no load condition. The operating principles and characteristics including the power transfer, root-mean-square (RMS) current, and soft switching are investigated in detail. Then the design guidelines of inductors are also given. Finally an experimental prototype with 30–60 V input and 400 V/2.5 An output is built to verify the correctness of theoretical analyses. [ABSTRACT FROM PUBLISHER]

The paper presents a new bridgeless power factor correction (PFC) topology, using a recently proposed controllable LCL filter, namely active virtual ground to achieve efficient power conversion, and high-frequency common mode voltage (CM) reduction. The proposed PFC circuit consists of high-frequency semiconductors for shaping inductor current and low-frequency semiconductors to form two different LCL structures for different conditions. This reduces grid differential mode current ripple or inductance. Besides, the PFC CM voltage, a main problem of bridgeless PFCs, is significantly reduced, since the capacitor in the LCL filter clamps the voltage between the grid and the converter ground. The performance of the proposed PFC is experimentally verified. The results show that the proposed PFC guarantees sinusoidal input current, low high-frequency common-mode voltage noise, and has a good agreement with the theoretical findings. [ABSTRACT FROM AUTHOR]

The three-level flying capacitor (3L-FC) submodule significantly reduces the magnitude of circulating currents, voltage ripple, and footprint size and improves the efficiency of the modular multilevel converter (MMC). Due to the above advantages, the 3L-FC submodule becomes an alternative for the conventional half-bridge submodule in the MMC. Each 3L-FC submodule consists of two floating capacitors with different nominal voltage rating. The precharging of floating capacitors without inrush current is one of the major challenges in the 3L-FC-based MMC. This paper proposes a sequence of design steps to precharge the floating capacitors in the 3L-FC-based MMC. The proposed approach is highly effective to charge the outer and inner capacitors of each 3L-FC submodule to their nominal value. The superiority of the proposed approach is verified through the MATLAB simulations and dSPACE/DS1103 experiments on a laboratory prototype of the 3L-FC-based MMC. [ABSTRACT FROM AUTHOR]

In signal injection sensorless drives, the injection voltage cannot be reduced under a certain value. The lower limit of the injection voltage is mainly enforced by the inverter nonlinearity that causes distortion of the injection voltage and degradation of the position estimation performance. After analyzing the inverter nonlinearity during the voltage injection, it is revealed that parasitic capacitances of insulated-gate bipolar transistors have positive effects on inverter output linearity and sensorless control. Based on this analysis, this paper proposes a method to reduce the injection voltage by connecting additional capacitors to the output terminals of the inverter. Simulation and experimental results are provided to verify the effectiveness of the proposed idea. In the experiments, using the capacitor-integrated inverter, it is shown that the injection voltage can be reduced by more than half without degrading the position estimation performance. [ABSTRACT FROM AUTHOR]

To solve some problems caused by the ac control method used for the existing modular multilevel dc–dc converter (MMDC), this paper has proposed a new MMDC topology with a wide range of output voltage by means of dc control. By reconstructing the submodule structure, the converter has a power branch and an auxiliary balance branch, which are used to transmit dc power and balance the capacitor voltage, respectively. Both dc analysis and control method are adopted to establish a mathematical model so as to deduce the mathematical relationships between the key electrical parameters. Moreover, what have been done include analyzing the self-balancing principle of the capacitor voltage and the mechanism of the auxiliary balance branch, calculating the related parameters of the capacitor voltage fluctuation, and presenting a dc closed-loop control strategy based on a small-signal model. The analyses of the steady and dynamic states in combination with simulation and experiment show that the proposed converter can stably operate in the mode of dc control, with a large adjustable range of output voltage, a small fluctuation in voltage of the capacitor, and the ability of the inductor to suppress the spike of the auxiliary balance current effectively so as to reduce the impact on the device. [ABSTRACT FROM AUTHOR]

Isolated modular multilevel dc–dc converter (IMMDCC), which consists of two modular multilevel converters and a medium-frequency transformer, is attractive for medium-voltage applications because of the following features: the modular structure can handle higher voltage, and synthesizing square-wave voltages toward the alternating current (ac) link increases the dc voltage utilization ratio and achieves the zero-voltage switching operation. However, the asymmetry of arm impedance in practice inevitably leads to power imbalance and divergence of total capacitor voltages in the upper and lower arms of IMMDCC, thereby inducing large ripples in the common-mode arm current and adding a dc bias to the synthesized ac voltage. To compensate for the power imbalance and maintain the stable operation, the interarm phase-shift modulation (IAPSM) scheme and arm voltage-balancing control strategy based on this scheme are presented in this paper. Combining the IAPSM scheme with the intersubmodule phase-shift modulation scheme, deep rising and falling edges of the synthesized square-wave voltage in each phase leg are modified into staircase waveforms with 2N + 1 steps, dv/dt in the ac-link is thus significantly reduced. Simulation and experimental results validate the theoretical analysis and control strategy. [ABSTRACT FROM AUTHOR]

With the rapid development of modern electrified railway, negative-sequence current minimization is one of the most important considerations in the high-speed railway traction system. In the past, many multiple or multilevel topologies with high compensation capacity have been introduced for railway power conditioner (RPC). This paper presents a simplified quantitative comparison of five previous modular RPC topologies for negative sequence compensation in V/V and SCOTT traction systems, aiming for an optimal selection of the compensators. Performance criteria such as transformer requirement, voltage stress and current stress of a power switch, numbers of the power switches and capacitor are derived by analytical methods. Moreover, the numerical comparison of operating controllers is completed for modular RPCs. In addition, power losses of five modular RPCs are obtained by theoretical analysis, IPOSIM calculation as well as PSIM simulation. These calculations are validated via simulations results in PSIM. The main conclusion is that presented modular RPCs can be divided into general purpose RPC and special purpose RPC in terms of the behavior and efficiency. It is helpful to choose the appropriate topology for specific applications. [ABSTRACT FROM AUTHOR]

This paper proposes a zero-ripple input-current high-step-up boost–single ended primary inductor converter (SEPIC) dc–dc converter with reduced switch-voltage stress to overcome some drawbacks of the conventional cascaded boost–SEPIC dc–dc converter. In the proposed converter, the input current ripple is significantly removed by the auxiliary circuit at the boost stage and the voltage gain is more increased by using turn ratio of a coupled inductor at the SEPIC stage. Additional, the switch-voltage stress is reduced due to the clamping circuit, and the reverse-recovery problem of the output diode is alleviated by the leakage inductor. Hence, the low-voltage-rating MOSFET, which has low $R_{{{\rm ds(on)}}}$, can be utilized as a main switch device. Therefore, the total power efficiency is improved. The theoretical analysis of the proposed converter is verified on an output 200-V to 200-W prototype. [ABSTRACT FROM AUTHOR]

This paper proposes a soft-switched interleaved boost converter with minimal conduction loss increment and removed reverse-recovery problem. The soft-switching operation is enabled by a soft-switching cell composed of passive components in which an auxiliary coupled inductor and a dc-link capacitor are connected between the switch legs of the interleaved boost modules and output stage. Every MOSFET switch of the proposed boost converter operates with zero-voltage switching turn-on using the coupled inductor current. Consequently, the switching loss of the proposed interleaved boost converter is greatly reduced. In addition, the reduced circulating current in the auxiliary circuit minimizes the increment of the conduction loss. The proposed soft-switched interleaved boost converter operation is verified with 500-W experimental results. [ABSTRACT FROM AUTHOR]

Distributed energy resources (DERs) are expected to provide ancillary functions including reactive power generation and harmonics compensation. Meanwhile, multilevel inverters and two-level converters with optimal pulsewidth modulation (OPWM) will be commonly used for DERs at high power levels. The challenge is to realize harmonic compensation with limited switching angles. This paper presents an online solution to realize the selective harmonics compensation (SHC), and power generation with DERs. For harmonics compensation, the selective harmonic components in the load current are detected. Then, the harmonic voltages are provided with DERs to cancel out these detected components. Since the power converter is requested to realize both harmonics filtering and power generation, limitations on harmonics compensation at the given power are discussed. Power hardware-in-the-loop-based online verifications are shown at the end of the paper. [ABSTRACT FROM AUTHOR]

An interline dynamic voltage restorer (IDVR) is invariably employed in distribution systems to mitigate voltage sag/swell problems. An IDVR merely consists of several dynamic voltage restorers (DVRs) sharing a common dc link connecting independent feeders to secure electric power to critical loads. While one of the DVRs compensates for the local voltage sag in its feeder, the other DVRs replenish the common dc-link voltage. For normal voltage levels, the DVRs should be bypassed. Instead of bypassing the DVRs in normal conditions, this paper proposes operating the DVRs, if needed, to improve the displacement factor (DF) of one of the involved feeders. DF improvement can be achieved via active and reactive power exchange (PQ sharing) between different feeders. To successfully apply this concept, several constraints are addressed throughout the paper. Simulation and experimental results elucidate and substantiate the proposed concept. [ABSTRACT FROM AUTHOR]

Full-bridge single-stage (FBSS) ac-dc converters allow to regulate both the output voltage and the input current that achieves a near sinusoidal waveform using only the four bridge transistors. Independent of this feature, these converters still need to be optimized in order to become an interesting and attractive solution for modern switch mode power supplies with power factor corrector (PFC) function. One of the most important improvements needed is the downsizing of the dc bus capacitor C b with the inherent cost reduction. However, this action introduces complex issues in the regulation of the input current and it is also responsible for the generation of high output voltage ripple. The new contribution of this paper consists in the introduction of a set of power circuit optimizations and control techniques in a FBSS PFC converter that solves the referred issues in order to enable the reduction of the dc bus capacitor's size and cost. These procedures are based in the use of a free wheeling circuit that improves the light load operation and in the application of one shot nonlinear modulator, in order reduce the output voltage ripple even when the dc bus ripple is high. The possibility of using, in the proposed topology, a reduced ratio capacitance/watt lower than the typical values used in commercial applications (0.7-0.5 μF/W for 385-450 V, respectively), while maintaining the accurate input current regulation, is also theoretically proved. The developed concepts, solutions and design criteria are detailed described in the paper. The correspondent theoretical study is verified trough experimental results token in an optimized FBSS topology prototype. [ABSTRACT FROM AUTHOR]

The five-level active neutral-point-clamped (5L-ANPC) converter has been widely studied for its excellent performance in high-power medium-voltage applications. This paper analyzes the space vector pulse width modulation (SVPWM) strategy of the 5L-ANPC converter in the virtual coordinate, and presents an optimized control strategy which can balance the neutral point (NP) voltage and avoid the dead-time effects for the first time. In this strategy, on one hand, the 125 space vectors are combined by 96 triangles in the seven-segment vector synthesis method, then the triangles are divided into seven categories which have different characteristics of balancing the NP voltage, and every category has its own principles to choose the vector sequence and compute the vector durations. On the other hand, the dead-time effects of the 5L-ANPC converter are studied in detail and the transitions between different switching states are constrained in the optimized control strategy to avoid the dead-time effects that cannot be compensated by traditional pulse-based dead-time compensation methods. Finally, the optimized SVPWM strategy is experimentally verified in this paper. [ABSTRACT FROM AUTHOR]

PWM techniques for a full-bridge dc/dc converter are investigated and a new random PWM technique is proposed in this paper. Three PWM techniques with constant switching frequency are discussed and the related random PWM techniques which spread the harmonic clusters and give constant average inductor current to reduce the output voltage ripple are discussed. The pros and cons of three constant switching frequency PWM techniques and the related random counterparts are investigated. Experimental results show that there is a significant efficiency drop of the random PWM technique due to significant increase of switching counts. Therefore, this paper presents a new random PWM technique to significantly reduce the harmonic intensity while not causing relevant impact on the efficiency. An FPGA-based digital-controlled isolated full-bridge dc/dc converter prototype is built to verify the performance of conventional and proposed PWM techniques. The specifications of the converter include the following: input voltage = 400 V, output voltage = 12 V, output power = 528 W, and switching frequency = 100 kHz. Measured efficiency and harmonic spread factor will be used for the evaluation of these PWM techniques. [ABSTRACT FROM AUTHOR]

This paper investigates the problem of low-frequency voltage oscillations that appear at the neutral point (NP) of a three-level neutral-point-clamped (NPC) converter. Starting with a detailed analysis of their origin, the paper derives the minimum amplitude of these oscillations that can be achieved by nearest-vector (NV) modulation strategies. It then proves that the criterion of the direction of dc-link capacitor imbalance, which is commonly adopted by NV strategies for performing the task of capacitor balancing, poses a barrier in achieving this minimum. A new criterion is proposed instead, together with an algorithm that incorporates it into existing NV strategies. For the case of NPC inverters operating as motor drives, the resulting reduction in the amplitude of NP voltage oscillations ranges from 30% to 50%. The approach has the advantage of avoiding the significant increment in switching losses and output voltage harmonic distortion, caused by other methods. Simulations in MATLAB-Simulink are used to illustrate its operation and verify that it offers the claimed benefit. [ABSTRACT FROM AUTHOR]

A digitally controlled low-dropout voltage regulator (LDO) that can perform fast-transient and autotuned voltage is introduced in this paper. Because there are still several arguments regarding the digital implementation on the LDOs, pros and cons of the digital control are first discussed in this paper to illustrate its opportunity in the LDO applications. Following that, the architecture and configuration of the digital scheme are demonstrated. The working principles and design flows of the functional algorithms are also illustrated and then verified by the simulation before the circuit implementation. The proposed LDO was implemented by the 0.18-μm manufacturing process for the performance test. Experimental results show that the LDO's output voltage Vout can accurately perform the dynamic voltage scaling function at various Vout levels (1/2, 5/9, 2/3, and 5/6 of the input voltage V\bf DD) from a wide V\bf DD range (from 1.8 to 0.9 V). The transient time is within 2 μs and the voltage spikes are within 50 mV when a 1-μF output capacitor is used. Test of the autotuning algorithm shows that the proposed LDO is able to work at its optimal performance under various uncertain conditions. [ABSTRACT FROM AUTHOR]

This paper presents analytical expressions for the class-E power amplifier with a shunt inductor for satisfying the subnominal condition and 50% duty ratio. The subnominal condition means that only the zero-current switching condition (ZCS) is achieved, though the nominal conditions mean that both the ZCS and zero-current derivative switching (ZCDS) are satisfied. The design values for achieving the subnominal condition are expressed as a function of the phase shift between the input and output voltages. The class-E amplifier with subnominal condition increases one design degree of freedom compared with that with the nominal conditions. Because of the increase in the design degree of freedom, one more relationship can be specified as a design specification. It is shown analytically that the dc-supply voltage and the current are always proportional to the amplitude of the output voltage and the current as a function of the phase shift. Additionally, the output power capability is affected by the phase shift, and the peak switch voltage has influence on the phase shift as well. This paper gives a circuit design example based on our proposed design expression by specifying the peak switch voltage instead of the ZCDS condition. The measurement and PSpice simulation results agree with the analytical expressions quantitatively, which show the validity of our analytical expressions. [ABSTRACT FROM AUTHOR]

With series insulated-gate bipolar transistor (IGBT) operation, well-matched gate drives will not ensure balanced dynamic voltage sharing between the switching devices. Rather, it is IGBT parasitic capacitances, mainly gate-to-collector capacitance Cgc, that dominate transient voltage sharing. As Cgc is collector voltage dependant and is significantly larger during the initial turn-off transition, it dominates IGBT dynamic voltage sharing. This paper presents an active control technique for series-connected IGBTs that allows their dynamic voltage transition dVce/dt to adaptively vary. Both switch ON and OFF transitions are controlled to follow a predefined dVce/dt. Switching losses associated with this technique are minimized by the adaptive dv /dt control technique incorporated into the design. A detailed description of the control circuits is presented in this paper. Experimental results with up to three series devices in a single-ended dc chopper circuit, operating at various low voltage and current levels, are used to illustrate the performance of the proposed technique. [ABSTRACT FROM AUTHOR]

This paper presents a method of mitigating the transient overshoots of dc-dc converters undergoing large load disturbances. The method involves a small power auxiliary circuit which exists as an energy buffer to provide a smooth absorption and release of excess energy from and to the main dc-dc converter during transients. In the method, the regulation of the current magnitude of the converter and energy storage of the auxiliary circuit are guaranteed by the relevant control schemes. The cost and size of the auxiliary circuit will be relatively small as it only operates intermittently. In this paper, the voltage deviation analysis and the auxiliary circuit design guideline are provided. Experimental results validating the approach are presented. [ABSTRACT FROM AUTHOR]