Search

This paper explores the feasibility of active clamping techniques in isolated time-sharing (TS) multiple-input converters (MICs). Additional losses caused by energy transfer from the leakage inductance in the isolating coupled-inductor into the input switches are addressed with a common active clamping leg for all input legs. An active clamping technique is applied to isolated TS-MIC to minimize the additional switching losses and voltage stresses on input legs. This paper also conducts an operational analysis of an isolated time-sharing dual-input single-ended primary-inductor converter (I-TS-DI-SEPIC) with the discussed active clamping technique. Zero-voltage switching can be achieved on the first-turned-on input leg and the active clamping leg with a proper driving strategy and well-chosen circuit parameter settings. Discussions on the effect of the active clamping technique to an MIC and the components stresses of the I-TS-DI-SEPIC with the active clamping technique have also been made to assist in the design of TS-MICs. Prototypes of the I-TS-DI-SEPIC with the active clamping technique have been built to demonstrate the performance in the application of split-phase dc distribution systems. Converter efficiency and voltage stresses are experimentally verified, showing that the active clamping technique achieves noticeable efficiency gains and component stress reduction. [ABSTRACT FROM AUTHOR]

A synchronous rectification buck converter in parallel with a Class AB linear amplifier is presented in this paper to construct an envelope-tracking (ET) power supply. To eliminate the influences of the output voltage on the linear amplifier output current, a full feedforward of the output-voltage scheme with two feedforward terms is proposed in this paper, which can counteract all the two load admittances of the linear amplifier, respectively, consequently decreasing the linear amplifier output current substantially. An ET power supply prototype with 100-kHz sine-wave tracking, 5-15 V output voltage, and 75-W-peak output power is fabricated and tested in the lab. The experimental results are well in agreement with the theoretical analyses, and the system efficiency is improved significantly. [ABSTRACT FROM AUTHOR]

This paper focuses on the common dc-link voltage between a three-phase diode rectifier and a modular multilevel cascade inverter based on double-star chopper cells (MMCI-DSCC) for a medium-voltage motor drive. This motor drive can be operated even when no capacitor exists on the dc link. However, a nonnegligible, but predictable, amount of switching-ripple voltage occurs on the dc link. This paper achieves modeling and analysis of the switching-ripple voltage, thus making it possible to design a small-sized dc passive filter consisting of series connection of a film capacitor and a damping resistor. A 400-V, 15-kW down scaled system is used to confirm the effectiveness of the analysis and the dc filter. Experimental results show that the switching-ripple voltage can be attenuated satisfactorily by the dc filter, and that the power loss dissipated in the damping resistor is negligible, compared to the rated power of 15 kW. [ABSTRACT FROM AUTHOR]

This paper presents a transformerless static synchronous compensator (STATCOM) system based on hybrid multilevel H-bridge converter with delta configuration. This hybrid multilevel STATCOM is characterized by per-phase series connection of a high-voltage H-bridge converter operating at fundamental frequency and a low-voltage H-bridge converter operating at 5 kHz without any other circuit for dc voltage control. A new control strategy is proposed in this paper with focus on dc voltage regulation. Clustered balancing control is realized by injecting a zero-sequence current to the delta-loop, while individual voltage control is achieved by adjusting the fundamental content of ac quasi-square-waveform voltage of high-voltage converter. A downscaled experimental prototype rated at 100 V and 3 kVA is constructed in author's laboratory. Experimental results show that the hybrid multilevel STATCOM performs satisfactory not only improving efficiency and waveform quality, but also compensating reactive power and negative-sequence current while maintaining dc voltage at the given value. [ABSTRACT FROM AUTHOR]

This paper proposes a pulse-width modulation three-level converter with reduced filter size using two transformers. The proposed converter has many advantages. All switches sustain only the half of the input voltage and since the secondary rectified voltage is a three-level waveform, the output filter inductor can be reduced. Also, because of the power sharing of transformer and reduced output inductor, high efficiency can be obtained. The operational principle, analysis, and design considerations of the proposed converter are presented in this paper. The validity of this study is confirmed by the experimental results from a prototype with 600 W, 500-600 V input, and 60 V output. [ABSTRACT FROM AUTHOR]

Multilevel inverters are receiving more attentions nowadays as one of preferred solutions for medium- and high-power applications. As one of the most popular hybrid multilevel inverter topologies, the five-level active-neutral-point-clamped inverter (5L-ANPC) combines the features of the conventional flying-capacitor type and neutral-point-clamped (NPC) type inverter and was commercially used for industrial applications. In order to further decrease the number of active switches, this paper proposes a seven-switch 5L-ANPC (7S-5L-ANPC) topology, which employs only seven active switches and two discrete diodes. The analysis has shown a lower current rating can be selected for the seventh switch under high power factor condition, which is verified by simulation results. The modulation strategy for 7S-5L-ANPC inverter is discussed. A 1 kVA single-phase experimental prototype is built to verify the validity and flexibility of the proposed topology and modulation method. [ABSTRACT FROM AUTHOR]

This paper proposes a modified proportional resonant (PR) based control scheme for a three-level Vienna rectifier that reduces the input current harmonic distortion [total harmonic distortion (THD)] for harmonic contaminated and unbalanced supply voltage conditions. Low-order current harmonics that are present in the source side currents can be selectively eliminated using this proposed control strategy. In addition, the complete control technique includes the proportional integral (PI) based voltage balancing technique to balance the output voltages of the Vienna rectifier. This method includes the advantages of both hysteresis-based current control (fast transient response) and PI-based vector control (fixed frequency operation) methods. Various computational blocks such as space vector modulation (SVM) block, current/voltage transformation blocks, etc., are not necessary to implement this control method. Therefore, this scheme is relatively easy to implement using inexpensive digital controllers. A 1-kW prototype of the rectifier is built and tested in the laboratory environment using the proposed control method. The converter provides a unity power factor operation with low-current THD at the input side, balances the capacitor voltages, and tracks the voltage reference at the output side. [ABSTRACT FROM AUTHOR]

In order to meet the high performance and efficiency requirements, a new space vector-based discontinuous modulation strategy for neutral-point clamped three-level inverter is presented in this paper. Different from the conventional discontinuous PWM (DPWM) strategies, a new clamping state is applied to synthesize the reference voltage under the condition of low modulation index. The rms value of output current ripple for different clamping states are calculated, and then the distribution of the new clamping state and the other two clamping states adopted in conventional DPWMs is optimized based on the calculation results. The switching sequences are redesigned according to the new distribution of the three clamping states. The output voltage and current, switching loss, neutral-point voltage ripple and the common mode voltage of the proposed DPWM strategy and DPWM0–DPWM3 are compared by simulation and experimental results. The results show that by the use of the proposed strategy, the values of total demand distortion of output current (ITDD) and weighted total harmonic distortion of output voltage (\boldsymbolV{\mathbf{WTHD}}) are the lowest. Furthermore, the product of switching loss and ITDD of the proposed strategy maintains the lowest within a large range of modulation index-load angle plane. It can be concluded that the utilization of the new clamping state and optimal distribution of different clamping states could enhance the output performance of the inverter. Moreover, the high-efficiency requirement can also be realized at the same time. [ABSTRACT FROM AUTHOR]

Different power electronic converter topologies have been investigated to integrate renewable energy systems to the grid. Cascaded multilevel converters with a high-frequency link have emerged as a viable candidate for such applications. Electrical isolation can be provided using a compact high-frequency transformer connected in the link thus avoiding a bulky line frequency transformer. The use of cascaded modules allows the generation of a multilevel voltage having low total harmonic distortion but increases the overall system size. In this paper, a 15-level high-frequency ac-link single-stage asymmetrical multilevel converter for grid integration is proposed. The single-stage conversion approach eliminates the dc-link capacitors, resulting in a reduced footprint. The asymmetrical module voltages are generated by the multiwinding transformer having unequal turns on each of the secondaries. This allows the generation of 15 output voltage levels, using only three modules in each phase. A modulation strategy is proposed to generate multilevel output voltage. The effect of switch nonidealities on the output voltage is analyzed and two compensation techniques are developed to improve the voltage profile. A multiwinding high-frequency transformer is designed and characterized for the proposed converter. The presented concepts are verified by simulation and further validated experimentally on a three-phase 15-level converter prototype. [ABSTRACT FROM AUTHOR]

A variable-on-time (VOT) control scheme for a critical conduction mode (CRM) integrated buck–flyback power factor correction (PFC) converter with high power factor (PF) and low total harmonic distortion (THD) is proposed in this paper. By utilizing the input and output voltage to modulate the on-time of both buck and flyback switches, the input current harmonics can be eliminated and high PF will be obtained. The operating principles of both the conventional constant-on-time (COT) control and VOT control for the CRM buck–flyback PFC converter are analyzed. A 100-W prototype has been built and tested in the lab. The experimental results demonstrate that the THD and PF of the converter with VOT control are greatly improved compared to those with COT control. [ABSTRACT FROM AUTHOR]

Permanent magnet synchronous motor and power electronics-based three-phase inverter are the major components in the modern industrial electric drive system, such as electrical actuators in an all-electric subsea Christmas tree. Inverters are the weakest components in the drive system, and power switches are the most vulnerable components in inverters. Fault detection and diagnosis of inverters are extremely necessary for improving drive system reliability. Motivated by solving the uncertainty problem in fault diagnosis of inverters, which is caused by various reasons, such as bias and noise of sensors, this paper proposes a Bayesian network-based data-driven fault diagnosis methodology of three-phase inverters. Two output line-to-line voltages for different fault modes are measured, the signal features are extracted using fast Fourier transform, the dimensions of samples are reduced using principal component analysis, and the faults are detected and diagnosed using Bayesian networks. Simulated and experimental data are used to train the fault diagnosis model, as well as validate the proposed fault diagnosis methodology. [ABSTRACT FROM AUTHOR]

This part of the paper takes a new look at the stability of the fundamental periodic behavior and the associated subharmonic oscillation boundary in dc–dc switching regulators with fixed-frequency pulse width modulation. After revisiting different approaches applied to a unified reduced-order model of switching regulators, the work presents a novel way of obtaining such a boundary without any simplification nor order reduction. A new simple closed-form condition is then obtained using the new approach, which is valid for different strategies with both trailing edge and leading edge modulation schemes. The critical condition is obtained from the steady-state response using an asymptotic approach without resorting to frequency-domain Fourier analysis or using the monodromy or the Jacobian matrix of the discrete-time model. Unlike the method based on the Fourier series expansion, the proposed method does not require the use of any transform and, most importantly, can be applied to bilinear switching regulators. As a byproduct of the proposed method, a singularity problem that is encountered in steady state, when the system involves integrators in the feedback loop, is addressed and a solution is developed to achieve a closed-form expression in the presence of such integrating feedback loops. [ABSTRACT FROM AUTHOR]

In this paper, a small signal model is proposed for the new unidirectional three-phase T-type rectifier topology known as five-level T-Rectifier (5L T-RECT). The proposed model is obtained starting from the large signal analytical representation of the 5L T-RECT configuration. The derived equations have been simplified using the synchronous reference frame transformation; to this purpose, the average values over the fundamental period T0 are considered for the input phase voltages. After that, the converter steady-state and dynamic models are derived by means of the local linearization around the desired operating point. The transfer functions related to the inputs and outputs of the system are, therefore, obtained and depicted. The achieved 5L T-RECT model has been first verified using the linear analysis tool in the matlab/Simulink environment starting from the detailed switching model. Theoretical results exhibit a very good accuracy between the small-signal, the large-signal, and the switching models. Then, experimental activity is depicted to further validate the proposed small-signal model. [ABSTRACT FROM AUTHOR]

This paper presents a new single-phase switched-coupled-inductor dc–ac inverter featuring higher voltage gain than the existing single-phase qZ-source and semi-Z-source inverters. Similar to the single-phase qZ-source and semi-Z-source inverters, the proposed inverter also has common grounds between the dc input and ac output voltages, which is beneficial especially for photovoltaic inverter systems. The inverter volume and maximum current flowing can be reduced significantly through the coupling of all inductors. A theoretical analysis of the proposed inverter is described and a 280-W experimental prototype is built to verify the performance of the inverter. [ABSTRACT FROM AUTHOR]

This paper proposes a single-phase, single-stage buck–boost inverter for photovoltaic (PV) systems. The presented topology has one common terminal in input and output ports which eliminates common mode leakage current problem in the grid-connected PV applications. Although it uses four switches, its operation is bimodal and only two switches receive high-frequency pulse width modulation signals in each mode. Its principle of operation is described in detail with the help of equivalent circuits. Its dynamic model is presented, based on which a bimodal controller is designed. Experimental results, in stand-alone and grid-connected mode, obtained with a 300-W laboratory prototype are presented to validate its performance. [ABSTRACT FROM AUTHOR]

High-power dc–dc converter is the essential component for connecting the renewable energy sources to medium-voltage dc (MVDC) grids. In this paper, a novel zero-voltage zero-current switching converter with two full-bridge cells sharing a bridge leg and connecting the secondary windings of two transformers in series is proposed for MVDC applications. One big feature of the proposed converter is that the required inductance used for energy transmission is reduced remarkably and even can be embedded in the transformer in some cases. Special but simple control strategy adopted by the converter makes it work in discontinuous current mode, which can realize zero-current switching for the main switches and rectifier diodes in the whole load range. Meanwhile, the auxiliary switches with small current rating can realize zero-voltage switching naturally. Hence, the switching loss is reduced, which is very important for high-power applications. The effects of the turns ratio of auxiliary transformer on the total loss and needed inductance are comprehensively analyzed and proved. With a detailed parameters design procedure, a simulation model is established in the software PLECS and the operation principle of the converter is verified. A 120 V–1200 V/1 kW prototype was built to validate the operation principle of the proposed converter. [ABSTRACT FROM AUTHOR]

In a modular multilevel converter (MMC), the zero-sequence currents at twice the fundamental frequency and its multiples flow through the dc bus and cause dc-bus power fluctuations during unbalanced conditions. These fluctuations appear in dc-bus current, considering that the dc-bus voltage is stiff. In this paper, a model-predictive control is proposed to minimize the ripple in dc-bus current. The proposed approach takes the advantage of internally generated zero-sequence voltage to mitigate the zero-sequence current during unbalanced conditions. To implement the proposed approach, a generalized mathematical model of the MMC, which includes the zero-sequence voltage, is presented. The performance of the proposed approach is verified through MATLAB/Simulink simulations on a 4.16-kV/5-MW system and dSPACE/DS1103-based experiments on a 208-V/3-kW laboratory prototype. [ABSTRACT FROM AUTHOR]

This paper addresses the inverter nonlinearity of a three-level T-type inverter. The main causes of the nonlinearity are pulse shaping, pulse skipping due to narrow pulses for the dead time, and voltage drop of the switching devices. Although the same causes have existed in two-level inverters, the pulse skipping phenomenon and results are quite different in the case of the three-level T-type inverter. The effects of pulse shaping and skipping have been investigated and discussed. In addition, the voltage drop of the switching devices has been considered in conjunction with the conduction path of the T-type inverter. Compensation methods based on the pulse width modulation (PWM) of T-type inverter to alleviate the inverter nonlinearity have been proposed from research results. The proposed methods could be easily implemented by adding appropriate offset voltages to the voltage references of the inverter in PWM. Furthermore, a neutral voltage balancing method of a three-level T-type inverter has been proposed in conjunction with the proposed PWM methods using offset voltage. Through extensive experimental tests, the fifth- and seventh-harmonic components of the current are conspicuously reduced along with the even harmonics. The neutral voltage of the inverter can be balanced effectively with the proposed offset voltage adjustments as well. [ABSTRACT FROM AUTHOR]

A novel isolated dc–dc converter is proposed, using the T-Type topology with zero voltage switching and pulse width modulated with a capacitive output filter. It uses four switches, two of which are subjected to the input voltage, and the other two to half the input voltage. All switches commutate under zero voltage over a wide load range. The proposed converter has the following features: (a) symmetrical operation of the isolation transformer, (b) modulation by pulse width with constant frequency, (c) zero voltage switching, and (d) three-level voltage applied to the primary winding of the transformer. Theoretical analysis, design example, and experimental data for a 2 kW, 400 VDC input, 400 VDC output, and 50 kHz switching frequency laboratory prototype, working in two operating points are included in this paper. The measured efficiency was 95% at 950 W. [ABSTRACT FROM AUTHOR]

The common-mode leakage current should be carefully considered when designing a transformer-less photovoltaic (PV) inverter since the leakage current can cause the output current distortion and increase the operational risk. The unipolar sinusoidal pulse width modulation of the traditional H-bridge inverter can produce the superior output performance but will cause a high-frequency fluctuated common-mode voltage and consequently the nonnegligible leakage current. To attenuate the fluctuation phenomena of common-mode voltage, few neutral-point-clamped (NPC) circuits have been designed to clamp the neutral-point voltage and maintain the common-mode voltage constant. This paper analyzes the equivalent common-mode circuit of single-phase inverters and proposes a generalized design principle of multiterminal NPC circuits, whose unidirectional and bidirectional variations are fully analyzed. Subsequently, two types of single-phase PV inverters with the NPC circuits are proposed. Also, the operational losses and component counts are compared between the proposed topologies and the traditional NPC inverters. The experimental results verified the theoretical findings. [ABSTRACT FROM AUTHOR]

To regulate an output ac voltage in inverter systems having wide input dc voltage variation, a buck–boost power conditioning system is preferred. This paper proposes a novel high-efficiency quasi single-stage single-phase buck–boost inverter. The proposed inverter can solve current shoot-through problem and eliminate PWM dead time, which leads to greatly enhanced system reliability. It allows bidirectional power flow and can use MOSFET as switching device without body diode conducting. The reverse recovery issues and related loss of the MOSFET body diode can be eliminated. The use of MOSFET contributes to the reduction of switching and conduction losses. Also, the proposed inverter can be operated with simple pulse width modulation (PWM) control and can be designed at higher switching frequency to reduce the volume of passive components. The detailed experimental results are provided to show the advantages of the proposed inverter. Efficiency measurement shows that using simple PWM control the proposed inverter can obtain peak efficiency of 97.8% for 1.1-kW output power at 30-kHz switching frequency. [ABSTRACT FROM AUTHOR]

Ripple cancellation LED driver can achieve flicker-free LED driving while maintaining high power factor, high efficiency, and low component cost. It is a very competitive solution compared to a conventional single-stage or two-stage LED driver design. In this paper, a primary-side-controlled ripple cancellation LED driver has been proposed. The voltages of the proposed LED driver are sensed at the primary side by transformer sensing windings. The LED current is also obtained by sensing the primary-side switching current. The entire control circuit is built on the primary side. All the advantages from the existing ripple cancellation LED drivers are maintained while achieving the primary-side control. Based on the proposed circuit, a potential integrated primary-side controller can be designed, which can significantly reduce the component cost and design complexity. A 30-W, 50-V, 0.6-A experimental prototype with a universal input voltage range has been built to verify the proposed LED driver. [ABSTRACT FROM AUTHOR]

This paper presents a new advanced bus-clamped space vector pulsewidth modulation (SVPWM) technique to reduce line current harmonic distortion as well as switching loss. The proposed sequence introduces multiple division of active vector time (MDAVT) in a subcycle. An analysis of optimal subdivision of active vector dwell time is presented. Existing bus-clamping pulsewidth modulation techniques use double-switching clamping sequences, which use only one zero state and apply an active vector twice in a subcycle. The proposed MDAVT-based SVPWM technique presents a hybrid SVPWM technique. The additional switching is added when the fundamental voltage crosses zero. The switching patterns for the other two phases are not changed. The harmonic performance and switching loss characteristics of the proposed hybrid SVPWM techniques over the existing SVPWM is verified with experimental results on a 415-V, 2.2-kW induction motor drive. [ABSTRACT FROM AUTHOR]

This paper presents a matrix-based nonisolated three-phase ac–dc converter with a current-doubler rectifier (CDR) circuit. Buck-type rectifiers are normally used for step-down ac-to-dc conversion. However, for three-phase buck rectifiers, the lower bound of rectified dc voltage is limited as the converter is severely underutilized by operating at lower modulation index. Moreover, at lower modulation index, the rms values of current increases contributing to higher conduction losses. However, by using a matrix (3 × 1) topology followed by a CDR, the desired dc output voltage can be reduced by half. The matrix topology directly converts three-phase line frequency ac voltages into intermediate high-frequency ac voltage which is subsequently, rectified using a CDR to obtain the required output dc voltage. A modified space vector modulation based modulation scheme especially suited for the proposed converter is presented for superior input power quality with reduced power loss. Comprehensive analysis and design of the proposed converter is carried out followed by simulation and laboratory-based experimental tests. Subsequently, the loss analysis of the proposed converter is carried out and a comparative evaluation of the proposed converter with the traditional six-switch buck rectifier is provided to demonstrate the suitability of the proposed converter for large step-down voltage gain. Digital implementation of the proposed modulation scheme is carried out at 40-kHz switching frequency. A hardware prototype of 500 W is developed to validate the theoretical and simulation results. [ABSTRACT FROM AUTHOR]

A series of switched-capacitor (SC) cell balancing circuits is proposed for rechargeable energy storage devices like battery and supercapacitor strings in this paper. Taking a basic SC-based cell balancing unit as an equivalent resistor, the behavioral models of the proposed cell balancing circuits are developed to evaluate their balancing performance. Comparing with existing SC-based cell balancing circuits, the main advantage of the proposed circuits is that their balancing speed is independent of both of the number of battery cells and initial mismatch distribution of cell voltages. In order to improve the operation performance of SC-based cell balancing circuits in the respect of minimizing the equivalent resistance, optimizing methodologies of circuit parameters are introduced by referring the concepts of slow switching limit and fast switching limit as well as inductive switching limit of SC power converters. Simulation and experimental results are provided to verify the feasibility of the proposed cell balancing circuits. [ABSTRACT FROM AUTHOR]

A simple scheme to realize phase-disposition carrier pulse width modulation (PD PWM) for parallel two-level voltage-source converters (2L-VSCs) is presented in this paper. The proposed implementation only uses a single carrier signal and can easily be implemented using a digital signal processor. The operation of the parallel VSCs with the coupled inductor (CI) under the PD PWM is briefly discussed, and the associated dc flux injection problem is investigated. A CI saturation issue during the band transition under the PD PWM scheme is also explored, and the strategy to avoid this problem is presented. In addition, the proposed strategy also maintains a volt–second balance to synthesize desired reference space voltage vector during the band transition. As a result, a smooth transition from one modulation band to the other is ensured without causing disturbances in the line-to-line voltage. The switching losses and the harmonic performance of the proposed implementation are also compared with the commonly used phase-shifted carrier pulse width modulation. The implementation issues are discussed and the experimental results are also presented. [ABSTRACT FROM AUTHOR]

The recently-developed nested neutral-point clamped (NNPC) converter is a four-level converter for medium-voltage high-power applications. It has some merits such as operating over wide voltage ranges (2.4–7.2 kV) without switching devices in series and less diodes or capacitors when compared with classical four-level topologies. But it has severe voltage balancing problems under low output frequency conditions when conventional space vector modulation (SVM) or sinusoidal pulse width modulation (SPWM) is applied, which limits its wide applications. In order to solve this issue, a space virtual-vector modulation (SVVM) along with a voltage balance control (VBC) algorithm is proposed in this paper. It helps reduce the voltage ripples greatly and maintain them within an acceptable region under low output frequency conditions. Therefore, it guarantees even voltage stresses among switching devices and extends the NNPC converter's applications. Principles of the proposed SVVM and VBC algorithms are elaborated in detail, and the voltage balancing performance is investigated and compared with the cases where conventional SVM and SPWM with the same VBC are applied. The relationship curves between voltage ripples and flying capacitance, output power, and output frequency have been explored and compared for both conventional SVM and proposed SVVM. Simulation and experimental results are presented to verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

By using a carrier-based pulse width modulation, this paper presents a developed phase-shift space vector modulation strategy for a nine-switch inverter to overcome one of major drawbacks, i.e., output voltage and current distortion. This is due to the crossover of modulating waves per phase based on the different phase-shift angle between dual terminals. The proposed strategy done by mathematical algorithms based on the critical operating point principle accomplishes in the wide range of phase-shift conditions that contribute in both common- and difference-frequency modes with its expediency of uncomplicated computation and handy implementation. Even more, the identical and nonidentical modulation index techniques are wholly brought up. The feasibility of the proposed strategy is confirmed by results of the simulation directly compared with the experiment, showing in good accordance with the theoretic analysis. [ABSTRACT FROM AUTHOR]

This paper proposes an active current source gate drive (ACSD) method based on voltage controlled current source(VCCS) feedback control strategy for high-power IGBTs. Unlike the common voltage source gate drive, the proposed ACSD method provides constant drive current to charge and discharge an IGBT. With a large gate drive current, high switching speed and low switching losses can be achieved in a power converter. However, a high-current/voltage overshoot occurs. To solve this problem, a feedback current proportional to the \rmdi/ \rmdt or \rmdv/ \rmdt signal is generated to the IGBT gate. Thus, direct control of the net gate drive current is produced. Then, the current/voltage overshoot is controlled with little sacrifice in switching time, and the switching losses are lower than that with the conventional gate drive method operating simply by gate resistance switchover. The operation principle and circuit implementation of the proposed ACSD method are presented. The experimental results from a 1200 V/800 A IGBT module verify the performance of the proposed method. [ABSTRACT FROM AUTHOR]

For the purpose of reducing cost and volume, techniques of reconstructing three-phase currents through a single current sensor have been reported for permanent magnet synchronous motor vector control system. In existing studies, the reconstruction precision is largely affected by the dead zones in space vector PWM plane, which requires additional efforts to compensate the dead zones either by modifying pulse width modulation (PWM) modulation strategy or by phase-shifting of PWM signal. In this paper, a novel zero voltage vector sampling method (ZVVSM) is proposed, which can move the current reconstruction dead zones in low modulation region and sector boundary regions toward the outline of the space vector hexagon without modifying PWM signal. By arranging the single current sensor at a novel position, the proposed method is able to sample current in two zero voltage vectors (ZVV). ZVVSM avoids the complicated algorithms as well as the increase of the switching times, so that it is beneficial to the PMSM drive performance. The proposed method is validated by both simulation and experiments. [ABSTRACT FROM AUTHOR]

Primary-side controlled universal-line flyback converters have been widely used in low-power applications due to their simplicity, low standby power, and low cost. However, conventional OCP schemes normally cause too large a variation in output current when the input voltage varies. This paper proposes a self-compensating OCP circuit to achieve a high-precision constant current at different input voltages which can be used in flyback converters working in discontinues conduction mode. It consists of a CS S/H circuit and a dynamic OCP voltage reference circuit. Compared with conventional OCP circuits, it does not need an extra compensation circuit. To verify the feasibility and performance of the proposed circuit, an IC controller that uses the proposed OCP circuit has been designed and fabricated in 0.35 μm 5-V/40-V high-voltage CMOS technology. Experimental results show that the constant output current precision of the prototype is within ±1% when the input line voltage changes from 85 to 265 Vac. In the common line voltage range (\rm110-220\ Vac ), the output current regulation accuracy can reach a level as high as ± 0.3%. [ABSTRACT FROM AUTHOR]

This paper proposes a five-level active-neutral-point-clamped (5L-ANPC) dc/dc converter for applications in medium-voltage dc grids. A modulation strategy is proposed for the 5L-ANPC dc/dc converter to generate multilevel voltage waveforms, which can effectively reduce voltage change rate \textdv/ dt, reduce voltage stress on the transformer, and thus reduce the electromagnetic interference and increase reliability. An elimination method for the dead time effect is also proposed along with the proposed modulation strategy by employing a switch in series with the flying capacitor, which can effectively eliminate high voltage leaps caused by the dead time effect. In addition, a capacitor voltage control strategy is proposed for the 5L-ANPC dc/dc converter to ensure the balanced flying capacitor voltage and desired five-level voltage waveforms. Finally, simulation and experimental studies are conducted, and the results have verified the proposed converter and control strategies. [ABSTRACT FROM AUTHOR]

Cascaded converters are generally used for medium-voltage (MV) grid-connected applications due to the limitation in the voltage rating of available silicon (Si) power devices. These converters find application in active power filters, STATCOM or as the active front end converters for solid state transformers at the distribution voltage levels. The high voltage wide bandgap semiconductor devices have enabled the grid connected operation of noncascaded converters. This results in high power density, less number of switching devices, and high efficiency for three-phase MV grid interface. This also results in control simplicity without the need for complex dc bus balancing algorithms otherwise needed for cascaded converters. However, such noncascaded, grid-connected converters introduce challenges in maintaining power quality at low currents. This paper investigates the harmonic performance and current distortion of the grid-connected, three-level neutral point clamped converter using 15 kV silicon carbide Insulated Gate Bipolar Transistor (IGBTs). A suitable control scheme for stable harmonic compensation is proposed. The challenges and control performance are explained through frequency domain analysis, simulations, and experimental validation on a developed prototype of the three-phase converter up to 4.16 kV, three-phase MV grid-connected operation. [ABSTRACT FROM AUTHOR]

This paper presents a pulse width modulation strategy for the cancellation of common-mode (CM) voltage generated by three-phase back-to-back two-level inverters. This method theoretically provides complete elimination of the CM voltage by synchronizing all the commutations of one converter with commutations of the other one, so that the overall resulting CM voltage does not vary. The degrees of freedom of this strategy are studied and an experimental implementation is carried out on a 15-kW motor drive prototype to validate the method effectiveness. Taking into account deadtime compensation, measurements in time and frequency domains show that the CM voltage is strongly reduced and that more than 15 dB reduction is achieved in a wide frequency range. [ABSTRACT FROM AUTHOR]

This paper investigates a control method to significantly reduce the low-frequency current oscillation for six-step operation of a three-phase inverter. The six-step operation of an ac electric machine drive system under high speeds has a few advantages compared with pulse width modulation (PWM) operation including reduced switching losses, a better utilization of the dc bus voltage, and an enhanced speed capability. In digital implementation of the six-step control, power electronics may not be able to switch on and off exactly at the zero crossing points of reference voltages, which will result in a dc offset in phase voltages and cause a low-frequency oscillation in phase currents. The low-frequency oscillation will create issues such as higher power losses, lower efficiency, and excessive heat that may demagnetize magnets on the rotor for a permanent magnet synchronous machine. This research presents a control algorithm using asymmetric PWM to ensure that power electronics switch on and off exactly at the reference voltage zero crossing points. Both simulation and experimental results demonstrate the algorithm can reduce the low-frequency oscillation in phase currents by more than 90%. [ABSTRACT FROM AUTHOR]

Multiple output converters (MOCs) are widely applied to applications requiring various levels of output voltages due to their advantages in terms of cost, volume, and efficiency. However, most of the conventional MOCs cannot regulate multiple outputs tightly and they can barely avoid the cross-regulation problem. In this paper, the recently developed time-division multiple control (TDMC) method, which can regulate all of the outputs with a high accuracy, is used for a multiple output battery charger based on the phase-shift full-bridge topology to simultaneously charge three batteries. The proposed charger is able to charge three different kinds of batteries or three of the same kind of battery in different state of charges (SOCs) independently and accurately with the constant current/constant voltage (CC/CV) charge method. As a result, the strict ripple specification of a battery can be satisfied for multiple battery charges without difficulty. In addition, the proposed charger exhibits a high efficiency since the soft switching of all of the switches during the entire charge process can be guaranteed. The operating principle of the converter and the design of the controller, including the state-space average modeling, will be detailed, and the validity of the proposed method is verified through experiments. [ABSTRACT FROM PUBLISHER]

In this paper, average modeling and analysis of a dual-supercapacitor bank, actively balanced by a bidirectional buck–boost converter, is presented. In such a system, natural balancing is achieved when the converter is operated in open loop with 50% duty cycle, eliminating the need for measuring the voltage of each storage device. Nevertheless, excessive currents arise even for slight voltage misbalance because of the highly underdamped nature of the system. In order to remedy this drawback, bidirectional pulse-by-pulse inductor current limitation is introduced, which is equivalent to adding a peak-current-mode-like control loop to the system. Since the duty cycle never exceeds 50%, compensation ramp is not required to maintain stability. On the other hand, while the uncontrolled system dynamics is linear, introducing the current limit mechanism turns the closed-loop dynamics into a nonlinear one, burdening the analysis task and thus calling for suitable average model to perform fast simulations for system analysis. Therefore, dynamical equations of the system are developed in order to derive the switching-cycle-averaged model and reveal the tradeoff between current limit level, balancing time and efficiency for the worst case of imbalance. Simulations and experiments support the presented findings. [ABSTRACT FROM PUBLISHER]

Diode-assisted buck–boost voltage-source inverter achieves high voltage gain by introducing a switch-capacitor based high step-up dc–dc circuit between the dc source and inverter bridge. As for the unique structure, various pulse width modulation (PWM) strategies are developed with regard to the chopped intermediate dc-link voltage. In order to maximize voltage gain and increase efficiency, this paper proposes a novel PWM strategy. It regulates the average value of intermediate dc-link voltage in one switching time period ( Ts) the same as the instantaneous maximum value of three-phase line voltage by controlling the front boost circuit. Then, the equivalent switching frequency of power devices in the inverter bridge can be reduced to 1/3fs (fs = 1/Ts). The operating principle and closed-loop controller design are analyzed and verified by simulations and experiments. Compared with existing PWM strategies, the new control strategy demonstrates less power device requirement and higher efficiency in high voltage gain applications. It is a more competitive topology for wide range dc/ac voltage regulation in renewable energy applications. Furthermore, with new control strategy, the dc-side inductor current and capacitor voltage contains six-time line-frequency ripples. To overcome the undesired influence of low frequency ripples, it is also suitable for 400–800 Hz medium frequency aircraft and vessel power supply system. [ABSTRACT FROM PUBLISHER]

This paper proposes a new method of generating higher number of levels in the voltage waveform by stacking multilevel converters with lower voltage space vector structures. An important feature of this stacked structure is the use of low voltage devices while attaining higher number of levels. This will find extensive applications in electric vehicles since direct battery drive is possible. The voltages of all the capacitors in the structure can be controlled within a switching cycle using the switching state redundancies (pole voltage redundancies). This helps in reducing the capacitor size. Also, the capacitor voltages can be balanced irrespective of modulation index and load power factor. To verify the concept experimentally, a nine-level inverter is developed by stacking two five-level inverters and an induction motor is run using V/f control scheme. Both steady state and transient results are presented. [ABSTRACT FROM AUTHOR]

Back-EMF-based sensorless control of permanent magnet synchronous machines (PMSMs) is preferred in many industrial applications due to its control simplicity and high machine efficiency. Position estimation based on the back-EMF is most reliable in the medium-to high-speed range. For applications where low-speed operation is not required, a simple-structure back-EMF-based sensorless controller coupled with a simple startup procedure offers an attractive low-cost solution. This paper proposes a new startup procedure based on closed-loop current regulation. Compared to the existing methods, the new starting method can work under different load conditions and allows smooth transition from the startup procedure to the back-EMF-based sensorless control mode. In order to determine the successful use of the proposed method in various applications, it stability under different load conditions is discussed in detail. The proposed method is robust when it comes to the motor parameter variation and can be used for both surface-mounted PMSMs (SPMSMs) and interior PMSMs. The method presented in this paper is validated using the experimental results on an SPMSM. A general design guideline is also given. [ABSTRACT FROM AUTHOR]

A new low-power single-stage ac-dc converter is proposed in the paper. The outstanding feature of the converter is that it can operate with a sinusoidal input current and a low primary-side dc bus voltage that is much less variable than that found in other single-stage converters. The operation of the converter is discussed in the paper and its various modes of operation are explained in detail. An analysis of the converter's steady-state characteristics is performed and the results are used in the design of the converter. Experimental results obtained from a prototype converter are also presented. [ABSTRACT FROM AUTHOR]

In this paper, a family of bidirectional dual-input dc/dc converters is proposed to combine a photovoltaic system and battery energy storage system. This family of converters utilizes a full-bridge, or half-bridge current-source circuit, as the primary side, and a quasi-switched-capacitor circuit as the secondary side. Depending on the power level of the primary side and voltage level of the battery, different topologies can be selected. Compared to other bidirectional multiple-input dc/dc converters with galvanic isolation, this family of converters requires less switches and passive components, reduces voltage stress on switches, and realizes soft switching for all switches. The operation principle of the converter is presented, and a power sharing strategy between two input sources is proposed. A 2-kW full-bridge circuit prototype is built in the lab, based on Gallium Nitride (GaN) switching devices. Simulation and experimental results are also presented to verify the theoretical analysis. [ABSTRACT FROM AUTHOR]

Switching common-mode voltage (CMV) generated by the pulse width modulation (PWM) of the inverter causes common-mode currents, which lead to motor bearing failures and electromagnetic interference problems in multiphase drives. Such switching CMV can be reduced by taking advantage of the switching states of multilevel multiphase inverters that produce zero CMV. Specific space-vector PWM (SVPWM) techniques with CMV elimination, which only use zero CMV states, have been proposed for three-level five-phase drives, and for open-end winding five-, six-, and seven-phase drives, but such methods cannot be extended to a higher number of levels or phases. This paper presents a general (for any number of levels and phases) SVPMW with CMV elimination. The proposed technique can be applied to most multilevel topologies, has low computational complexity and is suitable for low-cost hardware implementations. The new algorithm is implemented in a low-cost field-programmable gate array and it is successfully tested in the laboratory using a five-level five-phase motor drive. [ABSTRACT FROM AUTHOR]

Typical algorithms of multidimensional space-vector pulsewidth modulation (SVPWM) divide (n –1) dimensional space into (n–1)/2 subplanes with decoupling matrix or symmetrical component approach. However, the determination of effective sectors and appropriate space voltage vectors takes a heavy computing burden. Taking the five-phase inverter as example, the relationship between the operation time of branch switches and the dwell times of active space vectors in the SVPWM method is analyzed in this paper. Then, the branch space voltage vector (BSVV) corresponding to the individual active branch voltage is defined and the synthesis of other active space voltage vectors using BSVVs is given. Furthermore, only the BSVVs are chosen as the base vectors to synthesize the reference voltage vector, and a novel SVPWM algorithm is present. The operation time of branch switch is deduced, and the equivalence of the normalized load-phase voltages and operation times of branch switches is emphasized and used to analyze the simulation results. The zero-sequence voltage vector is also included in the algorithm as a parameter and its effects on the dwell time of the BSVVs, the modulation index and the common-mode voltage are explicated. Finally, the extension to an n-phase system is discussed. The algorithm eliminates the selection of sectors and proper active space vectors, and can effectively control the dwell time of switches of multiphase inverter. Experimental results proved the feasibility and effectiveness of the algorithm. [ABSTRACT FROM AUTHOR]

To enhance the power quality in the medium/high-voltage distribution power systems, a single-phase unified power quality conditioner (UPQC) based on the modular multilevel matrix converter (M3C) is presented in this paper. The M3C-UPQC is comprised of four identical multilevel converter arms and associated filtering inductors. According to the established equivalent circuit of M3C-UPQC, its operation principle and power balance of each arm are analyzed theoretically, and the parameters’ design for the arm inductance as well as submodule capacitance is studied. Then, an integrated control method for M3C-UPQC in which the dc circulating current is used to balance the instantaneous active power of each arm is proposed to prevent the capacitor voltages from divergence inter- and intra-arms, so as to achieve voltages balance of M3C-UPQC. Finally, the effectiveness of the proposed control method is verified by a prototype rated at 8 kVA. [ABSTRACT FROM AUTHOR]

The Dynamic Current or Dyna-C is a minimal topology for implementing the bidirectional three-phase solid-state transformer (SST). While only two current-source power conversion stages are employed, the Dyna-C SST has features of voltage step up/down, arbitrary power factors, and frequencies between the input and output terminals. In this paper, a compact 50-kVA three-phase SST based on this minimal topology is designed. More specifically, design considerations and practical implementation techniques are presented. Results from experimental measurements are shown and discussed. [ABSTRACT FROM AUTHOR]

Linear small-signal models of a dc–dc converter often ignore switching dynamics; thus such models are insufficient to fully explore the performance objective under large signal transients. Linear/nonlinear hybrid controllers are promising alternatives; however, they require structurally different hardware resources along with extra antiwindup arrangements. This paper proposes a geometric tuning method in a digitally current-mode-controlled buck converter under continuous-conduction mode. This considers a proportional-integral voltage controller along with a load current feedforward in the digital domain, while the inductor current has a traditional analog implementation. This resembles a first-order switching surface with near load-invariant regulation; thus a (fixed) small integral gain is sufficient to minimize the steady-state error. Using phase-plane geometry, the objective is to tune the controller gain in a way to achieve proximate time optimal recovery using a fixed-frequency pulse-width modulator and also to retain the large-signal stability. The effects of parameter variation and finite sampling are analyzed. The proposed tuning is implemented using an FPGA device. [ABSTRACT FROM AUTHOR]

In this paper, a single-phase converter consisting of two legs with four switches, called the $\theta$-converter, is proposed. It has a common ac and dc ground, which reduces common mode currents and removes the need for an isolation transformer, and two capacitors: one across the whole dc bus and the other across the output. The dc bus capacitor provides a direct path for the double-frequency ripple current inherently existing in single-phase converters to return continuously so the output capacitor can be sized very small, only to filter out switching ripples. Moreover, the dc bus capacitor is intentionally designed to store the system ripple energy with large voltage ripples, which reduces its capacitance. Hence, the total capacitance needed and the output voltage ripples are reduced at the same time. This makes it cost-effective to use highly reliable film capacitors instead of bulky and vulnerable electrolytic capacitors. Because of the removed isolation transformers and bulky electrolytic capacitors, the power density and system reliability are improved. In order to properly operate the converter, two independent controllers are designed for the two legs, respectively, to achieve the desired functions and other normal objectives, such as the unity power factor. Experimental results are presented to demonstrate the high performance of the proposed converter. [ABSTRACT FROM AUTHOR]

Differential-mode buck-boost inverters have merits such as reduced switch number, ability to provide voltages higher or lower than the input voltage magnitude, improved efficiency, reduced cost and size, and increased power density, especially in low-power applications. There are five buck-boost inverters that can provide flexible output voltage without the need of a large electrolytic input side capacitor, which degrades the reliability of inverters. The continuous input current of these inverters is appropriate for maximum power point tracking operation in photovoltaic and fuel cells applications. Three of the five inverters can be isolated with high-frequency-link transformers where the common-mode leakage current can be mitigated. However, the performance and control of such converters have not been discussed in detail. In this paper, the five possible single-stage three-phase differential-mode buck-boost inverters with continuous input current are investigated and compared in terms of total losses, maximum ripple current, total harmonic distortion, and device and passive element ratings. In addition, the possible methods are presented for eliminating the input third-order harmonic current, resulting from the stored energy in the passive elements, as well as the output second-order harmonic currents. The ability for isolating the input and output sides of the inverters with a small–high frequency transformers is discussed. A changeable-terminal 2.5-kW bidirectional inverter is used to validate the design flexibility of the inverter topologies, when digital signal processor-controlled. [ABSTRACT FROM AUTHOR]

This paper presents a new space vector modulation (SVM) strategy for matrix converters to reduce the common-mode voltage (CMV). The reduction is achieved by using the switch states that connect each input phase to a different output phase, or the switch state that connects all the output phases to the input phase with minimum absolute voltage. These two types of states always produce lower peak CMV than the others, especially the former ones that result in zero CMV at the output side of matrix converters. In comparison with the existing SVM methods, this strategy has a very similar software overhead and calculation time. Simulation and experiment results are shown to validate the effectiveness of the proposed modulation method in reducing not only the peak value but also the root-mean-square value of the CMV. [ABSTRACT FROM AUTHOR]